A DEFECT SENSITIVITY MEASUREMENT TOOL ENABLING COMPARISON OF MULTILEVEL INTERCONNECTION STRATEGIES Gerard A. Allan, Jane P. Elliott, Anthony J. Walton Dept Electrical Engineering University of Edinburgh Edinburgh EH9 3JL,UK +44 131 650 5602 email
[email protected] EXECUTIVE SUMMARY A tool to measure the defect sensitivity of commercial layout is reported. The EYE tool (Edinburgh Yield Estimator) is based on a previously reported O(N log N) algorithms for the calculation of critical area[1]. The tool has applications in yield prediction, design optimisation and the generation of fault probability maps. EXTENDED ABSTRACT The introduction of multilevel metalization processes brings new challenges to the design and fabrication of high yielding ICs. As much as 50% of yield loss in digital ICs can be attributed to the metalization stages of fabrication. This can be a particular problem when new process technologies such as multilevel interconnect are being introduced. The EYE tool addresses the problem of design for manufacture of IC layout in multilevel interconnect technologies by enabling the extraction of layout defect sensitivity. The EYE tool can perform a number of operations on integrated circuit mask layout. It supports Boolean (and, or, andnot, exor), polygon bloat/shrink, extra material (figure 1(a)) and pinhole (figure 1(b)) critical area operations. The algorithms used have a time complexity of O(N log N) [1, 2] and Node 3 Node 1
Node 1
Node 2
Pinhole Critical Area Node 3 Node 2
(a) Extra Material Critical Area
(b) Pinhole Critical Area
Figure 1: Extra Material and Pinhole Critical Areas are based on line edges and are therefore not restricted to Manhatten layout. A simple script control language is used by the tool to read in mask data (CIF/GDSII) and perform selected operations on the IC layout. The area of original and generated layers such as critical areas can be calculated. Layers can also be output as mask data files for viewing or later processing. The script control strategy enables the tool to be used for any VLSI process or technology.
Relative Probablity of Shorting Faults for Alliance AMD2901 1
AMD2901
Relative Fault Probablity Metal 1 Layer Metal 2 Layer
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Defect Size/Minimum Metal 1 Spacing 1 E6
Areas Susceptible to Pinhole Defects Metal 2 / Metal 1
Area (um2) 0.5 E6
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Metal 1 / Active Metal 1 / Polysilicon
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Figure 2: Extra Material and Pinhole Critical Areas for the Alliance AMD2901 The EYE tool can be used to find the extra material defect and pin-hole critical areas that are used to predict yield and indicate defect sensitivity. Figure 2 shows the some results generated by EYE for a 5000 transistor chip. The result where generated in approximately 90 minutes on a SUN Sparc 20. The tool can also be used for the comparison of defect sensitivities of place and routing algorithms and layout modifications [3]. Figures of merit can be calculated for different layout styles and algorithms in a similar way to that used for yield prediction (figure 2). These results can be used to optimise the layout and also indicate strategies that give the highest rewards for the human/computer
time invested since yield enhancement is subject to diminishing returns. Another useful technique is to highlight the regions of greatest fault probability using fault probability maps of layout. These maps are generated by plotting the critical area of a range of defect sizes colored according to the probability of defect size within the process. Figure 3 shows fault probability maps generated by EYE for layout modifications, similar to those reported by Kuo [4], to enhance the horizontal metal layer of a routing network (example 1 [5]). CONCLUSIONS The EYE tool presented enables fast measurements of layout defect sensitivity. These measurements can be used as metrics of manufacturability both to optimise layout strategy and also provide estimates of process capability. This is particularly important in the development of new processes such as multilevel interconnect allowing manufacturing to produce higher yielding product earlier and in a more predictable way.
Original Channel Routing Layout with Fault Probablity Map
Enhanced Channel Routing Layout with Fault Probablity Map
Figure 3: Fault Probability Maps of Routing Networks Before and After Yield Enhancement REFERENCES [1] G. A. Allan and A. J. Walton. Efficient critical area algorithms and their application to yield improvement and test strategies. In IEEE Workshop on Defect and Fault Tolerance in VLSI Systems, pages 88–96, Montreal, Quebec, Canada, Oct 1994. [2] U. Lauther. An O(N log N) algorithm for Boolean mask operations. In 18th Design Automation Conference, pages 555–560, 1981. [3] G. A. Allan, A. J. Walton, and R. J. Holwill. A yield improvement technique for IC layout using local design rules. IEEE Trans Comp. Aided Design, CAD-11(11):1355–1362, Nov 1992. [4] S. Kuo. YOR: A yield-optimizing routing algorithm by minimizing critical areas and vias. IEEE Trans Comp. Aided Design, 12(9), Sep 1993. [5] T. Yoshimura and E. S. Kuh. Efficient algorithms for channel routing. IEEE Trans Comp. Aided Design, CAD-1(1):25–35, Jan 1982.
