2011 IEEE Symposium on Wireless Technology and Applications (ISWTA), September 25-28, 2011, Langkawi, Malaysia
A Design of 5.2 GHz CMOS Up-conversion Mixer with IF Input Active Balun S.A.Z Murad, M.F Ahmad, M. Mazalan, M.M Shahimin, S.A.A Rais and M.N Norizan School of Microelectronic Engineering Universiti Malaysia Perlis (UniMAP) P.O Box 77, d/a Pejabat Pos Besar, 01000 Kanger, Perlis, Malaysia
[email protected] a critical requirement in RF transceivers and affects the linearity of the overall system. The measurement of linearity includes second-order intercept point (IP2), third-order intercept point (IP3), and 1-dB compression point (P1dB) decrease heavily with the supply voltage and dc biasing current. Therefore, it is a great challenge to achieve high linearity at low power and low voltage. Several linearization techniques were reported in CMOS designs in order to improve linearity such as adopting MOSFET transconductance linearization by multiple gated transistors [6], derivative superposition method [7], and third-order transconductance cancellation [8].
Abstract—This paper presents a high linearity and low power upconversion mixer at 5.2 GHz for wireless applications. The design based on Gilbert-cell active double-balanced mixer with integrated on-chip input active balun. Core mixer employs additional parallel capacitors and the degeneration inductors to obtain high linearity. A designed active balun which converts single-ended input to differential signals for 100 MHz intermediate frequency (IF) is proposed. The up-conversion mixer converts an input of 100 MHz IF signal to an output of 5.2 GHz radio frequency (RF) signal with a local oscillator (LO) frequency of 5.1 GHz. The simulation results indicated that the proposed method shows the conversion gain of 6-dB, the input third order intercept point (IIP3) of 8-Bm, and 2.48-mW power consumption at 1.8-V power supply.
The up-conversion mixer with differential IF, LO and RF signals are commonly used to provide high-quality port-to-port isolation, which cancels both LO-RF and IF-RF feedback [4],[9]. Balun or phase splitter circuits can be used to generate differential output signals, which have balanced amplitude and phase characteristic. There are two types of baluns; i.e passive baluns and active baluns. Passive baluns have advantages of consuming no dc power. However, they are often using many spiral inductors and microstrip line which are lossy and expansive for large physical size [8]. Therefore, active baluns are the best choice due to the characteristics of more acceptable gain imbalance and phase imbalance and occupy a small area in integrated circuit designs [11].
Keywords-component; high gain; up-conversion; mixer; active balun; intercept point; conversion gain
I.
INTRODUCTION
The growing demand for efficient wireless communication systems in the recent years has resulted in intensive efforts to develop single chip transceivers to minimize cost, power dissipation, and chip size using the advanced CMOS technology. Up-conversion mixer is one of the important blocks mainly used to convert an incoming low frequency IF signal to a higher frequency RF signal for reliable transmission in the RF transmitter front-end. The design of mixers forces many compromises between linearity, conversion gain (CG), LO power, noise figure (NF) and power consumption [1]-[2]. Therefore, it is hard to find a suitable mixer topology which can achieve a high linearity, low power, low noise figure, and high conversion gain simultaneously.
In this paper, high linearity and low power up-conversion mixer with additional parallel capacitors and the degeneration inductors is presented. The IF input active balun is also proposed to be integrated with core mixer. To evaluate the performance of the proposed design, a Gilbert-cell mixer based on the proposed method has been designed and simulated with active input balun in 0.18µm CMOS technology. The proposed mixer is very suitable for the application of the high linearity transmitters due to its superior linearity and low power.
The proposed up-conversion mixers have been reported in many CMOS designs based on Gilbert-cell active doublebalanced mixers. This choice provides high-quality port-to-port isolation due to its fully differential structure, which cancels both LO-RF and IF-RF feedback [3]-[4]. It consists of three stages: a transconductance stage, a LO switch stage and an output load stage. The up-conversion mixer is normally operated with a large input signal, thus a high conversion gain is not required, and noise figure is not a key parameter of measurement. Instead, the input linearity should be large and a fully differential architecture is essential to suppress the LO feedthrough at the output [5]. The linearity of a mixer becomes
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II.
CIRCUIT IMPLEMENTATION
Since most of the low frequency IF signals from the baseband section in the RF transceiver front-end are still single-ended, therefore on chip IF balun is required for converting signals from single-ended to differential and vice versa in order to realize fully integrated circuit. In the
1
to improve the linearity. Fig. 2 shows an equivalent smallsignal circuit of a single CS transconductance stage with a parallel capacitor. When a two tone input signal is applied to the CS transconductance stage, by using Volterra series analysis the third-order intermodulation distortion (IM3) can be derived as [6]. Therefore, the IM3 of the CS transconductance stage can be simplified as follows:
proposed design, the core mixer and IF balun are designed and integrated in a single chip. A. IF Input Balun Since the frequency of the IF input signal is relatively low at 100 MHz, the IF input balun is employed the simplest active balun. The low frequency of the signal is more attractive for an active balun than a passive balun due to the much smaller area of the circuit. The simple active balun consists of a FET M1 with resistors (R1 and R2) in the drain and the source is shown in Fig. 1 [11]. This basic structure is limited for low frequency only since at high frequency the parasitic capacitance seriously degrades the performance.
IM 3(2ω 1 - ω 2 ) ∝ 1 + jωC gs Z s (ω)
In equation (3), the magnitude of the IM3 decrease with C gs for the inductive degeneration since the impedance Z s (ω) is
multiplied with the jωC gs , therefore; the jωC gs Z s (ω) term
The amplitude of the two IF outputs can be made equally by properly optimizes the value of resistors R1 and R2. Since it is a follower circuit, the gain is approximately unity at IF have equal output. Therefore, to make sure that the , the following equations are used, output amplitude with where the negative sign in equation (1) indicates that the output at has a 180° phase-shift relative to the input. ⁄ 1
2
1⁄
_
1
1⁄
1
1⁄
Figure 1.
(3)
becomes a negative real value to cancel positive real one value partially. In order to improve linearity, the parallel capacitor Cp is added with the intrinsic GS capacitor C gs without degrading the gain and dissipation high current. The modification of equation (3) with the effect of parallel capacitor Cp can be shown as follows: (4) IM 3(2ω 1 - ω 2 ) ∝ 1 + jω( C gs + C p )Z s (ω) As can be seen from equation (4), the magnitude IM3 can be decreased by an additional capacitor, thus improving linearity. Therefore, with the given impedance Z s , the linearity can be improved by increasing the Cp.
(1) (2)
Schematic of FET IF active balun. Figure 2. An equavalent small-signal circuit of the single CS transconductance stage with parallel capacitor Cp.
B. Core Mixer Linearity is a very important issue because nonlinearity brings many problems such as gain compression, cross modulation and intermodulation, and etc. in RF systems. The third-order intermodulation distortion (IMD3) is the most dominant nonlinearity component and thus most popularly used parameter for measurement [13]. The circuit linearity is limited by MOSFET transistor linearity, which is the commonsource (CS) MOSFET transconductance. In Gilbert-cell mixer topology, the linearity is mostly dominant by the transconductance stage, therefore; it is very important to linearize the MOSFET transconductance stage.
The complete schematic of the proposed up-conversion mixer based on Gilbert-cell double balanced mixer with IF input active balun is shown in Fig. 3. The lower FET differential pair serves as a transconductance stage (M1-M2), converted incoming IF signals from voltage to current. While the upper FETs (M5~M8) act as switching cores to modulate the current provided by M1-M2 transistors, which is doubled balanced topology with the advantages of rejecting the strong LO signals and the even-order distortion products. To make M5~M8 as ideal switches, the transistors are biased in the saturation region close to the triode region. The additional parallel capacitors Cp and the degeneration inductors Ls are employed to obtain high linearity. On-chip capacitors (CDC) are applied to be the DC block to isolate the input or output port from the dc sources. The switching transistors are driven by a LO with -5 dBm power to reach the maximum possible gain and linearity. The load resistors (RL) stacked on the top of
A simple linearity improvement technique is proposed in [14]. However, the technique is employed in a narrow band downconversion mixer. In this paper, the same technique is used and applied in up-conversion mixer. The parallel capacitor Cp with the intrinsic gate-source (GS) capacitor of a transistor is added
2
LO switch is optimized to obtain a low power dissipation and good conversion gain.
The core mixer will up convert the input signal at 100 MHz to 5.2 GHz through a 5.1 GHz LO signal. The simulated conversion gain (CG) versus LO power is shown in Fig. 5. It shows that the proposed mixer can provide CG when LO power is larger than -20 dBm and the maximum gain of 6 dB is obtained when the input power is varied about -10 dBm to -5 dBm. The necessary value of -5 dBm is chosen for LO power in which the CG of 6 dB is obtained for achieving a tradeoff between LO power and CG. Notice that too much LO power can deteriorate the linearity of the switching transistor pairs. Two tone test has been performed for the IIP3 simulation as shown in Fig. 6. IIP3 is set at input frequency 100 MHz and 101 MHz with 1 MHz separation with IF input power and LO power is applied at -40 dBm and -5 dBm, respectively. As can be seen, the IIP3 of 8 dBm is obtained with the output power of 10 dBm. Fig. 7 shows the transient simulation's results with IF signal at 100 MHz and LO signal at 5.1 GHz. The IF power and LO power is -30 dBm and -5 dBm, respectively. Table 1 provides the comparison between simulated results performance of the proposed up-conversion mixer and the most recently published works.
Figure 3.
Complete schematic of proposed up-conversion Gilbert-cell mixer with input active baluns.
III. SIMULATION RESULTS The proposed up-conversion mixer with input active balun is designed by TSMC 0.18-µm CMOS technology, and simulated using Cadence SpectreRF simulator. The effects of the parasitic associated with the spiral inductor, and capacitors were taken into account during simulation. The total bias current consumed by the proposed core mixer is 1.38 mA with supply voltage of 1.8 V. The simulated gain difference and phase difference for low frequency IF FET input active balun is shown in Fig 4. The simulated data show that gain difference is 0.2 dB and the phase difference is 180.6° for two outputs at 100 MHz.
Figure 4.
Figure 5.
The simulated CG versus LO input power.
Simulation of gain difference and phase difference for IF FET balun. Figure 6.
3
The simulated linearity (IIP3) of the proposed mixer.
ACKNOWLEDGMENT The authors wish to express their appreciation to the support and contributions from those who assist in this research especially Universiti Malaysia Perlis (UniMAP) for providing the short term research grant (9009-00002) that enabled the production of this article. REFERENCES [1]
IF signal
RF signal [2]
Figure 7.
Simulated transient analysis of the proposed up-conversion mixer.
[3]
IV. CONCLUSION This paper has presented the design and simulation of a CMOS up-conversion mixer with an input active baluns. All core mixer and input active baluns are integrated on chip. In the proposed mixer, high linearity is enhanced by using additional parallel capacitors with source inductors degeneration. The IF input balun is employed using a simple FET active balun, while the LO input balun is realized using CSCG active balun. The simulation results show that the proposed mixer achieved IIP3 of 8.0 dBm with CG of 6 dB and core mixer consumes only 2.48-mW power at 1.8-V supply. Therefore, the proposed mixer is suitable for the applications of high linearity and low power CMOS transmitters for wireless applications.
TABLE I.
[4]
[5]
[6]
[7]
[8]
PERFORMANCE OF THE PROPOSED UP-CONVERSION MIXER WITH PREVIOUSLY PUBLISHED WORKS
Reference
[15]
[16]
This work
Technology (µm)
0.18
0.18
0.18
Vdd (V)
1.8
1.0
1.8
IF Freq. (MHz)
10
N/A
100
LO Freq. (GHz)
5.25
3-5
5.1
RF Freq. (GHz)
5.26
3-5
5.2
IF power (dBm)
-20
N/A
-30
LO power (dBm)
3
0
-5
CG (dB)
6.3
6.5
6
IIP3 (dBm)
-8.9
11.6-13.8
8
OIP3 (dBm)
-1.9
-5
10
Noise Figure (dB)
N/A
12~13
26
Core mixer Pdis. (mW)
3.45
11
2.48
IF Balun Pdis. (mW)
N/A
N/A
5.86
[9]
[10]
[11]
[12]
[13]
[14]
[15]
[16] .
4
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