A Development of Single Cycle Control Low Voltage Grid Connected ...

A Development of Single Cycle Control Low Voltage Grid Connected Inverter Pramod Ghimire

A thesis submitted in partial fulfilment of the requirements for the degree of Master of Engineering in Electrical and Computer Engineering at the University of Canterbury, Christchurch, New Zealand. June 2009

ABSTRACT

The thesis describes a development of simple and low engineering cost Single Cycle Controlled grid connected inverter. The voltage source current controlled inverter aims to support low voltage grid from small scale distributed power sources. Single Cycle Controller uses real time current to control PWM switching of the inverter. The controller forces output current to have the same phase as an ordered AC signal. The inverter supports the grid at unity power factor if the AC signal is taken directly from the grid. Use of a generated AC signal is proposed, which allows control over active and reactive current injection or absorption by the inverter. A new synchronized waveform generation method implementable in a microcontroller is proposed in the thesis. A number of Single Cycle Control switching strategies for the H-bridge converter are tested. A hybrid pulse width modulation switching strategy is used as it switches only one switch at high frequency at any time, which reduces switching losses in the bridge and allows easier implementation in hardware. The controller limitation near voltage zero crossing in boost mode is illustrated. Single Cycle Control results in current distortion near voltage zero crossings. Strategies to manage this are presented. The inverter is simulated in P SCAD and hardware prototype is built. The prototype results are presented for current injection into the grid at unity power factor.

ACKNOWLEDGEMENT

I would like to express my sincere gratitude to my supervisor Dr. Alan Wood. Thank you for encouragement, guidance and support throughout the time, since I have been enrolled at the University. I would like to thank my co-supervisor Dr. Paul Gayner. I would like to show my gratitude to Assoc Prof Dr. Nevile Watson, Prof Abdul Rahman, Dr. Chris Arnold and Dr. Piet Beukman for their encouragement during course work period. It is my pleasure to thank all the technical members for being there all time when I needed. Thanks to Late Ron Battersby for taking care at power electronics laboratory, Ken Smart for all those equipments, Michael Cusdin for helping in Altium design, Dudley Berry for bringing components, Nick Smith and Scott Lloyd in PCB preparation, David Healy for all mechanical work, Randy Hampton and Philipp Hof for helping with the oscilloscope, drilling, microcontroller etc. I am very grateful to New Zealand’s International Aid and Agency (NZAID) for offering me a scholarship and providing me supports during my stay in New Zealand, without the scholarship it would not be possible for me to study at Canterbury University. I owe my deepest gratitude to NZAID financial adviser Adrian Carpinter, NZAID advisor Stephen Harte and the people from International student support Mary Furnari, Jonie, Sarah, and Lawrence for making my life easy. I really appreciate the support and encouragement from Nepalese community (Nepal New Zealand Friendship Society), Christchurch for making my staying very special and unforgettable. I am indebted to EPECenter and thanks to Joseph Lawrence and Dr Pat Bodger for giving me a space at the program organized by the center. I appreciate the help and encouragement from all my colleagues Lance, Jordan, Zeff, Vijaya, Bhaba, Robert, Bob, Ida, Andrew, Nick, David, Simon etc. Thank you to all power system group. I would like to thank Dr Peter Freere and his family and KAPEG, Nepal members. Finally, I would like to thank my parents and sisters for everything and believing in me.

CONTENTS

GLOSSARY

xvii

CHAPTER 1

INTRODUCTION 1.1 General Introduction 1.2 Research Objectives 1.3 Thesis Outline

1 1 2 2

CHAPTER 2

BACKGROUND 2.1 Introduction 2.2 Distributed Power Sources 2.3 A Review of GCI Topology and Controller Strategy 2.3.1 GCI Topology 2.3.2 Current Controller Strategy 2.3.3 Converter Topology 2.4 DPS Integration in Electricity Distribution System 2.4.1 Low Voltage Grid 2.4.2 Grid Interconnection Issues and Options 2.5 Interaction Between Inverter and Low Voltage Grid 2.5.1 Steady State Conditions 2.5.2 Transient Stability 2.5.3 Voltage Stability 2.5.4 Voltage Waveform Distortion 2.6 Power Flow 2.7 Conclusion

5 5 5 6 6 9 10 11 11 12 12 12 13 13 13 14 14

CHAPTER 3

SINGLE CYCLE CONTROL 3.1 Introduction 3.2 Basics of Single Cycle Control Theory 3.2.1 Current Magnitude Control 3.2.2 Current Shape Control 3.2.3 Current Phase Control 3.3 Controller 3.3.1 Input Parameter Relation for Current Control 3.4 Control Process in Circuit 3.5 Conclusion

17 17 18 19 20 21 21 23 23 25

viii

CONTENTS

CHAPTER 4

SWITCHING LOGIC FOR SINGLE CYCLE CONTROL 4.1 Introduction 4.2 Converter Topology 4.3 Converter Switching Strategy 4.3.1 Unipolar Pulse Width Modulation 4.3.2 Bipolar Pulse Width Modulation 4.3.3 Hybrid Pulse Width Modulation 4.4 Switching Logic Circuit Development 4.4.1 HPWM Switching Strategy 4.4.2 Bipolar Switching Strategy 4.5 Selection Criteria of Switching Strategy 4.6 Converter Four Quadrant Operations 4.6.1 Buck Mode 4.6.2 Boost Mode 4.6.3 Constraints During Boost Operation 4.7 Conclusion

27 27 27 28 28 28 28 29 31 31 32 33 34 34 34 35

CHAPTER 5

SINGLE CYCLE CONTROL CURRENT WAVEFORM 5.1 Introduction 5.2 Current Control 5.3 Zero-Crossing Current 5.3.1 HPWM Switching Strategy 5.3.2 Bipolar Switching Strategy 5.4 Current Harmonics 5.5 Logic Circuit to Improve Current Waveshape 5.6 Conclusion

37 37 38 38 39 40 41 42 43

CHAPTER 6

FOUR QUADRANT POWER CONTROL 6.1 Introduction 6.2 Power Control 6.2.1 Controller Strategies 6.2.2 Active Power Control 6.2.3 Reactive Power Control 6.3 Voltage Control 6.4 Implementation of New Generated Waveform 6.4.1 Phase Synchronization 6.4.2 Lookup Table Development for Angle Measurement 6.5 Conclusion

45 45 45 45 46 47 47 49 49 52 53

CHAPTER 7

SIMULATION, DESIGN AND PROTOTYPE DEVELOPMENT 7.1 Introduction 7.2 Simulation 7.3 Controller Circuit 7.3.1 Oscillator 7.3.2 Resettable Integrator 7.4 Voltage and Current Detection

55 55 55 56 56 57 58

ix

CONTENTS

CHAPTER 8

7.4.1 Zero-Crossing Sensing 7.5 Logic Circuitry 7.6 IGBT Gate Drive Circuitry 7.7 Power Circuit 7.7.1 Parasitic Bus Inductance 7.7.2 Stray Inductance Between High Side and Low Side Switch 7.8 Filter 7.8.1 Size of Inductor 7.8.2 Selection of Core 7.9 Thermal Design 7.9.1 Inverter Board and Heat Sink Estimation 7.10 Hardware Construction 7.10.1 GCI Test Rig 7.10.2 Prototype Results and Discussion 7.11 Conclusion

59 59 59 61 62 63 64 64 65 66 66 67 68 68 71

CONCLUSION 8.1 Conclusion 8.2 Future Work

73 73 73

APPENDIX A MICROCONTROLLER

75

APPENDIX B INDUCTOR DESIGN

81

APPENDIX C THERMAL SYSTEM C.1 Inverter Board C.1.1 Power loss in IGBT C.1.2 Power loss in Diode

83 83 83 84

APPENDIX D PSCAD SIMULATION D.1 Single Cycle Controller D.2 Logic Circuit D.3 Inverter Circuit

87 87 88 89

APPENDIX E HARDWARE DEVELOPMENT E.1 Circuit Diagrams

91 91

APPENDIX F PUBLISHED PAPER

105

REFERENCES

107

LIST OF TABLES

3.1 3.2

SR latch truth table SCC logic sequence

24 25

4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9

UPWM switching options BPWM switching options HPWM switching options Logic development rules Terminology used in development of Boolean equations Boolean equations in first switching method Boolean equations in second switching method Boolean equations in third switching Method Boolean equations in fourth switching method

28 29 29 30 31 31 32 32 33

5.1

New truth table after addition of new logic

42

6.1 6.2 6.3

Logic to find the operating sin θ − cos θ plane Logic to find the operating sin θ − cos θ plane Phase angle decoupling

52 52 53

7.1 7.2 7.3 7.4

Simulation parameters Inductor designed paramter Bridge operating parameter Power loss in power switches

55 66 66 67

LIST OF FIGURES

2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11

Four switch and six switch buck-boost inverter Converter with a DC link Converter with a Pseudo DC link Converter without a DC link Hysteresis current controller Hysteresis current control Ramp comparison current controller with hysteresis Predictive current controller Grid series impedance Inverter grid connection Inverter connection to grid

7 7 8 8 9 9 10 10 12 13 14

3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10

Controller block diagram SCC signal flow block Single Cycle Control signals Current at variable x(t) and fixed v(t) Current at fixed x(t) and variable v(t) v(t) as leading phase angle Single Cycle Controller Controller operation waveform Current and voltage signals at the input of comparator Logic sequence and operation of SCC

17 18 19 20 20 21 21 22 23 24

4.1 4.2 4.3 4.4 4.5 4.6 4.7

Full bridge inverter Current lagging waveform Current leading waveform 4Q operation 1.HPWM 2.BPWM Equivalent buck circuit for 1. First quadrant 2. Third quadrant Equivalent boost circuit for 1. Second quadrant 2. Fourth quadrant Current distortion during boost mode

27 30 30 33 34 34 35

5.1 5.2 5.3 5.4

Current control in one switching cycle Power circuit vL (t), Vg , vo (t) for HPWM first switching method Current ripple for HPWM first switching method

37 38 38 39

xiv

LIST OF FIGURES

5.5

Grid voltage and output current near zero crossing for 2Q first switching method (HPWM) 5.6 Grid voltage and output current near zero crossing for 2Q second switching method (HPWM) 5.7 Grid voltage and output current near zero crossing for third switching method (BPWM) 5.8 Grid voltage and output current near zero crossing for fourth switching method (BPWM) 5.9 Output current harmonics 5.10 Additional logic on SR latch 5.11 SCC controller signals waveform near zero crossing 6.1 6.2 6.3 6.4

39 40 40 41 41 42 42

6.5 6.6 6.7 6.8 6.9 6.10 6.11 6.12 6.13 6.14

New waveform generation Power control strategy Active and reactive power injection into the grid using SCC Active power injection into the grid and reactive power absorption from the grid using SCC Inverter connected to grid Phaser diagram for 1. reactive power only 2. active power only Real and reactive power compensation Phase locked loop diagram Phase angle detection block diagram Continuous integrator sin θ and cos θ 1. tan θ 2. Phase angle 4Q sin θ − cos θ plane ADC register

46 47 47

7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.12 7.13 7.14 7.15 7.16 7.17

The SCC control signals 56 Grid voltage and output current 56 Timer 555 57 Resettable integrator 57 Analogue switch 58 Current and voltage monitoring circuit 59 Zero crossing detection 59 IGBT switching logic sequence for Q1 , Q2 , Q3 and Q4 at reactive current injection 60 IGBT driver IR2112 logic voltage level 60 IGBT driver circuit diagram 61 Snubber across IGBT 62 DC bus connection at PCB 63 Stray inductance 64 Inductor core 65 Equivalent circuit 1.at 50Hz 2.at 5kHz 65 Controller board and test set up 67 Inverter test rig layout 68

48 48 48 49 49 50 50 51 51 52 53

LIST OF FIGURES

7.18 7.19 7.20 7.21 7.22 7.23

Integrator reset pulse and output SCC controller operation IGBT switching gate pulse for Q1 Inverter output voltage Scaled AC voltage and current waveforms Current harmonic spectrum

xv

68 69 69 70 70 71

B.1 Duty cycle at fundamental current peak

81

D.1 Single cycle controller D.2 Switching logic circuit D.3 Inverter circuit

87 88 89

E.1 E.2 E.3 E.4 E.5 E.6 E.7 E.8 E.9 E.10 E.11 E.12

Circuit Oscillator Voltage detector Voltage and current sensing circuit Single cycle controller unit Logic IGBT driver circuit SCC controller PCB SCC controller PCB upside SCC controller PCB downside SCC controller PCB component layout Laboratory test set up

92 93 94 95 96 97 98 99 100 101 102 103

GLOSSARY

Abbreviations AC A/D APF BPWM CBS COM CMOS DC DG DPS DSP EMI EMTDC ESR FACTS FPGA FFT Fund GCI HPWM IGBT MIC PCC PFC PLL PI PSCAD pu PV PCB PWM RMS SCC SPWM SS STATCOM SW THD

Alternating Current Analogue to Digital Converter Active Power Filter Bipolar Pulse Width Modulation Bootstrap Capacitor Ground Complementary Metal-Oxide-Semiconductor Direct Current Distributed Generation Distributed Power Sources Digital Signal Processing Electromagnetic Interference Electro Magnetic Transient Direct Current Equivalent Series Resistance Flexible AC Transmission Systems Field Programmable Gate Array Fast Fourier Transform Fundamental Grid Connected Inverter Hybrid Pulse Width Modulation Insulated Gate Bi-polar Transistor Module Integrated Converter Point of Common Coupling Power Factor Controller Phase Locked Loop Proportional-Integral controller Power System Computer Aided Design - interface for EMTDC Per-unit Photo Voltaic Printed Circuit Board Pulse Width Modulation Root Mean Square Single cycle controller Sinusoidal Pulse Width Modulation Steady State Condition Static Compensator Switching Total Harmonic Distortion

xviii

GLOSSARY

TS UPWM VS VSC VWS 4Q 2Q

Transient Stability Unipolar Pulse Width Modulation Voltage Stability Voltage Source Converter Voltage Waveform Stability Four Quadrant Two Quadrant

Symbols C D1 , D2 , D3 , D4 io (t) i(t) P Q v(t) vnew (t) vo (t) X Q 1 , Q2 , Q3 , Q4

DC side Capacitor Diode Switches Inverter output current Small scaled current in Single cycle controller Real power Reactive power Scaled AC voltage for current control New generated current ordered AC signal AC supply voltage DC control signal IGBT Switches

Chapter 1 INTRODUCTION

1.1 GENERAL INTRODUCTION Proper use of freely available renewable energy sources is a global need today. There are two major global challenges ahead; one is to reduce the carbon emission to mitigate the reduction in global warming and another is to allow easy access to the basic need for power to all human beings. The proper use of effective power electronics technology will increase the use of widely distributed power sources which addresses both above mentioned challenges [1] . Advanced power electronics also play a vital role to interconnect different types of power sources efficiently, increase power transfers and reduce losses, allow flexible transmission of energy, variable speed operation of electric generators etc [2] . The thesis goal is the development of a simple and low engineering cost Grid Connected inverter (GCI) which will boost the use of renewable energy systems in remote and urban locations. The purpose of this thesis is to develop a cheap and simple inverter system to interconnect small scale power generator to the low voltage grid. GCI systems often require a Digital Signal Processor (DSP) and complex engineering [3]. Depending upon the nature of sources, the interconnection systems require AC to DC and DC to AC converters. Herein after the AC to DC converter is called generator side converter and DC to AC converter is called AC side converter. The generator side converters are relatively cheap and available in different standards. They directly connect generator output to the AC side converter through a DC link capacitor. The work is focused on the development of the AC side converter. The purpose of AC side converter is not only to invert DC into AC voltage, but also to interconnect output power to a utility grid. The GCI systems should be featured with interconnection standards acceptable by the utility systems [4]. Generally renewable power sources are connected to a distribution level grid. Penetration of both active and reactive power is significantly useful for stability of the grid. Reactive power control might not be very effective to control voltage at the low voltage grid in comparison to a high voltage systems [5]. Nevertheless, reactive power injection is important to support the inductive load and reactive part of grid itself. Use of reactive power control helps to stabilize the grid voltage to some extent. Optimum active power injection is effective to maintain the voltage level in such smaller systems. Generally low voltage systems have a high impedance. The proposed inverter system is intended to support the grid at unity power factor during normal grid voltage. Upon decreasing or increasing the grid voltage level, the inverter system either generates or absorbs reactive power. The consequence of reactive power compensation from individual system may be negligible. However, large numbers of such small systems at suitable locations can provide substantial support for the system stability. This thesis doesn’t outline the rating and number required to compensate the reactive power at different voltage level. It does, however,

2

CHAPTER 1

INTRODUCTION

discuss how much the proposed system can compensate reactive power at different voltage levels. The thesis proposes a GCI system to connect at distribution voltage level from small scale power generators for a range of 1KW in single phase systems. Single Cycle Control (SCC) [6] is proposed to control the inverter current either in phase with, leading or lagging the grid voltage. The minimum requirements of source voltage and operating characteristics are outlined. Single Cycle Controller is explained and power control methodologies are presented. The logic implementation for inverter switching strategies are presented and current zero-crossing problems are addressed for each strategy. A simulation is performed on P SCAD/EM T DC program. A laboratory hardware prototype is built. Both simulation and hardware results are presented in the thesis.

1.2 RESEARCH OBJECTIVES The objective of this research is to develop a cheap and simple grid connected inverter system which allows the connection of dispersed small scale renewable sources or DC energy storage to the grid. Available inverters are relatively expensive and uses complex circuitry for the purpose. The thesis investigates different single cycle logic switching methods for the H-bridge converter to find efficient and less current distorting methods for easier implementation in hardware. The performance for different switching methods are investigated through simulation. The inverter is proposed to support the grid at unity power factor, during healthy network conditions. However, if the system voltage level changes, it will inject the reactive current to compensate the reactive loss in the filter impedance and the grid itself. The converter will be equipped with power control and allows bidirectional flow of both active and reactive current.

1.3 THESIS OUTLINE Chapter 2 provides background on renewable energy integration into low voltage grids. Grid connected inverter topologies are reviewed and interactions of the inverter with low voltage grid are discussed. Chapter 3 describes Single Cycle Control theory. Chapter 4 presents switching logic for Single Cycle Control. Three different switching strategies are presented and ranges of switching methods are given for switching of full bridge inverter. Chapter 5 illustrates current performance in Single Cycle Control. Zero crossing performance of the current is shown for the ranges of switching methods. Chapter 6 presents power controller using Single Cycle Control. A waveform generation method is proposed. A phase synchronization method implementable in microcontroller is proposed in the chapter. Chapter 7 provides P SCAD simulation results. Circuit design is presented. A laboratory prototype development is given and experimental results are presented.

1.3

THESIS OUTLINE

3

Chapter 8 concludes thesis. Future work is recommended for proposed grid connected inverter.

Chapter 2 BACKGROUND

2.1 INTRODUCTION A number of grid connected inverter topologies and switching strategies have been developed depending upon the nature of distributed power sources. The aim of the inverter is to transfer maximum available energy to the power network despite having strong interactions during connection. An economic and reliable interconnected system is a challenging issue for a weak grid network. This chapter presents a brief summary of recent work in the field of interconnection of small distributed power sources through a inverter into the low voltage network. It contains a brief introduction to distributed energy sources, a review on inverter topology and controller strategies, integration of inverter and source into a distribution network and probable interactions between inverter and grid for single phase systems.

2.2 DISTRIBUTED POWER SOURCES Distributed Power Sources (DPS) are defined as ”demand and supply side resources that can be deployed throughout an electric distribution system (as distinguished from the transmission system) to meet the energy and reliability needs of the customers served by the system. Distributed resources can be installed on either the customer side or the utility side of the meter” [7]. Various kinds of renewable and non renewable distributed power sources exist [8]. Due to the increasing global crisis in non-renewable energy resources, renewable and green sources have been attracting more attention recently. Established distributed energy sources are; microhydro, wind, solar power fuel cell, combined heat and power, bio-gas, bio-mass, geothermal and diesel power. In order to improve the reliability of the generation and injection of power into the grid during overload, several energy storage systems have been investigated and are implemented primarily in renewable energy integrated systems. The well developed energy storage systems are; flywheels, hydrogen storage, battery storage, super-capacitors, compressed air energy storage, super-conducting magnetic energy storage and pump hydro-electric storage. This thesis is concerned with grid connection of a renewable or storage energy sources but does not outline its characteristics and nature. Generally the renewable energy sources have a stochastic nature and require advanced power electronics control to maintain the power output as required by the utility standards [4] [9]. In order to be incorporated into the grid certain technical guidelines need to be met before interconnection so that the distributed power sources do not strongly affect the normal operation of network. The proposed system can be implemented

6

CHAPTER 2

BACKGROUND

for any type of energy source which satisfies the general input requirements of the proposed inverter.

2.3 A REVIEW OF GCI TOPOLOGY AND CONTROLLER STRATEGY The proposed GCI system primarily controls three major parameters; current magnitude, phase and frequency. Several types of inverter topology and controller strategy have been used for three phase and single phase systems in the past. Synchronization of the systems with the the utility supply is a challenging issue. It is often achieved by using DSP or field programmable gate array (FPGA). It adds complexity to the circuit and increases the engineering cost. However, the complex digital control ensures a delivery of a good power quality into the grid and intelligent quick controller systems. Various single stage and multi stage GCIs are used. The single stage inverters offer simple structure and low cost but suffer from limited input voltage range, while the multi stage inverters are complex, expensive and less efficient [10]. The proposed system uses a single stage inverter with a full bridge topology and a Single Cycle Controller (SCC) strategy for single phase system. Several research publications report various topologies and controller strategies for GCI systems. Popular controller strategies implement DQ conversions and real time reference current regulation. They require a high speed DSP and high performance A/D converters. A multi functional power electronic converter for DPS has been reported [11]. The converter system is assigned to deliver power and acts as an active power compensator in a hybrid compensation system for the local network to improve the overall power quality and improve the stability of the power system. The integration of a STATCOM and battery energy storage has been reported, however, the energy storage device is small and only able to provide for a short period of time [12]. This system increases flexibility over traditional STATCOM with improved damping capabilities due to the additional degree of control freedom provided by the active power capabilities.

2.3.1 GCI Topology In the case of Photo-Voltaic (PV) connected grid systems, inverters are classified into three different families. 1. Central inverter system: This is a single large converter for multiple panels. 2. String inverter system: Multiple inverter connected in series for multiple panels. 3. Module integrated converter system: Each dedicated converter is used for each panel. Central and string inverter systems are popular at high and medium voltage level with medium power capacities up to the ranges of a Megawatt. Module integrated converter (MIC) systems are used at low power level and offer a plug and play facility for grid connection. The MIC concept provides the potential to connect many dispersed energy sources, but this challenges system reliability, stability and increases cost. GCI system topologies can be classified in terms of conversion stages, design specifications and converter topology. A single stage-inverter is defined as an inverter with only one stage of power conversion for both stepping up the low DC voltage and modulating the sinusoidal load current or voltage [10]. Single stage power inverters are classified based on either 4 switch or 6 switch

2.3

7

A REVIEW OF GCI TOPOLOGY AND CONTROLLER STRATEGY

Q1

Q3

Q1 Q5 Q2

DC Q3

Q2

Q4

Q4

Figure 2.1

Q6

Four switch and six switch buck-boost inverter

topology as shown in Figure 2.1. Four switch topology is implemented using the DC inputs of two identical boost DC to DC converters in parallel with the DC source. Each converter is modulated to produce out of phase sinusoidal output with each other [13]. Six switch topology is implementing using two buck-boost DC to DC converters in a four switch bridge with two additional switches used for synchronous commutation in each half cycle of AC output [14]. A multistage inverter is defined as an inverter with more than one stage of power conversion, in which mostly one or more stages accomplish voltage step up or step down or electrical isolation and the last stage performs DC to AC conversion [10]. The MIC topologies have been classified into three different arrangements according to the DC link configuration converter with a DC link, converter with a pseudo DC link and converter without a DC link [15].

Converter With a DC Link The converter system with a DC link has DC to DC and DC to AC power conversion stages as shown in Figure 2.2. The DC side converter is used to control the maximum power from source and AC side converter is used to produce AC power with unity power factor. This topology has two major disadvantages. The AC side converter requires a PWM control in order to reduce

AC

DC Source

DC side Converter

Figure 2.2

DC Link

AC side Converter

Converter with a DC link

the harmonic distortion. Both stages of power conversion require high frequency switching of power electronics, which increases the switching losses. However, losses can be minimized with a suitable switching topology and for implementing soft switching techniques.

8

CHAPTER 2

BACKGROUND

Converter With a Pseudo DC Link The converter system with a pseudo DC link has a modulated DC to DC converter which produces a rectified sinusoidal voltage on the DC link as shown in Figure 2.3. A grid side DC to AC converter with the square wave control converts the link voltage to the AC in unity power factor. The major advantage is that the AC side converter operates at the line frequency and a simple low frequency switching can be implemented which reduces high switching losses. Many single stage or transformerless GCIs have implemented such topology but they can’t avoid the following drawbacks [16]: 1. The transformerless inverters have limited AC peak voltage that is less than the DC voltage. 2. The DC voltage range in single stage inverters is more limited than the multiple stage inverters. 3. The dual grounding becomes difficult issue in the transformer less inverters.

AC

DC Source

DC side Converter

Figure 2.3

Mains Frequency Unfolder

Converter with a Pseudo DC link

Converter Without a DC Link The converter system without a DC link has two conversion stages with the DC voltage transformed to a higher frequency AC voltage and amplified to a higher level compatible with the AC grid voltage as shown in Figure 2.4. It completely avoids the DC link between conversion stages. This topology requires more sophisticated and higher bandwidth controls as no intermediate energy storage is present and power conversion can no longer be identified as independent DC to DC and DC to AC conversion stages. This has the advantage of having total power conversion in two stages only.

AC

DC Source

DC side Converter Figure 2.4

Frequency Converter

Converter without a DC link

2.3

9

A REVIEW OF GCI TOPOLOGY AND CONTROLLER STRATEGY

2.3.2 Current Controller Strategy In direct grid connected GCI systems, there are generally three types of current controller proposed in the past; hysteresis current controller, ramp comparison and predictive current controller. As the system is directly connected to the grid, the voltage is same as the grid voltage. Hysteresis current control compares load current to the reference current using hysteresis method as shown in Figure 2.5. This method is simple and robust but the switching frequency depends on the load as shown in Figure 2.6.

iordered

Q+ Switching circuit

+-

Q-

imeasured Figure 2.5

Hysteresis current controller

The improved hysteresis controller has been proposed using hysteresis band control method which maintains nearly constant switching frequency, but doesn’t improve the current ripples [17].

i

t v Ton

t Toff

Figure 2.6

Hysteresis current control

The ramp comparison controller measures current error and compares to a triangle waveform to generate switching pulses as shown in Figure 2.7. The PI controller has steady state error and accurate tuning is hard [18]. The predictive current controller calculates the inverter voltages necessary to force the output current close to the reference current as shown in Figure 2.8 [19]. But it needs more calculations, a good knowledge of the system parameters as well as a fast DSP.

10

CHAPTER 2

Q+

-

iordered

+

BACKGROUND

Switching circuit

-

Q-

imeasured Figure 2.7

Ramp comparison current controller with hysteresis

ierror Q+ iordered

K1

+

-

Hold

Vector to phase transformation

Switching circuit

Q-

K2 imeasured Figure 2.8

Predictive current controller

2.3.3 Converter Topology Suitable converter topologies include, 1. Half bridge inverter 2. Full bridge inverter 3. Push pull inverter 4. Buck boost converter 5. Flyback converter 6. Cuk converter 7. Zeta converter 8. D2 converter Half bridge inverters require two equal capacitors in series connection across the DC input with a equal voltage drop across each capacitor. The peak voltage and current ratings of the switches are same as DC voltage and output AC peak current. This topology is not suitable for high current applications. Full bridge inverters consist of two legs with twice number of switches than the half bridge inverter. It gives an output voltage twice than of the half bridge inverter for same DC voltage input. Thus it is preferred for high power ratings. Push pull converters require a transformer with center tapped primary. The main advantage is that only one switch conducts at any instant of time, which is an advantage for low voltage sources like PV, battery. The transformer requires very good magnetic coupling between two half windings in order to reduce the leakage inductance with the two primary windings. For sinusoidal output, the transformer must be designed for fundamental frequency output [20].

2.4

DPS INTEGRATION IN ELECTRICITY DISTRIBUTION SYSTEM

11

The buck-boost topology helps to accommodate wide range of input DC voltages for a single stage inverter topology. The flyback topology allows electrical isolation. This topology has the advantages of being simple and with a small number of switching operations. The flyback has been used in buck-boost type inverter in several research papers. All CUK, Zeta and D2converters are fourth order converters and are developed based on the buck-boost converter topology. The CUK converters require a large reservoir capacitor for high power applications to support the full load current. Several topologies have been tried to reduce the size and cost of the capacitor in the CUK topology [21]. Zeta converter is made up of two inductors and two capacitors and is capable of providing continuous current [22]. D2-converter is similar to the CUK converter. Like the CUK and Zeta converters, the D2-converter is capable of producing continuous output current, which eases the filter design.

2.4 DPS INTEGRATION IN ELECTRICITY DISTRIBUTION SYSTEM The GCI is a part of DPS and used for interfacing to the network. The maximum rating of the DPS depends on the voltage level of the distribution networks [23] and short circuit capacity under maximum fault current condition at the connection points [24].

2.4.1 Low Voltage Grid The term ”Low voltage grid” generally represents a utility system at distribution level. The nature of low voltage networks may vary according to the locations, for example rural, urban and near urban networks. The voltage level in the weaker grid tends to fluctuate more with changes in load, because loads are connected close to such networks. In comparison with urban area networks, rural area networks are more vulnerable to the changes in load. Hence, the low voltage networks mainly in rural area described as a weak system. The high voltage and extra high voltage networks are considered strong as they pose a smaller impedance and consequently are less susceptible to the changes in load. Generally the system weakness characteristics can be categorized into three different natures. 1. High impedance grid 2. Power impotent grid 3. High harmonics grid All three characteristics are interrelated. The low voltage grid has high series impedance due to low voltage level, thinner cable and long transmission as shown in Figure 2.9. In general, it contains equivalent resistive and reactive components. Upon increasing inductive load, significant voltage drop occurs in both components of the line. Hence, they require both active and reactive power injection to compensate for the extra voltage drop. The term ”Power impotent grid” represents a system which is operating at peak load capacity. Any increment in load would result to a drop in frequency and voltage level resulting ultimately in a black out. Weak systems are more vulnerable to high harmonic levels. This will increase energy loss and the system operating cost. The line voltage distorts due to harmonic current injection from loads.

12

CHAPTER 2

jXL

R

Vgrid

E Figure 2.9

BACKGROUND

Grid series impedance

2.4.2 Grid Interconnection Issues and Options The integration of small scale GCI at the distribution level may affect network stability and power quality. Primarily there are three different issues related to DPS interconnections; technical, legal and procedural and tariff issues [26]. Technical issues include safety, power quality, system impacts, islanding etc. The increase in GCIs adds new challenges in electricity distribution networks. Renewable energy technologies pose additional technical challenges. High penetration rates of intermittent GCI poses serious technical constraints, which requires some form of back up power or energy storage. System stability and reliability of the power supply will be the major issues, which can be addressed with a suitable injection of reactive and active power to the networks at suitable locations.

2.5 INTERACTION BETWEEN INVERTER AND LOW VOLTAGE GRID The power grid is a dynamic system. The GCI, while transferring energy to the grid acts differently during normal and fault operations of the system. The equivalent circuit of converter connection to grid is shown in Figure 2.10. Due to inevitable faults like short circuits, generator islanding etc, the system takes time to regain normal operation. Small scale inverters cannot provide effective support on a large system during abnormal events, but they need to consider likely interactions with the design to enable the system stability by the mixed active and reactive power control. One possible way to analyse the interactions is in terms of time constant, which can be divided mainly into four different stabilities. 1. Steady State Conditions (SS) 2. Transient Stability (TS) 3. Voltage Stability (VS) 4. Voltage Waveform Distortion (VWD)

2.5.1 Steady State Conditions Steady state conditions are a mix real and reactive power flow controls, steady state voltage and power balance in the system. Droop control helps active and reactive power flow. The proposed inverter features with a mix real and reactive power flow.

2.5

13

INTERACTION BETWEEN INVERTER AND LOW VOLTAGE GRID

R

jXL

o

Vinv ∟δ

VAC ∟0

Inverter

Grid

Figure 2.10

o

Inverter grid connection

2.5.2 Transient Stability Transient stability can be defined as the ability of a power system to recover synchronism after large and sudden disturbances such as a fault, generator and energy storage devices islanding etc. In terms of time constant frame this occurs within a few seconds. The main purpose of TS analysis is to ensure a return to fundamental frequency during sudden disturbances as quickly as possible. Upon increasing the number of generators and energy stores into the system, the complexity of TS increases. In large power systems, synchronous generator inertial constants protect from large variation of frequency on sudden load change or disturbances. The GCIs transferring energy from DC link are inertia-less. However, The power flow controller to regulate the DC bus voltage will have some degree of filtering and this gives the appearance of of inertia similar to that seen in a synchronous machine. The GCI can be equipped with extra energy storage devices such as battery to support the system during TS. Power frequency droop control helps to regain the TS. The proposed inverter supports active power during underfrequency. The power injection will be lower from the inverter during overfrequency.

2.5.3 Voltage Stability Voltage stability is defined as the ability of a power system to maintain steady acceptable voltages at all busses in the system under normal operating conditions and after being subjected to a disturbance. The VS mainly occurs in highly inductive network and influences by generator reactive power and voltage control limitations, load characteristics, system impedance etc. In terms of time constant it occurs for more than half cycle of the fundamental waveform. If the voltage drop is within limit, a Voltage droop control helps to stabilize the voltage level. The inverter generates reactive power when AC fundamental voltage is below acceptable level and absorbs reactive power when high.

2.5.4 Voltage Waveform Distortion Voltage waveform distortion can be defined as any deviation from the nominal sine waveform of the AC line voltage. Harmonic current injection from loadside is a main source of the VWD. A filter or voltage reinjection circuit can be used to regain a shape of the fundamental waveform. Higher order harmonics due to high frequency switching operation of the inverter may resonate with the system impedance resulting in voltage distortion. A well designed filter can attenuate high frequency components but has an impact on the control bandwidth and the impedance. Various schemes and filter designs have been introduced but a high order filter increases the complexity and cost of the overall system [27] [28] [29] .

14

CHAPTER 2

BACKGROUND

The proposed GCI uses a generated reference waveform to inject current into the system, thus, even if the system voltage distorted, it injects less harmonic current. This reduces the effect of harmonics. The filter impedance is prone to resonate with the dynamic grid capacitance. Hence before designing a filter, it is important to understand dynamic parameters of the network [29]. Large grid impedance variation in weak systems challenges the control and the grid filter design in terms of stability. The impedance variation leads to both dynamic and stability problems in the low frequency range as well as high frequency range. In the low frequency range, the possible variation of the impedance challenges the design of resonance controllers adopted to mitigate the effect of the grid harmonic voltage distortion on the grid current. In the high frequency range the grid impedance influences the frequency characteristics of the filter and the design of passive or active damping becomes more difficult [30] [31].

2.6 POWER FLOW The inverter power capability mainly depends on the DC side voltage, filter impedance and the grid voltage. The DC side voltage is generally kept constant through a P I controller, consequently all the real power coming into the DC link is instantaneously transferred into the grid. When the generator power increases, the capacitor voltage increases. The GCI should force more power to the grid to keep the capacitor voltage level fixed. If the generator power is not enough to charge up the capacitor, the grid supports power to the input side. The proposed system is designed to control bi-directional power flow. The proposed inverter connection to grid is shown in Figure 2.11. For unity power factor operation the inverter works in Buck mode. Filter Q1

D1

Q3

R

D3

jXL

DC Source

RG Vg

+ Vinv

C

jXLG

AC Grid

VAC 50Hz

Q2

D2

Figure 2.11

Q4

D4

Inverter connection to grid

This requires the DC side voltage to be greater than the peak of the grid voltage. During non unity power factor operation, the inverter operates in both buck and boost mode. During boost mode, the AC voltage supplies current to the DC side. This is possible due to four quadrant operation of the inverter.

2.7 CONCLUSION The integration of distributed power sources into a weak distribution network is challenging in order to maintain stability and power quality. The chapter gives a brief overview of the development in the converter and its classifications, distributed power sources and problems related to the energy integration into power grid. A number of inverter topologies are presented

2.7

CONCLUSION

15

and classified according to applications, power conversion stages, power level etc. Low power converters with plug and play facility at residential mains voltage level are increasing rapidly. Power qualities issues such as poor voltage regulation, harmonic distortions and voltage dip are common in the low voltage networks. More research is required on the low power scale converter to augment the performance of weak networks with the maximum utilization of distributed power sources.

Chapter 3 SINGLE CYCLE CONTROL

3.1 INTRODUCTION Single Cycle Control (SCC) is a dynamic switching technique employed in a power electronics converter for voltage or current control using Pulse Width Modulation (PWM) [6]. This is a general method based on integration of a voltage or current in order to force its average value to some control reference signal. It has been identified as a simple technique for current control and has already been proposed as a potential technique for control of converters in grid interconnection applications [32]. The control theory has already been tested for controlling three phase PFCs, APFs, STATCOMs [33]. It avoids the use of complex circuitry and digital signal processors for control applications which not only reduces complexity but also makes it cheaper and faster. It is easier to implement in hardware and requires few analogue and logic components. With simple engineering, it can be implemented anywhere with locally available components at a fairly cheap price. The controller is used to control the inverter output current Reset integrator DC signal

Resettable integrator

Adder

Current control signal

Figure 3.1

Comparator

Latch logic

Power switch control

Current

Controller block diagram

at constant switching frequency and the method forces the output current waveform to match the reference voltage. This makes it easy to synchronize with the grid at unity power factor. The Single Cycle Controller method is also implemented for reactive current control in the proposed inverter. A block diagram for the Single Cycle Controller is shown in Figure 3.2 This chapter explains the Single Cycle Controller and presents output current magnitude, shape and phase control methods. The basics of Single Cycle Control theory is explained in section 3.1. The implementation of the controller for constant switching frequency and the controller operation are introduced in sections 3.3 and 3.4.

18

CHAPTER 3

SINGLE CYCLE CONTROL

3.2 BASICS OF SINGLE CYCLE CONTROL THEORY The aim of Single Cycle Control is to adjust the duty ratio of the power switches in real time such that the average value of the current waveform at the switch is exactly equal to the control reference on each switching cycle. This switching method can be implemented for constant on time switching, constant of f time switching, constant frequency switching and variable switching frequency for power converter applications [6]. Constant frequency switching is chosen. The SCC requires two instantaneous reference signals at two stages as shown in Figure 3.2. The first reference signal is taken from grid voltage or equivalent generated signal v(t) which has a similar shape as and is synchronized with the grid voltage. The shape of the reference voltage signal v(t) will define the shape of the output current io (t) injected into the grid. The second reference signal is taken from real time output current which is flowing through the inductor in series with the inverter output. The measured reference current i(t) signal is scaled for a given power level. |i(t)|

i(t) -vm(t) X

y(t)

Logic output to latch

+ +

Reset

|v(t)|

v(t) Figure 3.2

SCC signal flow block

Let the input signal X be steady as shown in Figure 3.3. Assume that the X is integrated and reset at much higher frequency than the grid fundamental frequency. The real time integrator starts working exactly at the time when a power switch is turned on. The real time integrated output is −vm (t). The negative sign represents vm (t) is falling. The −vm (t) is added to the absolute scaled AC voltage signal v(t). Suppose the effective time varying output after addition is y(t). The y(t) is compared with the scaled absolute inverter output current i(t) in real time. At the instant when the added signal meets the current signal, the switch is turned of f . At the same time, the controller resets the integrator and the process will repeat in the next switching cycle. Any perturbations in control signal X or reference signal v(t), will change the output current instantly in each cycle. Let ton , tof f and D(t) be turn on, turn of f time and duty cycle respectively for a total switching period T . Hence, ton = D(t) × T 1 y(t) = v(t) − T

Z

t

x(t)dt

(3.1)

0

The output y(t) is compared with the reference signal i(t) instantaneously. In each switching cycle, the switch turn of f instant is based on signals y(t) and i(t). The switch is of f when y(t) = i(t)

(3.2)

3.2

19

BASICS OF SINGLE CYCLE CONTROL THEORY

X t t -νm(t)

|ν(t)| t

|i(t)| t y(t)

|i(t)| t Switching logic t

Figure 3.3

Single Cycle Control signals

Equation 3.2 shows that the output current is function of the reference voltage signal v(t) and the input control signal X for a constant load. The power switches are controlled so that they turn on at the start of the integration period. The current i(t) rises and the calculated y(t) falls, and the switches turn of f when the signals are equal. In this way, the current magnitude tracks the same shape as the voltage v(t), but to a smaller value dependent on the slope of the integrator X.

3.2.1 Current Magnitude Control The slope of the integrator output depends on the amplitude of signal X. Any perturbations in signal X would change the real time slope of the integrator output −vm (t). A higher value of X increases the slope of the −vm (t), which reduces the peak current in each switching cycle. Suppose reference signal v(t) is fixed for a switching period T , and the input DC signal X1 has slope −X1 as shown in Figure 3.4. When the input signal increases from X1 to X2 , the corresponding slope increases from −X1 to −X2 and the inductive current rises for a shorter time, reducing the average output current. Let Ioav1 and Ioav2 be average output currents for input signals X1 and X2 respectively. Hence, the average output current Ioav reduces in proportion to the integrator input signal X, assuming other parameters constant. Ioav ∝ (1 − X(t))

(3.3)

20

CHAPTER 3


Vo

X1 X2

i(t) Ioav1 Ioav2

T

0 Figure 3.4

t

Current at variable x(t) and fixed v(t)

3.2.2 Current Shape Control The reference voltage signal v(t) provides the starting point for the −vm (t). A high amplitude of v(t) allows more time for the current rise before y(t) = v(t) − vm (t) meets i(t) and the power switch turns off. The output current magnitude is directly proportional to the magnitude of v(t), which adjusts the converter current shape.

vo1 X1 vo2 X2

i(t) Ioav1 Ioav2

0

Figure 3.5

T

t

Current at fixed x(t) and variable v(t)

Suppose X is fixed for a switching period T , the reference voltage signal v(t) is reduces from vo1 (t) to vo2 (t) as shown in Figure 3.5. The integrator slope is the same but the current rise time decreases, reducing the average output current. Let, Ioav1 and Ioav2 be average output current for input vo1 (t) and vo2 (t) respectively. Hence, the average output current Ioav is proportional

3.3

21

CONTROLLER

to the reference voltage v(t) assuming remaining parameters are constant. Ioav ∝ v(t)

(3.4)

3.2.3 Current Phase Control As the current shape is proportional to the v(t), with a suitable phase reference, the output current phase can be adjusted with respect to the grid voltage as shown in Figure 3.6. A new reference waveform is generated synchronized with the grid voltage with a capability of phase and magnitude variation. The phase angle is adjusted according to the need of reactive current injection or absorption by the inverter. The maximum reactive current injection has a limit, as it supports active power at the same time. v(t)

Grid voltage

Grid injected current Phase angle Figure 3.6

v(t) as leading phase angle

3.3 CONTROLLER The SCC controller is mainly comprised of a resettable integrator, adder, comparator and SR latch as shown in Figure 3.7. Switch

Resettable integrator X

R1

C1

Comparator

Adder

SR latch

Driving signal

|v(t)| Figure 3.7

|i(t)|

Oscillator

Single Cycle Controller

Here, vo (t) = inverter output voltage, D(t) = duty ratio. The control signals are v(t) = k × vo (t) and i(t) = Rs × io (t). k represents AC voltage scaling factor and Rs represents a current sensing resistance which

22

CHAPTER 3


is used to scale the output current for control purposes. The converter has a average output voltage over a single switching period, vo (t) = Vg × D(t)

(3.5)

Here Vg is the inverter input DC voltage. During turn on time, the maximum voltage that the

k*vo(t) - vm(t) -vm(t) -vmax

Rs* io(t)

t switching pulses

t

Ton T

Figure 3.8

Controller operation waveform

integrator output voltage can fall, vmax , can be written as Equation 3.6. vmax =

X ×T R1 × C1

(3.6)

Where T is a total switching period. The integrator time constant, R1 × C1 ≤ T . Referring to Figure 3.8, the measured output current flowing through the current sensing resistor Rs , is compared with the (k ∗ vo (t) − vm (t)) in each switching cycle. The Equation 3.7 is the condition to turn of f the power switch. Then current starts falling until next cycle. Rs × io (t) = k × vo (t) − vm (t)

(3.7)

Where k is a constant and vm (t) is the voltage fall before the integrator is reset. As shown in Figure 3.8, vmax is the maximum voltage that can fall in each cycle. Thus vm (t) from equation can be described by Equations 3.8 and 3.9. vm (t) = −vmax ×

t f or t ≤ D(t)T T

vm (t) = 0 f or t ≥ D(t)T

(3.8) (3.9)

3.4

23

CONTROL PROCESS IN CIRCUIT

3.3.1 Input Parameter Relation for Current Control X can be controlled to adjust peak of the output current io (t). Equation 3.7 can be used to adjust the controller parameters for regulating the peak current. The output current has ripple, hence the peak doesn’t give the true power flow into the grid. But by reducing the ripple, the power flow can be regulated optimally by satisfying Equation 3.7. The ripple depends on effective switching frequency of the converter, inductor and integrator time constant. Mainly there are two ways to control the peak of current magnitude. 1. The control signal X. 2. Active and reactive current control by adjusting the phase and amplitude of the v(t). Referring to Equation 3.7, the output current peak in each switching cycle can be written as Equation 3.10. 1 (k × vo (t) − vmax × D(t)) io (t) = (3.10) Rs Smaller ripple gives higher power for the same peak current. The instantaneous power at unity power factor can be estimated by the Equation 3.11 for very low current ripple. Po (t) = vo (t) × io (t) =

X × T vo (t) vo (t) vo (t) (k × vo (t) − vmax × D(t)) = (k × vo (t) − ) (3.11) Rs Rs R1 × C1 Vg

Referring Equation 3.5, 3.6 and 3.11, the output power can be represented by Equation 3.12. Po (t) =

T X vo2 (t) (k − ) Rs R1 × C1 Vg

(3.12)

k controls the maximum power flow. Upon increasing X, the power level decreases. When Vg increases, the current magnitude increases again. Hence the DC control signal X is a function of DC voltage, while increasing Vg , the control signal X should be decreasing to increase the power injection into the grid. 1 v(t)

i(t)

t

Figure 3.9

Current and voltage signals at the input of comparator

3.4 CONTROL PROCESS IN CIRCUIT The integrated voltage output −vm (t) Equation 3.9 is added to the absolute reference AC voltage v(t). The result (k × vo (t) − vm (t)) is now compared with the absolute measured reference current signal i(t) as shown in Figure 3.9. While current is smaller, the switches are such that converter current is rising. Similarly, for higher current level, integrator resets and power switch

24

CHAPTER 3


turned of f . The stored inductive energy decays with negative current slope on each switching cycle. The simulated voltage and current waveforms are shown in Figure 3.10. Increasing X will increase the slope of −vm (t) and reduces the current io (t) rise time before it meets (k × vo (t) − vm (t)), which lowers the average output current and ultimately reduces the power flow.

1

Oscillator

0 1

Latch reset

0 1

Driver control

0 1

Integrator reset

0 1 Integrator output 0 0.071 0.073 Time (sec) Figure 3.10

0.075

0.077

Logic sequence and operation of SCC

The comparator and oscillator output are given to the Reset and Set pin of the SR latch as shown in Figure 3.7. The truth table for the SR latch is shown in Table 3.1. The output of

Reset (R) 0 0 1 1

Set (S) 0 1 0 1

Table 3.1

Q Don’t Care 1 0 unknown

Q0 Don’t Care 0 1 unknown

SR latch truth table

latch (Q) is used to drive the power switches. The inverting output of Q i.e. Q0 is used to reset the integrator. Hence, whenever the IGBT is turned of f the integrator resets instantly. The whole process for the Single Cycle Controller can be realized as shown in Table 3.2. Here i(t) is absolute measured value of current (Rs × io (t)) and (k × vo (t) − vm (t)) is the difference between absolute reference voltage signal and integrator output voltage on each cycle.

3.5

25

CONCLUSION

Comparator i(t)(k × vo (t) − vm (t))

R 0 0 1 1

S 0 1 0 1

Q Don’t Care 1 0 Not used Table 3.2

Q0 Don’t Care 0 1 Not used

Integrator Continue (Integration or Reset) Integrating Reset Not used

SCC logic sequence

3.5 CONCLUSION The Single Cycle Controller is an easy switching technique and suits for the power electronics converter control particularly for the grid connected applications. It can synchronize with the grid voltage as it forces the inverter output current to follow the reference voltage waveform. As the controller uses real time current for switch control, it increases the transient response of the circuit. The basis of Single Cycle Controller and its implementation in the circuit are explained. The simulation of the controller shows promising results from a handful of components avoiding any complex circuitry and numerical calculations.

Chapter 4 SWITCHING LOGIC FOR SINGLE CYCLE CONTROL

4.1 INTRODUCTION A current controlled voltage source inverter is used. The inverter is directly connected to the grid. Different switching strategies for a full bridge inverter are given. The development of switching logic and Boolean equations are presented. Full bridge operation in the four quadrant voltage-current plane is described. A limitation for the Single Cycle Controlled H-bridge during boost mode is discussed.

4.2 CONVERTER TOPOLOGY A simple single phase H-bridge inverter switch topology is used as shown in Figure 4.1. It is capable of driving high current at low voltage, hence is popular in medium power and photovoltaic (PV) applications. It has high efficiency. The other desirable features are high power density, high reliability and low electromagnetic interference (EMI) [36]. This topology allows flexibility to use the inverter in both two-quadrant (2Q) and four-quadrant (4Q) operation in the output voltage-current plane. 4Q operation allows bidirectional power flow and offers more controllability over the output voltage and current. This topology is implemented in hardware because of its simple structure and simple controllability. + Q1

D1

Q3

D3 R

Vg

+ vinv(t) -

C

Q2

D2

Q4

jXL vo(t) 50Hz

D4

-

Figure 4.1

Full bridge inverter

The drawback for the simple H-bridge topology is that it operates with hard switching, which reduces its efficiency at high switching frequency. Soft switching techniques such as zero voltage switching and zero current switching can be used to reduce the switching losses. However, these add more passive components and increase the complexity. To keep it simple, the switching strategy is designed in such a way that minimizes the switching losses, which will be described later.

28

CHAPTER 4

SWITCHING LOGIC FOR SINGLE CYCLE CONTROL

IGBTs are chosen as the power switches, which have a low conduction loss at high power capability and operate best at less than 100KHz switching frequency. The switching frequency is chosen to be much higher than the fundamental frequency.

4.3 CONVERTER SWITCHING STRATEGY The proposed switching strategy aims to increase the efficiency of the inverter with a simple logic implementation. There are three pulse width modulation (PWM) methods based on a switching frequency triangular waveform are popularly being used for the switching of full bridge inverter. 1. Unipolar Pulse Width Modulation (UPWM) 2. Bipolar Pulse Width Modulation (BPWM) 3. Hybrid Pulse Width Modulation (HPWM)

4.3.1 Unipolar Pulse Width Modulation UPWM controls the two legs of the single phase inverter independently. The switching PWM signals are generated by comparing a switching frequency triangular waveform with two control voltage signals for the two legs of the inverter. The advantage of UPWM is that the effective switching frequency of the output voltage is doubled, which reduces the ripple of the output current. The prospective inverter output voltage after UPWM is given in Table 4.1 for different switch states. The switches operating at high frequency switching are referred as SW f requency in the table. High side Q1 SW f requency on of f on of f

Low side

Q3 SW f requency of f on on of f

Q2 SW f requency of f on of f on

Table 4.1

Q4 SW f requency on of f of f on

Prospective voltage Vinv +Vg -Vg 0 0

UPWM switching options

4.3.2 Bipolar Pulse Width Modulation BPWM controls the switches of the two legs simultaneously. The switching PWM signals are generated by comparing a switching frequency triangular waveform with one control voltage and one of the switch pairs always remains on in each leg. The effective switching frequency of the output voltage is same as the triangular waveform. Hence, the ripple of the output current is higher than the UPWM switching strategy. The inverter prospective output voltage for the BPWM is given in Table 4.2 for different switch states.

4.3.3 Hybrid Pulse Width Modulation HPWM controls the two switches connected to the negative rail at the fundamental frequency, and selectively controls one or other of the switches connected to the positive rail at the switching frequency. Only one switch is ever switched at the switching frequency at any time. For

4.4

29

SWITCHING LOGIC CIRCUIT DEVELOPMENT

High side Q1 SW f requency on of f

Low side

Q3 SW f requency of f on

Q2 SW f requency of f on

Table 4.2

Q4 SW f requency on of f

Prospective voltage Vinv +Vg −Vg

BPWM switching options

example, one switch pair Q1 and Q4 are on at positive half cycle and another switch pair Q3 and Q2 are on at negative half cycle. Moreover, only one of the switch pairs operates at the switching frequency and the another is controlled at the fundamental frequency [37], whereas both the UPWM and BPWM control all switches at the switching frequency. This method reduces the high frequency switching losses, which offer some benefits for the hard switching full bridge inverter. It offers another advantage that the prospective output voltage is similar to the UPWM switching strategy, however it loses the frequency doubling effect of the UPWM. A similar strategy is also called UPWM switching because the HPWM and UPWM generate the identical output voltage [38]. The inverter prospective output voltage for the HPWM is given in Table 4.3 for different switch states. The switches operating at fundamental frequency are referred as F und f requency in the table. High side Q1 SW frequency on of f on of f

Low side

Q3 SW frequency of f on on of f

Q2 F und frequency of f on of f on

Table 4.3

Q4 F und frequency on of f of f on

Prospective voltage Vinv +Vg -Vg 0 0

HPWM switching options

The UPWM has less Total Harmonic Distortion (THD) and a lower distortion factor than the BPWM for single phase voltage source inverter [35]. The HPWM is chosen for hardware implementation because of its identical wave shape of inverter output voltage with the UPWM and lower switching losses.

4.4 SWITCHING LOGIC CIRCUIT DEVELOPMENT Simple digital logic has been developed to implement a switching strategy in the controller circuit. The parameters used for the logic development are the voltage polarity, current direction and switching states. The voltage polarity and PWM switching states are used for the switching logic development in 2Q operation while current direction is also considered for the 4Q switching operation. The voltage polarity and current direction for 4Q operation are considered as shown in Figure 4.2 and 4.3 respectively. Decision making conditions for the logic circuits are defined as listed below. 1. Positive voltage, positive current

30

CHAPTER 4


+ v(t), + io(t) - v(t), - io(t) t

+ v(t), - io(t)

- v(t), + io(t)

Figure 4.2

Current lagging waveform

+ v(t), + io(t)

- v(t), - io(t)

t

+ v(t), - io(t) Figure 4.3

- v(t), + io(t)

Current leading waveform

2. Negative voltage, negative current 3. Positive voltage, negative current 4. Negative voltage, positive current The logic used for the voltage polarity, current direction and switching states of the power switches is summarized in Table 4.4. Voltage polarity v+ve v−ve Current direction i+ve i−ve Switch state on of f Table 4.4

Logic representation 1 0 Logic 1 0 Logic 1 0

Logic development rules

Boolean equations are developed for each different switching strategy and implemented in the P SCAD simulation. The terminology used in the development of Boolean equations is defined in Table 4.5.

4.4

SWITCHING LOGIC CIRCUIT DEVELOPMENT

Terminology SW on of f v vg i Table 4.5

31

Definition On/Off at high switching frequency Stay On for half cycle Stay OFF for half cycle AC voltage DC voltage Inverter output current

Terminology used in development of Boolean equations

4.4.1 HPWM Switching Strategy First and second switching methods tested in HPWM switching strategy for 2Q and 4Q operation. First Switching Method Only one switch operates at switching frequency at any time. During positive half cycle Q1 is switching, Q4 is on and Q3 , Q2 are of f . During negative half cycle, Q3 is switching, Q2 is on and Q1 , Q4 are of f . First switching logic (HPWM) Two quadrant operation Four quadrant operation Prospective voltage Boolean equations: Boolean equations: Q1 = v × SW Q1 = v × i × SW Q2 = v Q2 = v × i × SW +Vg , 0, − Vg Q3 = v × SW Q3 = v + i × SW Q4 = v Q4 = v + i × SW Table 4.6

Boolean equations in first switching method

In 4Q operation during positive voltage and negative current Q2 is switching, Q4 is on and Q1 , Q3 are of f . During negative voltage and positive current Q4 is switching, Q2 is on and Q1 , Q3 are of f . The Boolean equations for switching are given in Table 4.6. Second Switching Method Second switching method only provides 2Q operation. Only two switches are operating at switching frequency in each half cycle. During positive half cycle Q1 and Q2 are operating alternatively at the switching frequency, Q4 is on and Q3 is of f . During negative half cycle, Q3 and Q4 are operating alternatively at the switching frequency, Q2 is on and Q1 is of f . The switching Boolean equations are given in Table 4.7.

4.4.2 Bipolar Switching Strategy The third and fourth switching methods are BPWM switching strategy.

32

CHAPTER 4


Second switching logic (HPWM) Two quadrant operation Prospective voltage Boolean equations: Q1 = v × SW Q2 = v + SW +Vg , 0, − Vg Q3 = v × SW Q4 = v + SW Table 4.7

Boolean equations in second switching method

Third Switching Method All four switches operate at switching frequency diagonally but only two at a time. When Q1 , Q4 are switching, Q3 , Q2 are of f . When Q3 , Q2 are switching, Q1 , Q4 are of f . The Boolean equations for third switching method are given in Table 4.8. Third switching logic (BPWM) Four quadrant Operation Prospective voltage Boolean equations: Q1 = v × SW + v × SW Q2 = v × SW + v × SW +Vg , − Vg Q3 = v × SW + v × SW Q4 = v × SW + v × SW Table 4.8

Boolean equations in third switching Method

Fourth Switching Method Only two switches operate at switching frequency at each half cycle diagonally in this switching method. In both 2Q and 4Q operations, during the positive half cycle Q1 , Q4 operate at switching frequency and Q3 Q2 are of f . During the negative half cycle Q3 , Q2 operate at switching frequency and Q1 , Q4 are of f . In 4Q operation, during positive voltage and negative current Q2 , Q4 operate at switching frequency and Q1 , Q3 are of f . During negative voltage and positive current Q4 , Q2 are operating at switching frequency and Q1 , Q3 are of f . The switching Boolean equations for each switch are given in Table 4.9.

4.5 SELECTION CRITERIA OF SWITCHING STRATEGY The switching strategy selection depends on various criteria. The primary criteria considered for the proposed inverter are listed as follows. 1. To improve the current performance during zero-crossings.

4.6

33

CONVERTER FOUR QUADRANT OPERATIONS

Fourth switching logic (BPWM) Two Quadrant Operation Four Quadrant Operation Boolean equations: Boolean equations: Q1 = v × SW Q1 = v × i × SW Q2 = v × SW Q2 = i × SW Q3 = v × SW Q3 = v × i × SW Q4 = v × SW Q4 = i × SW Table 4.9

Prospective voltage

+Vg , − Vg

Boolean equations in fourth switching method

2. To reduce the switching losses. 3. To enable bidirectional power flow. 4. To ease implementation in the circuit. The HPWM first switching method decreases switching losses due to only one switch operating at high frequency at any time. Current zero crossing performance for each strategy is compared in Chapter 5. The current is less distorted during zero crossings in this strategy. Thus the HPWM first switching strategy is implemented in hardware. vo(t)

vo(t) Q2 Switching

Q1 Switching

Q2 Switching

Q1 Switching

Q4 on

Q4 on

Q4 Switching

Q4 Switching

Q1, Q3 off

Q2, Q3 off

Q1, Q3 off

Q2, Q3 off

II

I

III

IV

io(t)

II

I

III

IV

io(t)

Q3 Switching

Q4 Switching

Q2 on

Q2 Switching

Q2 Switching

Q1, Q3 off

Q1, Q4 off

Q1, Q3 off

Q3 Switching

Q4 Switching

Q2 on Q1, Q4 off

Figure 4.4

4Q operation 1.HPWM 2.BPWM

4.6 CONVERTER FOUR QUADRANT OPERATIONS The H-bridge inverter from Figure 4.2 can be decoupled into four different circuits representing different quadrants operation of the voltage-current plane. Figure 4.4 shows 4Q switching for HPWM and BPWM. The inverter operates in buck mode during first and third quadrants, thus the voltage polarity and current direction will always be the same. It operates in boost mode during second and third quadrant operations. The 4Q operation as shown in Figure 4.4 allows more options for control of the voltage and current. With little additional logic 4Q can be implemented.

34

CHAPTER 4


4.6.1 Buck Mode The inverter works in buck mode during first and third quadrants operation. Figure 4.5 shows equivalent circuit for buck mode operation. The current flows from DC side to AC. The AC voltage polarity is positive in first quadrant. Q1 is switching, Q4 is on and diode D2 is active. The voltage polarity is negative in third quadrant. Q3 is switching, Q2 and D4 are on. L

R

io(t) Q3

Q1 D2

Vg

vo(t)

R

Figure 4.5

vo(t)

D4

Vg

L

io(t)

Equivalent buck circuit for 1. First quadrant 2. Third quadrant

4.6.2 Boost Mode The inverter works in boost mode during second and fourth quadrant operation of voltage current plane. Figure 4.6 shows equivalent circuit for boost mode operation. The current flows from AC voltage to DC side. The voltage polarity is positive during the second quadrant. Q2 is switching, Q4 , D4 and D1 are on. The voltage polarity is negative during the fourth quadrant. Q4 is switching, Q2 , D2 and D3 are on.

D3

D1 L

R

io(t) Vg

Vg vo(t)

Q2

Q4 R

Figure 4.6

L

vo(t) io(t)

Equivalent boost circuit for 1. Second quadrant 2. Fourth quadrant

4.6.3 Constraints During Boost Operation During buck mode, the H-bridge operates in continuous current conduction. During boost mode, near zero crossing of voltage waveform, the inverter operates in discontinuous current conduction, as the inductor can not store enough energy during the on period and the inductor de-energizes too quickly during the of f period. Prior to disruption of the SCC in boost mode, the latch set and reset occur at the same time. The switch is turned of f and the current ramps down for longer (at 0.069s in Figure 4.7), as the

4.7

35

CONCLUSION

falling integrator output is unable to meet current within a cycle. Then the integrator is reset (at 0.0695s) after two complete switching cycles. Consequently switching frequency appears halved during the period and distorts the output current for few switching cycles. After the few switching cycles , the controller regains its control. The logic to avoid the same level state in set and reset does not improve the disturbance in boost mode. The logic needs to be extended to reset the integrator using an external signal during disrupted cycles only. The distorted current and missed switching logic during the discontinuous operation of the inverter is shown in Figure 4.7. Reset pulse Control signal

Current

0.5

Latch set

0 0.0685

0.069

0.0695

0.07

0.0705

0.0685 1

0.069

0.0695

0.07

0.0705

0.069

0.07 0.0695 Time (sec)

0.0705

1

Q

0

0

0.0685

Figure 4.7

Current distortion during boost mode

The current waveform can be improved by increasing the inductor size or increasing a time constant of the integrator. The increasing of inductor size is not practicable. The inverter current is tested at different integrator time constants during buck and boost mode operations. It helps to regain the current waveform during boost mode at larger time constants of the integrator, but the time constant is always smaller than the switching frequency. Another possibility is to change the inverter topology to augment the performance during boost mode. Finding a suitable inverter topology could be considered for future work.

4.7 CONCLUSION A simple H-bridge inverter topology is used. Different switching strategies and their logic development for the full bridge inverter are described. The hybrid PWM switching is suitable to reduce switching losses and increase the inverter efficiency. The current direction and voltage polarity are used to develop the logic sequence for the inverter switching in four quadrant operation. The inverter operation in each quadrants is described. The Single Cycle Controller malfunctions during reactive current flow due to discontinuous current operation of the H-bridge. This requires more study to develop a better topology or switching or Single Cycle Control strategy to improve the current performance during boost mode. Finally, the hybrid PWM switching strategy (first switching method) for 4Q operation is implemented in the hardware.

Chapter 5 SINGLE CYCLE CONTROL CURRENT WAVEFORM

5.1 INTRODUCTION Single Cycle Controlled output current waveform depends upon various factors, for example shape of the current ordered AC signal, integrator slope, inductance, DC and grid voltages. The real time inductor current is used to control the duty cycle of the power switches. The Single Cycle Controlled current has zero crossing distortion. However, a switching strategy with minimum distortion is used in hardware. An optimum approach is described to operate the inverter in unipolar mode for most of the AC cycle and to operate in bipolar mode near zero crossings [38]. Unipolar PWM and bipolar PWM switching strategies are not used in the proposed inverter due to high switching losses in compare to hybrid PWM. This chapter describes the current zero-crossing wave shape for different hybrid PWM and bipolar PWM switching strategies. The current harmonic spectrum is presented. Finally, a logic circuit is presented to fix this issue.

T v(t) = k × vo(t)

-x1 imax(t) -vo(t)/L irip(t)

Ioav

(Vg-vo(t))/L imin1(t)

D(t)T

imin2(t) (1-D(t))T

t=0

Figure 5.1

Current control in one switching cycle

38

CHAPTER 5

SINGLE CYCLE CONTROL CURRENT WAVEFORM

5.2 CURRENT CONTROL Figure 5.1 illustrates current control using the SCC for one switching cycle. Suppose Vg and vo (t) are DC source and AC supply voltage respectively. When the switch turns on, the current V −v (t) starts from imin1 (t) with a slope of g Lo until the integrator is reset. When the switch turns of f , the current falls from imax (t) to imin2 (t) with a slope of −vLo (t) . The current level imin1 (t) and imin2 (t) are different. The shape of average current ioav is expected to be close to that of v(t). Peak to peak ripple current irip (t) depends on the voltage difference between Vg and vo (t), which is bigger when vo (t) is low and smaller when vo (t) is high.

5.3 ZERO-CROSSING CURRENT The voltage across the inductor vL (t) in the circuit shown in Figure 5.2 is the difference between Vg and vo (t). L +

io(t)

Switches

vL(t)

Vg

vo(t) 50Hz

Figure 5.2

Power circuit

The waveforms for Vg , vo (t) and vL (t) are shown in Figure 5.3 for the HPWM first switching method. Vg

vo(t) vL(t)

-vo(t) s Figure 5.3

vL (t), Vg , vo (t) for HPWM first switching method

vL (t) defines the change in current with respect to time, didto , flowing through the inductor. Figure 5.4 illustrates that during beginning of the fundamental cycle, when vo (t) is low, the rise in output current didto through the inductor is high. Similarly, when vo (t) is high, the rise in inductor current is small. For half fundamental cycle, the switch duty cycle increases from 0o di all di is high and o,f is slow around the AC to 90o and falls from 90o to 180o . Hence the o,rise dt dt dio,f all dio,rise voltage zero-crossings and the dt is slow and dt is high around the voltage peak.

39

ZERO-CROSSING CURRENT

5.3

3.5

{ dio,fall/dt < dio,rise/dt

{

Current, A

dio,fall/dt > dio,rise/dt

0 0.061

0.062

0.063

Figure 5.4

0.064

0.065 Time (sec)

0.066

0.067

0.068

0.069

Current ripple for HPWM first switching method

The current falls slowly when vo (t) is near zero. Consequently the current falls more slowly than the voltage and the zero-crossing is delayed. The current performance for different switching strategies is summarized in each subsection. The switches Q1 , Q2 , Q3 , Q4 and diodes D1 , D2 , D3 , D4 mentioned in subsections are referred to the bridge inverter as shown in Figure 4.2.

5.3.1 HPWM Switching Strategy The switching operation is already descibed in Chapter 4. The current performance for each method is given. First Switching Method

Output Voltage (V), Current (A)

The current shape is identical in 2Q and 4Q operation. AC supply voltage and current waveforms near zero crossing are shown in Figure 5.5. In the positive half cycle, this provides inverter terminal voltages of +Vg and 0. In the negative half cycle, this provides inverter terminal voltages of −Vg and 0. Voltage scale = 1 Current scale = 0.1

10

Current zero 0 Voltage zero -10

0.0685

Figure 5.5

0.069

0.0695

0.07 Time (Sec)

0.0705

0.071

0.0715

Grid voltage and output current near zero crossing for 2Q first switching method (HPWM)

Prior to the zero crossing of positive half voltage and current, the switch Q1 is turn of f . But inductor current keeps flowing through the switch Q4 and diode D2 with an exponential decay and delays the current zero. As soon as the negative voltage starts, current drops to zero steeply and flows through the switches Q3 and Q2 .

40

CHAPTER 5


Second Switching Method


In the positive half cycle, this provides inverter terminal voltages of +Vg and 0. In the negative half cycle, this provides the terminal voltages of −Vg and 0. The output current and voltage 20

Voltage scale = 1 Current scale = 0.1

10 Current zero 0 Voltage zero -10 -20 0.0685

Figure 5.6

0.069

0.0695

0.07 Time (sec)

0.071

0.0705

0.0715

Grid voltage and output current near zero crossing for 2Q second switching method (HPWM)

waveforms during zero crossing are shown in Figure 5.6. It has worse current waveform during the zero crossings. The current fall is slower than the voltage. When the switches Q3 and Q2 are of f , the positive current flows through the switch Q4 and diode D2 . After the negative cycle starts, the positive current keep flowing through the switch Q4 and diode D2 instead of going to the negative direction. It requires extra logic to turn of f the Q4 or Q2 immediately before the next cycle starts to fix the problem.

5.3.2 Bipolar Switching Strategy The inverter operation in bipolar switching strategy is described in chapter 4. Third Switching Method


For full cycle, the switches Q1 , Q4 and Q3 , Q2 operate at the PWM switching frequency diagonally. In both half cycles, this provides inverter terminal voltages of +Vg and −Vg .

4

Voltage scale = 1 Current scale = 0.1

2

Voltage zero

0 -2

Current zero

Current zero

-4 0.0685

Figure 5.7

0.069

0.0695

0.07 Time (sec)

0.0705

0.071

Grid voltage and output current near zero crossing for third switching method (BPWM)

This allows reduction of stored inductor energy quickly. Prior to zero crossing of the voltage, negative current flows through the inductor. The controller senses the absolute value of current. When the negative half cycle starts, the switches Q3 and Q2 are on, which add more negative current resulting undesirable high current for a short period. The output current and voltage waveforms during zero crossing are shown in Figure 5.7.

5.4

41

CURRENT HARMONICS

Fourth Switching Method


The current shape is similar in 2Q and 4Q operation near zero crossings. The output current and Voltage scale = 1 Current scale = 0.1

5

Current zero 0 Voltage zero

Current zero -5 0.0685

Figure 5.8

0.069

0.0695

0.07 Time (sec)

0.0705

0.071

0.0715

Grid voltage and output current near zero crossing for fourth switching method (BPWM)

voltage waveforms during zero crossing are shown in Figure 5.8. Even though the prospective voltages goes from +Vg to −Vg , the current fall near zero crossing has an exponential decay. The switch Q4 turns of f prior to zero crossing of the voltage waveform and the output current reaches zero ahead of the voltage with the exponential decay. Similarly, the current delays to start in the next half cycle. The current waveform is symmetric with the voltage, but contains high order harmonics.

Current (A)

3

2 THD = 3.6% 1

0

20

10

30

40

50

60

Harmonic order Figure 5.9

Output current harmonics

5.4 CURRENT HARMONICS The SCC controlled inverter current contains odd harmonics. Figure 5.9 illustrates the magnitude of the fundamental and harmonic currents. The harmonic spectrum is measured for the inverter operating in 4Q operation and the first switching method as described in Chapter 4. High frequency harmonics in the order of switching frequency are also observed, which can be minimized with a application of filter. The current Total Harmonic Distortion (THD) for the shown spectrum is calculated as 3.6%, which compliances the Australian Standard 4777.2 (Grid connected of energy system via inverters) is an acceptable level to inject into the grid. Increasing the fundamental current magnitude reduces the THD. The harmonic distortion is due to the switching frequency ripple and Single Cycle Control loss of control near waveform zero-crossing.

42

CHAPTER 5


5.5 LOGIC CIRCUIT TO IMPROVE CURRENT WAVESHAPE A SR latch is used in the SCC to reset the integrator after a certain time period. The latch enables the controller to operate at fixed frequency and preserves the SCC principle. As the real time current is taken for the controller, any distortion in the output will affect it. The nature of current distortion at zero-crossing at various switching strategies is shown in section 5.3. A logic circuit is used to minimize the effect of the distortions.

R 0 0 1 1 Table 5.1

SW 0 1 0 1

SW1 1 1 1 0

SW2 0 1 0 0

New truth table after addition of new logic

As shown in truth table of the SR latch Table 3.1, the 1-1 input state is unknown for its output. If the current fall is slower than the voltage, the latch can be in the unknown state near the zero crossings. A logic circuit is used to avoid the unknown states. Using N AN D, AN D and N AN D − latch as shown in Figure 5.10, the circuit is able to force both the output state low. The set and reset input for the N AN D − latch are active low, thus a N OT is added at the input of the latch. The truth table after addition of logic is obtained as shown in Table 5.1. Oscillator (SW)

AND

SW2

S

NAND

SET

Q

SW1

Reset (R)

R

CLR

Q

NOT

Figure 5.10

Additional logic on SR latch

However, the problem at zero crossings still persist even if the latch closes the switch, because the rising current signal is higher than the falling integrator output. The current near zero crossing flows continuously until the next cycle starts as shown in Figure 5.11.

Voltage and Current

0.1

Exponential decaying of inductor current

0.02 0 0.0692

0.0694

0.0696

0.0698

0.07

0.0702

Time (sec)

Figure 5.11

SCC controller signals waveform near zero crossing

0.0704

0.0706

5.6

CONCLUSION

43

5.6 CONCLUSION The Single Cycle Controlled inverter current performance is presented for ranges of switching strategies. The current depends on the shape and magnitude of the current ordered AC signal, the integrator DC signal and the DC source and grid voltages. The zero crossing performance and the current waveform distortion for various switching strategies has been presented. It can be minimized by switching at high frequency near zero crossing and using bipolar switching strategy. After implementing a new logic circuit, the current distortion level reduces. As the distortion is less and occurs for a short period of time near zero-crossings, it has less effect. The converter current Total Harmonic Distortion has found by simulation to be 3.6% at rated current.

Chapter 6 FOUR QUADRANT POWER CONTROL

6.1 INTRODUCTION The inverter power capability mainly depends on the DC side voltage, filter impedance and the grid RMS voltage [39]. The power rating of the inverter is also limited by rating of the power switches, filter etc. The inverter peak current control using integrator slope is discussed in Chapter 3. Another possibility to control active and reactive current injection is varying magnitude and phase of the current ordered AC signal in Single Cycle Control. The proposed current controlled inverter is featured with bidirectional power flow capability. It is proposed to independently control active and reactive current injection. This enables reactive power compensation into low voltage grid from small power sources. Voltage stability is of key importance in low voltage grids, and can be achieved by mixed real and reactive current support from inverters at suitable locations in the grid. The inverter is proposed to inject or absorb reactive current depending on the AC supply voltage. The proposed inverter needs a new reference waveform to generate suitable active or reactive current. A new AC waveform generation method is discussed. A novel synchronized waveform generation method implementable in a microcontroller is proposed.

6.2 POWER CONTROL The inverter current waveform normally follows the AC signal used in the SCC. Reactive current control can not be implemented if the signal is directly taken from AC supply voltage. Key advantages of using a new generated AC signal vnew (t) are listed as follows. 1. Less sensitivity to grid voltage distortion. 2. Independent active and reactive power control.

6.2.1 Controller Strategies The signal vnew (t) can be decoupled into in-phase and out-of-phase components. Independent variations of the in-phase and out-of-phase components give magnitude and phase variations of the control signal vnew (t). Magnitude of the in-phase and out-of-phase signals depend upon the DC source and AC supply voltage. Two multiplying factors are introduced whose magnitudes vary according to the voltages. Each component is multiplied by the factors and summed to get

46

CHAPTER 6

FOUR QUADRANT POWER CONTROL

the vnew (t). Suppose kp and kq are multiplying factors for in phase and out of phase components. kp ≤ 1, kq ≤ 1. Figure 6.1 illustrates vnew (t) as the summation of two independently variable waveforms. In phase × 1

1

Out of phase × 0.6

Volt

0.5 0

-0.5 -1 0.06

0.062

0.064

0.066

0.068

Volt

1

0.07 0.072 Time (sec)

0.074

0.076

0.078

vnew(t)

0 -1 0.06

0.062

0.066

0.064

0.068

Figure 6.1

0.07 Time (sec)

0.072

0.074

0.076

0.078

New waveform generation

vnew (t) = kp × sin(wt) + kq × cos(wt)

(6.1)

If, kp = km × cosφ and kq = km × sinφ Then vnew (t) can be written as equation 6.2. vnew (t) = km × sin(wt + φ)

(6.2)

Figure 6.2 shows a block diagram of the independent active and reactive power control strategy. DC side voltage is measured across the capacitor and compared with ordered DC voltage for active power control. Similarly, absolute measured AC supply voltage is compared with ordered AC voltage for reactive power control. Proportional control is used in both to respond to the measured voltage deviation from ordered value and assign multiplying factors for synchronized in phase and out of phase components. This strategy requires that two waveforms, synchronised with the grid voltage and 90o separated be available. Generation of these waveforms discussed in section 6.4.

6.2.2 Active Power Control Increasing magnitude of the in-phase component Equation 6.1 increases the amount of active power injection into the grid. The decision is made based on the DC side voltage. If the voltage tends to go high the inverter injects more active current, which acts to reduce DC side voltage. Similarly, when DC voltage goes low, the active current reduces, which eventually helps to boost the DC side voltage. For small DC voltage, the inverter absorbs reactive power from the grid. Protection system should be implemented for the DC side voltage for higher or smaller than the

6.3

47

VOLTAGE CONTROL

vnew(t)

sin

+ +

*

cos

*

P

P

Synchronization (Out of phase)

Synchronization (In phase)

Error

Error Vg Measured

+

+ -

-

Vg Ordered

|Vac| Ordered

Active power Figure 6.2

|Vac| Measured

Reactive power Power control strategy

overvoltage and undervoltage limit. Figure 6.3 shows a simulation of active and reactive power injection into grid from proposed inverter. Q

P (W), Q (Var)

1000

P

500

0

-500 0

0.05

Figure 6.3

0.1

0.15 Time (sec)

0.2

0.25

Active and reactive power injection into the grid using SCC

6.2.3 Reactive Power Control Changing magnitude of the out-of-phase component in Equation 6.1 mainly changes the phase of the vnew (t) if the reactive power component is small compared to the real power component. It helps to achieve leading or lagging inverter current with respect to the grid voltage. The grid voltage magnitude is taken as a reference to decide phase for vnew (t). If the grid voltage tends to drop, by whatever reason, the controller shifts the vnew (t) to lead the grid voltage, so that it supplies reactive power to the grid. If the grid voltage tends to go high, the converter absorbs reactive power from the grid. Figure 6.4 shows a dynamic simulation of reactive power absorbed by the inverter while supporting active power into grid.

6.3 VOLTAGE CONTROL The converter connection to the low voltage grid is shown in Figure 6.5. The resistance of the low voltage grid Rgrid cannot be neglected. When the load draws current from the grid, the

48

CHAPTER 6


P (W), Q (Var)

1000 500 P 0 Q -500 -1000 0

0.05

0.2

0.15

0.1

0.25

Time (sec)

Figure 6.4

Active power injection into the grid and reactive power absorption from the grid using SCC

terminal voltage Vo drops below the fundamental voltage magnitude. The voltage drop depends on load current, grid impedance and auxiliary grid support at the connection point.

Rgrid Igrid

Xgrid

Xinv

Vzgrid

+

+

Vzinv

I +

Vo

E -

Vinv -

-

Inverter

Grid Figure 6.5

Inverter connected to grid

The inverter should compensate the voltage drop due to grid impedance and loads. This requires both active and reactive current injection. The filter impedance between inverter and grid is highly inductive. The inverter voltage magnitude controls the reactive power flow into the grid. Similarly, the angle between the converter

Vo I Vinv

Vzinv Vo

Figure 6.6

Vzinv

δ

Vinv

I

Phaser diagram for 1. reactive power only 2. active power only

and grid voltage controls the active power flow. Figure 6.6 shows phasor diagrams for independent reactive and active power flow. The proposed inverter aims to modulate real and reactive current injection for voltage control. Figure 6.7 shows the phasor diagram for real and reactive compensation for the low voltage grid. It shows that the injected current should be phase shifted from the voltage by the system characteristic impedance angle for the best voltage compensation.

6.4

49

IMPLEMENTATION OF NEW GENERATED WAVEFORM

Igrid o

45 Vzgrid

Vo

Vzinv o

45

E I

Figure 6.7

Real and reactive power compensation

6.4 IMPLEMENTATION OF NEW GENERATED WAVEFORM A 32-bit microcontroller ST M 32F 103RB [42] is used to generate the new AC signal vnew (t). ST M 32 has 16-bit timers featured with PWM or pulse counter. PWM output at variable duty cycle is generated using look up table. C-programming code for waveform generation is given in Appendix A [43]. The look up table consists of 296 elements, which gives the duty cycle for each pulse and is varied sinusoidally to get sinusoidal waveform. Frequency of PWM is defined by value assigned in auto reload register and it can be updated during controller operation. A simple first order RC high pass filter is used to remove the 2.5V DC offset output from microcontroller output and get 50Hz AC reference wave. Two waveforms are generated with 90o phase difference and added to get the control signal vnew (t) as given in Equation 6.3. The waveforms are synchronized with the grid fundamental voltage. Any frequency changes in the grid will update the time period to update to synchronize the frequency of the signal vnew (t).

6.4.1 Phase Synchronization Phase synchronization is a challenging issue in weak power systems. Phase locked loops are mainly used for three phase systems, whereas zero crossing detection is used for single phase systems. Due to distortion during zero crossings, peak detection method is used in some work. But it is strongly affected by harmonics and wave shapes. Phase detection is the main task for the synchronization. A novel method implementable in microcontroller is proposed for phase synchronization in a single phase system.

Vo(t)

Angle detect

θm +

P

+

I 1/s

θestim Look-up table sin cos Figure 6.8

Phase locked loop diagram

Figure 6.8 shows block diagram for proposed PLL based phase synchronization method. The

50

CHAPTER 6


phase detection block is used to measure phase angle θm of the AC voltage. The angle is compared with θestim from the look up table used for waveform generation. A PI controller is used to respond to the error between the measured angle and the estimated angle. The PI corrected output needs another integrator to convert into angle which gives desired phase angle for sin θ and cos θ wave generation. If the integrator output gives angle greater than 360o , it is reset to zero. Phase Detection Zero-crossing detection gives unreliable results during voltage distortions. |tanθ|

cosθ

vo(t)

|sinθ|/|cosθ|

ωo/s Figure 6.9

Look up table

θ

sinθ

Phase angle detection block diagram

The α − β transformation reduces 3-phase waveforms to orthogonal components, from which phase angle can be directly calculated. The proposed method integrates the voltage waveform to deduce an orthogonal component, from which phase angle be directly calculated. It is important that the integrator gain is chosen so that the resultant waveform is the same magnitude as the measured voltage at the nominal frequency and the integrator needs to forget information more than a few cycles old so that any DC offset is forgotten. Integration rather than differentiation is chosen due to its relative insensitivity to waveform distortion. The final phase calculation is implemented through a look-up table as shown in Figure 6.9. Integrator Design The integrator output depends on phase and magnitude of input AC signal. The requirements are the output must be in similar amplitude and 90o phase difference to the input signal. The integrator filter is important to keep the same amplitude and maintain the phase difference.

R2 C1 Vin

R1

Vout + Rb

Figure 6.10

Continuous integrator

6.4

51

IMPLEMENTATION OF NEW GENERATED WAVEFORM

Figure 6.10 shows an integrator. The addition of large value of resistor R2 across capacitor R2 at C1 gives the circuit characteristics of an inverting amplifier with finite closed loop gain of R 1 low frequencies while acting as an integrator at high frequencies. Any initial DC offset is lost.

vin (t) = Vm cos 2πf t

(6.3)

After integration, the output voltage will be 1 vout (t) = RC

Z

vout (t) ==

Vm vin dt = RC

Z cos 2πf tdt

Vm sin 2πf t + C 2πf RC

(6.4)

Where, C is the initial offset voltage. The gain can be calculated with constant is 0.01.

1 2πf RC .

The RC time

Hence, C = 0.01µF , R2 = 100K, R1 = 31K. Rb = 22K (Bias resistance).

Phase Angle Calculation Figure 6.11 shows input cos θ and integrated output sin θ. tan θ and prospective angle in each quadrants is shown in Figure 6.12. The phase angle can be realized in four quadrants of the sin θ − cos θ plane for a fundamental cycle as shown in Figure 6.13. The operating quadrant of 1

cosθ

0 sinθ -1 0.072

0.074

0.076

0.078 0.08 Time (sec)

Figure 6.11

0.084

0.086

0.088

sin θ and cos θ

90

o

Angle(|θ|)

|tanθ|

10

0.082

5

0

0 0.072

0.076

0.08 Time (sec)

0.084

0.088

Figure 6.12

0.072

0.076

0.08 Time (sec)

0.084

0.088

1. tan θ 2. Phase angle

the rotating angle vector can be decoupled using the logic representation in Table 6.1. A look up table is required to find angle for inverse of tan θ. The table can be built for first quadrant only, for different quadrants angle vector the angle is added to the measured angle as shown in Table 6.2.

52

CHAPTER 6

Function sin θ sin θ cos θ cos θ Table 6.1

Direction +ve −ve +ve −ve

Logic representation 1 0 1 0

Logic to find the operating sin θ − cos θ plane

sin θ 1 1 0 0 Table 6.2


cos θ 1 0 0 1

Phase angle(φ) φ = θ + 00 φ = θ + 900 φ = θ + 1800 φ = θ + 2700

Logic to find the operating sin θ − cos θ plane

6.4.2 Lookup Table Development for Angle Measurement The microcontroller is not featured with inverse tan θ function calculation. A look up table method is proposed to detect phase angle in each quadrant of sin θ − cos θ plane. The angle vector is rotating in all quadrants for complete cycle, but using absolute value and detecting direction of sin θ − cos θ helps to reduce the size of the table for inverse tan θ function. The microcontroller has a 12-bit resolution analogue to digital converter (ADC). The lowest significance 5-bit can be neglected to read angle for each quadrant. Remaining the most significant 7-bit records angle for 128 different values as shown in Figure 6.14. After each conversion, the A/D converted value used to look up the estimated angle from the table. Each ADC converted value represents phase angle in each quadrant. Table 6.3 computes the angle for each converted value. After detecting tan θ and its quadrant, the angle can be decoupled. The table is computed for one quadrant and depending upon operating quadrants of rotating vector, corresponding angle is added as shown in Table 6.2. The look up table for waveform generation consists of 296 elements for complete cycle 2π. sinθ o 90 cosθ -ve sinθ +ve 180

o

II

III cosθ -ve sinθ -ve

cosθ +ve sinθ +ve I

o

cosθ

IV cosθ +ve sinθ -ve 270

Figure 6.13

0

o

4Q sin θ − cos θ plane

6.5

53

CONCLUSION

6 5 4 3 2 1 0

{ {

11 10 9 8 7 7

Don’t care

2 = 128 Figure 6.14

ADC register

ADC converted value (Hex value) 0 . . 20 . . 40 . . 60 . . 7f Table 6.3

Phase angle (Degree) 0 . . 22 . . 45 . . 68 . . 90

Phase angle decoupling

Angle for xth element is decoupled by Angle = x ×

2π × 57.29 (in degree) 296

(6.5)

The measured angle is compared with the estimated angle from the waveform generation table continuously.

6.5 CONCLUSION An extended power control strategy for the Single Cycle Controller is proposed. P SCAD simulated results are presented for active and reactive power control. It requires new generated current ordered AC signal. Major advantages of using new current ordered waveform are less current distortion and independent control over active and reactive current. It is proposed to use microcontroller for new waveform generation featured with independent phase and magnitude control. The proposed technique allows the inverter for independent active and reactive current injection into grid. A novel idea for synchronization of new generated single phase wave implementable in microcontroller is proposed.

Chapter 7 SIMULATION, DESIGN AND PROTOTYPE DEVELOPMENT

7.1 INTRODUCTION The proposed grid connected inverter is simulated in P SCAD/EM T DC. The system includes a Single Cycle Controller, inverter, DC source and low voltage grid. The grid voltage is assumed ideal for the simulation. An analogue controller circuit is designed taking reference from the simulation. The controller board is built using surface mount components on four layer printed circuit board. Insulated Gate Bipolar Transistors (IGBTs) are used and built on a double layer printed circuit board for the inverter. A test rig is prepared. This chapter explains the simulation and hardware design considerations. A controller circuit design is presented. Finally, the prototype development and experimental results are presented.

7.2 SIMULATION The aim of simulation is to find out controller performance and transient behavior of the single phase inverter during grid connection. It is used to study output current distortion, inverter operation for different switching strategies , power flow etc. The parameters used in simulation are tabulated in Table 7.1. DC side Parameter DC Source 400V Capacitor 150µF Single phase grid Line Voltage 230V Frequency 50Hz AC side parameter Inductor 40mH Series resistance 0.1Ω Controller parameters Switching Frequency 5KHz Integrator time constant 0.5µs Table 7.1

Simulation parameters

56

CHAPTER 7

SIMULATION, DESIGN AND PROTOTYPE DEVELOPMENT

The time constant for the resettable integrator is smaller than the switching frequency to ensure that the integrator is reset before the start of the next switching cycle. The controller loses its principle of operation, if integrator cannot reset within the switching time period. The selection of time constants also depends on inductance of the inverter output filter. IGBTs with reverse diodes and snubbers are used for the inverter simulation. The grid voltage is considered as an ideal source, but it is not possible to get an ideal source in practice. The grid has its own impedance. Initially, the current ordered AC signal for the controller is taken directly from the grid. The advantage is that the controller forces the current to have the same phase as the grid voltage. However, if grid voltage is distorted, it contributes to a poor current waveform. Thus, to make the current less vulnerable to the grid distortion and to enable reactive current injection, a generated AC signal is used to control the current. This enables the controller to inject a good current waveshape and consequently improve grid voltage distortion by increasing a fundamental component. The simulated controller signals are shown in Figure 7.1 and the grid voltage and output current are shown in Figure 7.2. Current controlled signal 5V

Scaled real time current 0 0.062

0.064

0.066

0.068

0.07

0.072

0.074

0.076

0.078

Time (sec)

Figure 7.1

32.5

The SCC control signals

V scale: 0.1x I scale: 10x

Voltage (V)

0 Current (A)

-32.5 0.062

0.064

0.066

0.068

0.07

0.072

0.074

0.076

0.078

Time (sec) Figure 7.2

Grid voltage and output current

7.3 CONTROLLER CIRCUIT The controller circuit comprises a resettable integrator, oscillator, adder, SR latch, logic, comparator and current detection module as shown in Figure 3.7.

7.3.1 Oscillator An oscillator is used to generate a switching frequency which enables the latch and sets a constant frequency for the inverter switching. The oscillator frequency is chosen at 5kHz. The frequency is good for IGBT switching operation. Lower frequency reduces switching losses and increases efficiency of the inverter but increases the AC current distortion. Universally accessible

7.3

57

CONTROLLER CIRCUIT

timer 555 is used as an oscillator. The timer output has a 5% duty cycle square wave. Only a narrow pulse is required to set the latch, thus a small duty cycle is chosen. High frequency back to back diodes are used to set the different time constants during charging and discharging to get 5% duty cycle output as shown in Figure 7.3. The circuit parameters for the timer are;

R1 Vcc Disc

R2

Rst

Trig Out

Thr

C

Gnd

Cvolt

Figure 7.3

Timer 555

R1 = 1.4K, R2 = 28K, C = 0.01µF.

7.3.2 Resettable Integrator A resettable integrator is an important part of the SCC to control the PWM for inverter switching. An op-amp T L074 is used to make an analogue integrator as shown in Figure 7.4. A Reset pulse Analogue switch C

Vdc R -

Vout +

Figure 7.4

Resettable integrator

capacitor is connected at the feedback from output to an inverting input pin. The initial voltage at the inverting input pin is zero, because the non-inverting pin is grounded. Whenever the DC voltage is applied at the input of the integrator, the capacitor charges from 0V to −Vcc at the designed time constant. When the integrator is reset, it goes from −Vcc to 0V quickly. Thus, the voltage across capacitor is varied from 0V and −Vcc . A CMOS analogue switch (ADG619) is used to reset the integrator. The circuit diagram and logic representation for the switch is shown in Figure 7.5. When the latch output Q goes high, the switch S2 is on, and the capacitor discharges quickly through series resistance connected in the switch. The series resistance is small and used to limit the current during transient voltage

58

CHAPTER 7


switching across the integrator. As the turn on resistance for the switch is very small, the capacitor discharges very quickly and the reset the integrator.

Latch output Q

VDD

2

S1

8

S2

6

IN

5 3

D

+5V 4 0.01uF

1

Logic representation for ADG619 Latch output Q Switch S2 off 0 on 1

-5V

VL GND

VEE

7

ADG619 0.01uF

10.0Ω

2.2nF

Across integrator

Figure 7.5

Analogue switch

The integrator parameters are designed from the measured frequency and duty cycle. The integrator time constant must be smaller than the switching frequency. Let, maximum fall in integrator slope = −4V Measured switching frequency = 5.4kHz Switching period = 185µsec Hence, change in voltage with respect to time is, =

4V 185µs

V = 21.62 ms

So, for capacitor (C)= 2.2nF V Current(i) = C dV dt = 2.2nF × 21.62 ms = 47.56µA

Resistance (R) = 84.1kΩ Thus, the integrator parameter are chosen as C R = 100kΩ.

=

2.2nF and

7.4 VOLTAGE AND CURRENT DETECTION A HCPL788j [45] isolated differential amplifier is used to detect the AC voltage and inverter output current. The amplifier has an analogue rectified output (ABSVAl) as required in the SCC. A resistive divider circuit is used to scaled down the grid voltage peak to 5V level for the controller purposes. The maximum recommended input voltage to the amplifier is ±200mV . The output voltage gain is nearly 10 for 5V supply and reference voltage input to the amplifier. A 0.02Ω series resistor is used in series with inverter output for current detection purposes up to a peak rating of 10A. Two separate isolation amplifiers are used for the voltage and current as shown in Figure 7.6, and the output of each is passed through buffer amplifiers. The AC voltage output has a 2.5V DC offset. An RC high pass filter is used to avoid the offset level in the controller circuit.

7.5

59

LOGIC CIRCUITRY

39.0Ω

39.0Ω

io(t)

0.04Ω 0.1uF AC GND +5isolated 0.1uF

1 2 3 0.1uF 4 5 6 7 8

AC GND

Vin+ Gnd2 VinVdd2 CH Fault CL ABSVAL Vdd1 Vout VLed+ Vref Vdd1 Vdd2 Gnd1 Gnd2

HCPL 788j

v(t)

0.1uF

16 15 14 13 12 11 10 9

0.1uF

To amplifier

0.1uF

470pF +5V

Figure 7.6

AC GND +5isolated

0

1 2 3 0.1uF 4 5 6 7 8

AC GND

Vin+ Gnd2 VinVdd2 CH Fault CL ABSVAL Vdd1 Vout VLed+ Vref Vdd1 Vdd2 Gnd1 Gnd2

HCPL 788j

0.1uF

16 15 14 13 12 11 10 9

To filter 2.5V

470pF +5V

Current and voltage monitoring circuit

7.4.1 Zero-Crossing Sensing An ultra-fast comparator (T L3116) is used to detect polarity of grid voltage and current waveforms as shown in Figure 7.7. There are two comparators used in the circuit to enable four quadrant inverter operation. The sensing circuitry is isolated from grid. V or I +

-

Figure 7.7

Zero crossing detection

7.5 LOGIC CIRCUITRY A few logic components are added to the SCC to reduce current distortion at zero-crossings and enable 4Q operation. A SR latch is used to set the constant switching frequency and reset the integrator. A circuit to avoid the zero-crossing distortion is explained in Chapter 5. A combination of logic AN D, OR and N AN D gates are implemented in the circuit to implement switching strategy. The logic circuit is given in Appendix E.1. Boolean equations for the logic implementation are mentioned in Chapter 4. Figure 7.8 shows a switching sequence for Q1 , Q2 , Q3 and Q4 .

7.6 IGBT GATE DRIVE CIRCUITRY Gate drive circuitry is used to perform a high quality IGBT switching. A number of gate drive circuits can be used. For example, pulse transformer, charge pump, floating gate driver supply and bootstrap circuits are popular. A high and low side driver IR2112 is chosen for IGBT switching, which has 600V floating channel. It operates on the bootstrap principle, which is popular in switching applications for frequency ranges in tens of Hertz to few hundreds of kHz. The gate drive voltage ranges from 10V to 20V and the chip is compatible with 3.3V logic input. The switching frequency is 5kHz. Duty cycle will vary from 0 to nearly 100%. The gate driver must be able to provide enough power at the gate of IGBT to turn it on properly. Gate capacitance Energy, (W) =

1 2

× ∆Qg × ∆Vge = 0.5 × 142nC × 8V = 0.568µJoule

The required output power from the driver = W × fsw = 0.568µJoule × 5kHz = 2.84mW att

60

CHAPTER 7


1 Q1 0 1 Q2 0 1 Q3 0 1 Q4 0 0.06

0.062

Figure 7.8

0.064

0.066

0.068

0.072 0.07 Time (sec)

0.074

0.076

0.078

IGBT switching logic sequence for Q1 , Q2 , Q3 and Q4 at reactive current injection

The major task in designing the driver is the selection of the bootstrap capacitor value. The input voltage level is 5V . The logic voltage level at input and output of the driver IR2112 are shown in Figure 7.9.

Logic 1

{

15V

5V Logic 1 3.7V

9.5V uncertain

uncertain 1.8V

Logic 0

{

Logic 0

0V Input logic voltage level Figure 7.9

{

{

6V

0V Output logic voltage level

IGBT driver IR2112 logic voltage level

The minimum bootstrap capacitor value can be calculated from the following equation taken from IR application note [40]. C≥

2[2Qg +

Iqbs (max) f

+ QLs +

ILbs (Leak) ] f

Vcc − Vf − VLs − Vmin

Where Gate charge of high side IGBT (Qg ) = 142nC Maximum VBS quiescent current (Iqbs (max)) = 230µA Level shift charged required per cycle (QLS ) = 5nC (typical value)

(7.1)

7.7

61

POWER CIRCUIT

Bootstrap capacitor leakage current (Icbs (Leak)) can be neglected for ceramic capacitor. Logic section voltage source (Vcc ) = 15V Forward voltage drop across bootstrap diode (Vf ) = 1.0V Minimum voltage between VB and VS (Vmin ) = 0V Using Equation 7.1, the capacitor value found to be greater than 0.047µF. As shown in Figure 7.10, the bootstrap capacitor (CBS) is the only source to turn on and Rbs

Vdc

Dbs

Q1 D1

Q2 D2

Figure 7.10

IGBT driver circuit diagram

of f of Q1 . When Q2 is on, the lower pin of the CBS is connected to the ground potential and charges from 15V supply through a diode in series. When the Q2 is of f , the capacitor current can not flow through the reverse bias diode. This floating charged voltage will be applied at the gate of the high side switch. The high side channel of the drive is connected to the high side of inverter where voltage swings between two rails. The voltage at Q1 varies from Vdc (400V ) to ground potential, so the gate voltage should be 415V to turn on. Thus, output side terminal of the driver is isolated from the input terminals. The minimum required capacitor value is calculated from the Equation 7.1, and its time constant should be one tenth or less than the switching period. Q1 gate pulse has variable duty cycle. During higher duty cycle the CBS charges for small period, when output current is flowing through D2 during Q1 , Q2 of f . Hence, the capacitor should store enough energy to turn it on for long discharging period. Finally, the CBS value is chosen at 1µF in parallel with a small decoupling capacitor 0.01µF . Both capacitors are ceramic multi-layers. Special care is required while selecting bootstrap diode, which is connected in series with a small resistance and the CBS. The diode should be able to block high rail voltage, which is 400V and should be fast recovery to minimize the charge flowing back to the Vcc from the CBS. The resistor is used to limit the transient current during switchings, but maintain a short capacitor charging time constant. Another low equivalent series resistance (ESR) ceramic capacitor is used on the low side channel from Vcc to COM (ground). As this capacitor supports both output buffer and bootstrap recharge, it is chosen 10 times bigger than the bootstrap capacitor which is 10µF [40].

7.7 POWER CIRCUIT The power circuit board is vulnerable to overvoltage due to the high frequency switching of high voltage and current. The single phase full bridge inverter is built using n-type IGBT

62

CHAPTER 7


(T 0 − 247) package. Careful PCB layout is important to reduce parasitic bus inductance and stray inductance between the high side and low side of the switching devices.

7.7.1 Parasitic Bus Inductance The parasitic bus inductance appears due to a separation between bus plate and connections. The inductance causes high transient voltage during IGBT switching. The snubber circuit across IGBT is used to protect from the transients as shown in Figure 7.11. When Q1 is of f , parasitic bus inductance causes a transient voltage across Q1 . The snubber diode is forward biased and diverts the transient energy into the snubber capacitor. The capacitor voltage discharges through the snubber resistance and releases stored energy when Q1 turns on. During turn on the snubber capacitor discharges through snubber resistance whose time constant is smaller than on state of the IGBT and the resistance is selected to limit the high discharging current. The snubbers are primarily useful to: 1. Limit switch di/dt or dv/dt. 2. Shape the load line to keep it within safe operating area. 3. Reduce total switching losses. 4. Transfer power dissipation from the switching device to resistor. Parasitic series inductance L

Q1 Cs=27pF

Figure 7.11

Snubber

Rs=220Ω

Snubber across IGBT

The H-bridge is constructed on 1mm thick board with 2 ounce thickness of copper on double sided PCB. The negative voltage rail is constructed underneath the positive voltage rail of the PCB as shown in Figure 7.12. The cross sectional area of the positive bus is similar to the negative bus. A high voltage electrolytic capacitor is connected across the positive and negative bus as close as possible to avoid the lead-inductance due to the capacitor connection. Usually some low ESR ceramic capacitors are added. The parasitic inductance due to the bus connection and snubber capacitors for peak 10A fundamental current are calculated as follows. Length of flux path (l) = 90mm Distance between positive and negative bus (d) = 1mm Wide of the bus (b) = 30mm Surface area of flux path (A) = 30mm2

7.7

63

POWER CIRCUIT

= 90m m

Positive Bus

Flux p

a th l

i

30mm 1mm A

Negative Bus Figure 7.12

DC bus connection at PCB

Assuming free space in between two bus, Permeability (µ) = 4π × 10−7 N/A2 Reluctance of the bus can be approximated by, < =

l µ×A

= 2387.32M ( Amp−turns ) W eber

Hence, the parasitic inductance can be calculated by, Inductance (L) =

N2

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