Micro-DVR – A Development Platform for DVR and FACDS W. Komatsu, Member, IEEE, A. R. Giaretta, M. A. Oliveira, T. C. Monteiro, M. Galassi, S. U. Ahn, L. Matakas Jr., E. Bormio Jr., J. Camargo, J. A. Jardini, Fellow, IEEE
Abstract—This work presents a development platform with reduced power for DVR and FACDS applications and development. The proposed equipment allows testing control algorithms, hardware behavior as well as the strategy applied in the development of the power circuitry. The DVR (Dynamic Voltage Restorer) is one way to mitigate Voltage Sags and Voltage Swells, which are a common cause of damage for the industry, because of the growing number of equipment sensitive to the quality of the delivered electrical energy. The same equipment can be operated as a FACDS (Flexible Alternating Current Distribution Systems) allowing series compensation of distribution lines, as well as power flow control between parallel feeders, as well as an UPFC (Unified Power Flow Controller). This paper emphasizes the implementation of a DVR topology and its results. Index Terms—PWM Converter, Dynamic Voltage Restorer, FACDS, Voltage Sags, Voltage Swells.
I. NOMENCLATURE DVR – Dynamic Voltage Restorer FACDS – Flexible Alternating Current Distribution Systems UPFC – Unified Power Flow Controller PWM - Pulse Width Modulation IPE – Individual Protection Equipment PLL – Phase Locked Loop DC – Continuous Current AC – Alternating Current LC – Inductor-capacitor (filter) PI – Proportional-Integral (controller) LPF – Low Pass Filter
T
II. INTRODUCTION
his paper presents a platform for DVR and FACDS development which allows testing control algorithms, hardware behavior and validation of dimensioning strategies of the circuits without the inconveniences of the dangerous voltage and current levels. This work was supported by Companhia Paulista de Força e Luz (CPFL Piratininga), within the Research and Development Program of the Agência Nacional de Energia Elétrica – ANEEL (Brazilian Electrical Energy Agency). J. A. Jardini, W. Komatsu, L. Matakas Jr; M. Galassi and A. R. Giaretta are with Escola Politécnica da Universidade de São Paulo (EPUSP), São Paulo, SP 05508-900, BRAZIL (e-mail:
[email protected]). S.U. Ahn and E. Bormio Jr. are with Companhia Paulista de Força e Luz (CPFL Piratininga), Campinas, SP, BRAZIL (e-mail:
[email protected]). J. Camargo, M. A. Oliveira and T. Monteiro are with Expertise Engenharia Ltda, Campinas, SP, BRAZIL (e-mail:
[email protected]).
978-1-4244-1904-3/08/$25.00 ©2008 IEEE
This platform operates with reduced three-phase AC voltage and current levels (31V RMS phase voltages and 3A RMS phase currents). Therefore, there is a decrease in the system size, allowing an easier handling compared with a real scale system. With reduced current and voltage levels, besides the reduction of hazardous working environment conditions, electromagnetic interference generated by platform’s static converters switching is also minimized. Small scale equipment can also drastically reduce development costs. Within a small laboratory with limited AC power capability, tests emulating full scale equipment can be done. Human and material resources can also be saved, as less people must be engaged and basic insulation levels both for measurement equipment and IPEs are reduced. With the size and power reduction, equipment can be easily transported and operated, in order to allow training and qualification about power electronics equipments applied in distribution and transmission systems. As this small scale equipment is effectively built with all features found in full scale ones, the supervision and control boards, as well as all associated control hardware, would be the same found in full scale equipment, allowing easier development and debugging of both software and hardware. Power hardware dimensioning and validating strategies can also be studied, taking into account scale issues. These features can not be reproduced in a digital simulation environment. III. MICRO-DVR TOPOLOGY Simplified single-wire diagram of the Micro-DVR is presented in Fig. 1. The system is connected to the AC mains through two single-phase transformer banks with star-star connection and a delta connected tertiary1. This configuration allows operation in phase with the AC mains as well as galvanic insulation. One transformer bank is connected to the series branch, and the other to the parallel branch. Series branch is implemented with three one-phase full bridge inverters, with three-level switching PWM2, connected to LC (LINV, CINV) output filters, and series connected between insulated AC side and load through three one-phase injection transformers, allowing zero sequence current injection. The
1 Delta connected tertiary avoids output voltage distortion due to the primary side magnetizing current, as the primary and secondary connection is a star-star one. 2 Also known as unipolar PWM switching [1].
Fig. 1. Simplified single-wire diagram of the Micro-DVR.
presence of switchable inductors LFACDS allows the emulation of a transmission or distribution line impedance, concentrated at their ends. RSAG resistor has the same ohmic value of the transformer banks series impedance. Its momentary connection generates a three-phase voltage sag to 50% of the nominal phase value. Parallel branch is composed by the second transformer bank connected to a three-phase PWM rectifier, which absorbs AC sinusoidal currents with high power factor3 and keeps the DC voltage on the bank of capacitors C constant and equal to VDC = 50V. In a load rejection event which generates a momentary AC voltage swell, series branch inverters return the energy back to the capacitors bank, and the PWM rectifier returns the energy to the mains. In the initial energization, with the PWM rectifier still turned off, capacitor bank C charging current is limited temporarily with resistors RRET When VDC reaches a minimum value, the control system short circuit the resistors RRET and turns on the PWM rectifier, as well as the three series inverters. Due to the boost effect of the PWM rectifier operation, in steady state VDC is higher than the peak line voltage value at the secondary of the parallel branch, allowing the PWM rectifier to impose current with positive or negative di/dt values on the LRET inductors. The implemented Micro-DVR can compensate threephase Voltage Sags up to VSag3φ = 0,5pu and Voltage Swells up to VSwell = 1,2pu with maximum duration of ∆t = 300ms. IV. MICRO-DVR CONTROL A. Series branch control Control system for the series branch of the Micro-DVR 3 AC current of this rectifier is PWM modulated and has its harmonic content filtered by inductor LRET [2]
is represented by the reference generation, phase locked loop (PLL) and inverter control blocks, as shown in Fig. 2. Reference generation block gives to the inverter control blocks the reference voltage to be injected by the DVR. The inverter control blocks track the phase reference voltages, in order to assure correct voltage injection per phase. Phase angle and AC voltage frequency, given by the PLL block, are critical to the DVR performance. Some strategies for voltage control and PLL are presented in [6], [7], [8] e [9]. PLL, series voltage reference generation and series inverter voltage control implemented in this platform are presented in following itens 1), 2) and 3).
Fig. 2. Simplified block diagram for power and control of the series branch.
1) Positive sequence PLL [8] A phase detector based on the filtered dot product of the AC phase voltages VA,B,C and synchronizing PLL phase voltages VPLLA,B,C was implemented (Fig. 3). If AC and PLL phase voltages were synchronized with 90 degrees between each other, the mean value of the dot product has null result. In any other situation a PI controller adjusts the PLL
frequency, correcting phase and frequency. From VPLLA,B,C, the voltages VPLL//A, B, C, which are in phase with the AC positive sequence voltages, are generated. This method´s advantage is the generation of a three-phase set of references with the same phase of the fundamental component of the mains positive sequence. Besides, the implemented PLL algorithm is simple and has low processing time and memory requirements, useful features in DSP based control systems implementation.
compensate them. With this approach, voltage harmonic distortions on the load are also compensated in steady state and transitory conditions, because references v+1A(t), v+1B(t) and v+1C(t) have peak value |v+1(t)|. 3) Series inverter control Series inverter control of the Micro-DVR, operating as DVR, can be divided in series voltage control (Fig. 5) and series current control (Fig. 6), independent for each phase. Figures 5 and 6 indicate internal control variables referred to phase A.
Fig. 3. Basic structure of the applied PLL, implemented as a closed loop control system.
2) Reference Generation for sags, swells and voltage harmonics compensation The applied method has as advantage the correction of the positive sequence amplitude during sags and swells events, as well as eliminating voltage harmonics distortion of the load.
Fig. 5. Series voltage control, referred to phase A.
Fig. 6. Series current control, referred to phase A.
Fig. 4. Reference generation for the DVR operation, based on the voltage positive sequence extraction.
In Fig. 4, the instantaneous values generated by the PLL (vPLL//A(t), vPLL//B(t) and vPLL//C(t)), in phase with the mains positive sequence, are multiplied individually with their correspondent measured mains phase voltages vA(t), vB(t) and vC(t). The sum of the three products is low-pass filtered (LPF) and multiplied by a constant (K=2/3), resulting in the mains voltage positive sequence peak value |v+1(t)|. Multiplying this value with vPLL//A(t), vPLL//B(t) and vPLL//C(t), one obtains v+1A(t), v+1B(t) and v+1C(t) (reference load voltage values) and subtracting mains measured voltages, one gets the reference voltages vREFA(t), vREFB(t) and vREFC(t), for each of the three inverters of the series branch of the platform. The |v+1(t)| value is the real peak value of the positive sequence fundamental component, and changes slowly during the day, due to variations on distribution system loading. Therefore, reference generator dynamics must be slow enough to follow only this small variation around nominal mains voltage, but must be kept practically unchanged during sags and swells events, in order to
Both voltage and current control are implemented with PI controllers with anti-windup feature. Especially during transients, or due to internal saturation of the control loops, the integral part of the PI controller can saturate, resulting in performance degradation. This problem, also known as windup, can be prevented with an anti-windup block which restricts integral action during transients. The implemented algorithm changes the LA limit of the integral action dynamically. With a fixed limit (maximum value) for the proportional action, the variable limit of the integral action is given by (1): L A [ k ] = y REFMAX − K P ⋅ e[ k ] (1) B. Parallel branch control Parallel branch control of the Micro-DVR, operating as DVR, is represented by the DC voltage control blocks (Fig. 7) and AC current control, both referred to the PWM rectifier control (Fig. 8).
Fig. 7. Block diagram of the DC voltage control of the parallel branch.
cabinet as seen in Figs. 9 to 11. Digital control was implemented with two Digital Signal Processors (DSP) Analog Devices ADSP-21992, one for the series branch and the other for the parallel one. They operate independently and without communication between them, sharing only the DC voltage measurement. For the power signal measurements, Hall effect current sensors LEM LA25 and voltage sensors LEM LV20 were applied. The static converters were implemented with IGBT transistors IRG4PC50UD (VCES=600V, IC=27A) and gate driver optocouplers Avago HCPL-316J. The converters operate with switching frequency fSwitch=10kHz and the sampling frequency of the DSPs is fSampling=20kHz.
Fig. 8. Block diagram of the AC current control of the parallel branch.
1) DC voltage control DC voltage control block is implemented with a PI controller with anti-windup (described before) and keeps DC voltage within a pre-determined value VDCREF. The expression of the PI controller, discretized from s plane to z plane by bilinear transform, is given by (2): I PAR [ k ] = K P ⋅ e[ k ] + ⋅ ⋅ ⋅ (2) T ⋅K ⋅K ⋅ ⋅ ⋅ + A P I ⋅ {(e[ k ] + e [ k − 1 ] ) + y I [ k − 1 ]} 2
Fig. 9. View of the Micro-DVR
where TA is the sampling period, KP is the proportional gain and KI is the integral gain. IPAR is the PI block output, resulting from the error in its input (which is the difference between the reference voltage VDCREF and the measured voltage VDC), and k is the k-th sampling in the discretized system. 2) AC current control The AC current controller, based on a deadbeat algorithm [3], [4], [5], [6], [7], [9]), tracks the reference current in order to assure sinusoidal AC currents in phase with AC voltages at the entrance of the PWM rectifier. For a given phase, the difference between mains phase voltage vA(t), vB(t) or vC(t) and the synthesized voltage vRETA(t), vRETB(t) or vRETC(t) at the PWM rectifier output is over the LRET series inductor, generating an iLRET=iRET current absorbed by the PWM rectifier. The synthesized phase voltage vRET which assures deadbeat response is given by (3): I [ k ] − I REFRET [ k ] ⋅ LRET + ⋅ ⋅ ⋅ v RET [ k + 1 ] = LRET TA (3) ⋅ ⋅ ⋅ +2v MAINS [ k ] − v RET [ k ]
Fig. 10. Front view of the Micro-DVR
V. HARDWARE DESCRIPTION The Micro-DVR was assembled in a standard industrial
Fig. 11. Side view of the Micro-DVR
The values of the components shown in Fig. 1 are described in Table 1. TABLE 1 MICRO-DVR´S COMPONENTS VALUES
LFACDS LINV LRET CINV CLINK RRET RSAG Injection Transformer Series Branch Transformer Parallel Branch Transformer
10mH 1.7mH 0.8mH 15µF 94mF 8.2Ω 0.47Ω Primary: 31V / 150VA Secondary: 31V / 150VA Primary: 127V / 240VA Secondary: 31V / 150VA Tertiary: 12V / 90VA Primary: 127V / 180VA Secondary: 18V / 120VA Tertiary: 12V / 60VA
adopted design criterion, and its behavior does not present overshoot. Positive sequence reference can not change considerably during the short term sag or swell event. For the MicroDVR design the maximum duration for a sag/swell event was defined as t SAG _ max = 0.3 s , and the low-pass filter (LPF) of the reference generator (Fig. 4) must have a settling time tsettling higher than tSAG_max. It assures that during the disturbance the positive sequence is kept practically constant, and the Micro-DVR can restore load voltages to the levels before the disturbance. In the simulation and implementation the settling time is about t settling = 5 s .
VI. SIMULATIONS The PLL algorithm from Fig. 3 was simulated with the Matlab software for mains frequency of fMAINS=60Hz, three-phase sag to 50% of the fundamental and presence of 5th harmonics (20%). The results are on Fig. 12, showing synchronization due to the presence of the three positive sequence voltages VPLL//. The PI controller (controller GC(s) rad on Fig. 3) was adjusted with k I = 0.04 2 2 V s rad and k P = 0.28 2 . Maximum variation of the angular V s rad frequency is ∆ω = 4π . Sampling frequency for this s simulation is fSampling = 20kHz.
Fig. 13. Simulation of the voltage reference behavior (red) during a threephase sag (blue). Waveforms referred to phase A.
For the parallel branch (PWM rectifier), the PI controller of the DC link voltage was adjusted for a settling time of t settling = 1s and 5% maximum error compared to the reference voltage. With these settings, after a load step of 50% of the nominal power one can verify the performance of the controller in Fig. 14.
Fig. 12. PLL simulation. Distorted phase voltages (green, cian, yellow) and synchronized VPLL// voltages (blue, red, purple) are shown.
Reference generator of Fig. 4 was simulated with PSIMCAD software (Fig. 13). A RMS voltage (of phase A) V A _ rms = 31V (1 pu) without harmonics was simulated, as well as the PLL generated voltage reference (also for phase A) with initial value of V Aref _ rms = 31V (1 pu). A threephase sag to 65% and duration t SAG = 0.5 s was applied. It can be seen in Fig. 13 that the voltage reference is kept above 95% of the initial value (nominal), following the
Figura 14. Simulation of the DC voltage control action for a load step.
VII. EXPERIMENTAL RESULTS Performance measurements for DVR operation were made, with voltage harmonics compensation (Fig. 15) and three-phase voltage sags to 65% with resistive (Fig. 16)
and resistive-inductive (Fig. 17) loads.
the inconvenience of the high voltages and currents operation. It reduces the risk of electrical accidents, reduces electromagnetic interference, and allows installation in laboratories with reduced available power. The equipment portability hints for the use of this equipment in personnel training on the application of power electronics devices applied in distribution systems. Computer simulations and experimental results were presented in order to validate the project and implementation criteria. IX. ACKNOWLEDGEMENTS
Fig. 15. Voltage harmonics compensation (phase A) on the load.
The authors gratefully acknowledge the contributions of M. Masuda, F.A.T. Silva, F.O. Martinz, S. Copeliovitch, W. Borges, E.R. Zanetti and E. Lima in the development of the research and development project which originated this work. X. REFERENCES [1] [2] [3]
[4] Fig. 16. Three-phase sag to 50% compensation (showing only phases A and B) with resistive load R=22Ω. [5]
[6]
[7]
[8]
Fig. 17. Three-phase sag to 50% compensation (showing only phases A and B) with resistive-inductive load R=22Ω, L=10mH.
VIII. CONCLUSIONS This work presented a development platform for DVR and FACDS with reduced voltage and currents, which allows testing control algorithms, hardware behavior, as well as validating circuits dimensioning strategies, without
[9]
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XI. BIOGRAPHIES José Antonio Jardini (LF’1990), was born in March 27, 1941. He was graduated from EPUSP - Polytechnic School at São Paulo University, in 1963. He obtained his M.Sc. degree in 1970 and PhD in 1973. He became Associate Professor in 1991 and Professor in 1999. He worked at Themag Engineering Ltd. in the area of power systems studies – transmission line projects and automation. At present he is a professor at the Department of Energy and Electric Automation Engineering where he teaches “Generation Automation” and “Transmission and Distribution of Power”. He has represented Brazil at the SC38 group of CIGRE, CIGRE member, Life Fellow of IEEE and Distinguished Lecturer of the IAS/IEEE. Se Un Ahn, was born in Inchon, South Korea, in 1957. He was graduated from Escola de Engenharia Mackenzie (São Paulo) in 1981. He obtained his M.Sc. and Ph.D. degrees at the EPUSP - Escola Politécnica da Universidade de São Paulo in 1993 and 1997 respectively. He works since 1986 as research engineer of distribution systems at CPFL Piratininga Company, and formely at Eletropaulo and Bandeirante, all electrical utility companies. His professional activities also include the use of load curves and planning of the expansion of the electrical system. Lourenço Matakas Jr, was born in São Paulo, Brazil, in September 27, 1960. He was graduated from EPUSP - Polytechnic School at Sao Paulo University, in 1983 and obtained his M.Sc. degree in 1989 and PhD in 1998 also from EPUSP. He worked from 1984 to 1989 at FDTE/EPUSP developing projects related to electrical vehicles, electronics ballasts, induction furnaces and high power factor rectifiers. At the University Of Tokyo, Japan, he was in the Ph.D program from 1990 to 1992, and was hired as assistant professor from 1993 to 1995, researching on static converters association. Since 1996 he is assistant professor at EPUSP, Pontifical Catholic University of São Paulo (PUC-SP) and Universidade São Judas, teaching disciplines related to power electronics, electronics and industrial automation. His research areas are electrical energy quality, static converters control and modeling as well as their application to electrical power systems. Wilson Komatsu (M’1989), was born in São Paulo, Brasil, in 1963. He graduated from EPUSP - Polytechnic School at São Paulo University, in 1986, He obtained his M.Sc. and Ph.D. degrees the EPUSP in 1992 e 2000 respectively. He worked from 1987 to 1989 at FDTE/EPUSP developing induction furnaces project. Since 1989 he teaches at EPUSP subjects related to power electronics and control. His research areas are electrical power quality, control and modeling of static converters and their application to electrical power systems. Edison Bormio Jr. was born in Bauru, São Paulo State, Brazil, in 1965. He was graduated from the Escola Federal de Engenharia de Itajubá (EFEI-MG) in 1990 as Electrical Engineer. He works since 1992 as distribution systems planning engineer at CPFL Paulista, na electrical utility company. His professional activities also include the use of load curves.
Josué de Camargo, was born in São Paulo, Brazil, in April 28, 1958. He was graduated in Electrical Engineering from the Universidade Estadual de Campinas (UNICAMP). He worked for 18 years at the CPFL - Companhia Paulista de Força e Luz, and has several papers on voltage regulation and reactive control área, especially involving series reactive compensation. Nowadays he is director of Expertise Engenharia, working in the research areas of electrical energy distribution and electrical energy quality. Antonio Ricardo Giaretta was born in Jundiaí, São Paulo, in 1980. He was graduated in Electrical Engineering in 2005 from the EPUSP Escola Politécnica da Universidade de São Paulo with emphasis on Electronic Systems. He works as research engineer of the LEP – Power Electronics Laboratory of EPUSP, where he is also M.Sc. student. His research area is power electronics applications on electrical power distribution systems. Maurício Galassi, was born in São Paulo, Brazil, in August 22, 1978. He was graduated from the Electrical Energy and Automation course of EPUSP - Escola Politécnica da Universidade de São Paulo, in 2002, and obtained his M.Sc. also from EPUSP in 2006. He is now Ph.D. student at EPUSP and is research engineer of the LEP – Power Electronics Laboratory of EPUSP. Thiago Costa Monteiro, was born in Rio Claro, Brazil, in 1983. He was graduated in Electrical Engineering from the Universidade Estadual de Campinas (UNICAMP) in 2005, with emphasis in Electrical Energy Systems. His experience in electrical engineering includes Energy Distribution, Electrical Measuring Systems, Control and Correction of Electrical Disturbances related to Electrical Energy Quality. He worked for one year at the electrical utility CPFL in the Distribution System Expansion Planning Area. Nowadays he works in Research and Development projects related to Dynamic Voltage Restorers (DVRs) and Flexible AC Transmission Systems (FACTS) at Expertise Engenharia. Marco Antônio de Oliveira was born in November 16, 1967, in Jacareí, Brazil and was graduated in Electrical Engineering from the Pontifical Catholic University of São Paulo (PUCSP) in 2003. Nowadays he works on Research and Development projects at Expertise Engenharia.
