composed of a Gilbert-Cell based up-conversion Tx mixer, an active band-pass filter and a high-gain Driver. Amplifier. A low-size LC-tuned MOS-VCO with a ...
A Fully Integrated SiGe BiCMOS MMIC Frontend for Using in the ISM Bands F. Eshghabadi*, M. Yazdizadeh*, R. Shabanpour*, M. Dousti**,***, F. Temcamani****, B. Delacressoniere**** and J. L. Gautier **** **
* Department of Electrical and Electronics Engineering, Azad University (IAU) of Arak, Arak, Iran Department of Electronics Engineering, Azad University (IAU), Science & Research Campus, Tehran, Iran *** Department of Computer and Electronics, Power and Water University of Technology, Tehran, Iran **** ENSEA, ECIME research group, 95014 Cergy-Pontoise Cedex, France
Abstract— A fully monolithic radio transceiver front-end for wireless applications in a 2.4 to 2.5 GHz band is presented in a 0.35 µm SiGe BiCMOS technology. This high performance transceiver contains a receive (Rx) chain with a two-stage cascode low noise amplifier, an active transversal band-pass filter and an active downconversion Rx mixer, and a transmit (Tx) chain composed of a Gilbert-Cell based up-conversion Tx mixer, an active band-pass filter and a high-gain Driver Amplifier. A low-size LC-tuned MOS-VCO with a phase noise of -130.3 dBc for 1 MHz offset from center frequency was integrated to drive the mixers. The high linear receiver exhibited a gain of +27 dB and an excellent noise figure (NF) of 3 dB, while the transmit string has a gain of 29.4 dB and an output-referred thirdorder intercept point (OIP3) of +17.5 dBm. The overall receiver and transmitter consumption is about 170 mW and 180 mW for a 3.3V DC supply, respectively.
I. INTRODUCTION Nowadays, the emerging interests on high data rate wireless transmission with the target application of portable devices such as WLAN, Bluetooth, RFIDs and etc., have increased the demand on low-power and low cost wireless devices with high performance. This motivates the design efforts for low-power implementations in the low-cost silicon technologies. There are many technologies suitable for a 2.4 GHz transceiver system. By contrast, silicon-based technologies are cheaper and lend themselves to high integration. SiGe BiCMOS technology offers very fast heterojunction bipolar transistors (HBTs) and it is compatible with CMOS process. As a result, the highest integration level can be achieved. This work presents RF front-end receivers and transmitters for 2.4 GHz frequency ISM band designed and optimized using 0.35 µm SiGe BiCMOS HBT of which cutoff frequency is 40 GHz. The front-end contains a receiver and a transmitter chain. The receiver path consists of a low noise amplifier (LNA) which reduces the overall noise figure (NF), an active transversal filter which acts as an image rejection filter, and a Receive (Rx) mixer. In the transmitter path, a Transmit (Tx) mixer which acts as an up-conversion mixer, an active band pass filter which acts as an image rejection filter, and a driver
Fig. 1
Block diagram of 2.4GHz Front-end system
amplifier which boosts the output signal is presented. A low-size LC-tuned mosfet voltage controlled oscillator (MOSVCO) with high enough output power is integrated to drive both Rx and Tx mixers. The building blocks have been optimized and developed to be nonsensitive to 5 percents of variations in fabrication and bias voltages, and preserve its own specified parameters such as matching. All the matching components and DC blocks were on-chip excluding the balun inductors in Rx mixer. II. THE RF FRONT-END: DESIGN AND PERFORMANCE The front-end building blocks are a high-linear LNA, an active band-pass filter (BPF) and a down-conversion mixer in the receive (Rx) path, and an up-conversion mixer, an active BPF and a high-gain Driver Amplifier (DA) in the transmit (Tx) path (Fig. 1). Also an integrated tunable MOSVCO is developed to drive the mixers’ switches. The transceiver is completed with an external power amplifier (PA). The front-end is based on a 340MHz IF architecture on the basis of analysis of the spurious response and half IF problem. If the IF is too low, the image frequency is too close to the receiver band and too high a selectivity is required in the image rejection filter. If the IF is too high, the number of spurious responses that arise from the frequencies falling within the RF passband increases dramatically [1]. A 0.35 µm SiGe BiCMOS technology was used for these designs. The actives include high-speed HBTs and the passives benefit of high-Q inductors. The front-end was developed to have the highest performance in the 2.4 GHz ISM frequency band.
A. LNA The LNA features a two-stage cascode topology with a resistive shunt feedback (Fig. 2). The cascode topology has the inherent advantage of separating the output and input optimization criteria in the LNA circuit. Also, two important features of avoiding Miller capacitor effect and achieving higher reverse isolation are realized. S12 is important to keep the LO-to-RF leakage to a minimum [2]. This topology is sufficient for a gain in excess of 16.7 dB in the entire band. The 1-dB bandwidth is about 1.5 GHz. The input matching is optimized to compromise input reflection (S11) and noise figure (NF). For the used transistors, the optimum noise figure matching point is very close to the conjugate-matching point, so that S11 and NF can be optimized simultaneously. The most effective way of improving the NF is increasing emitter size of Q1 [3] where using NPN254 transistors with large enough area gave a NF of 1.70dB. Use of inductive degeneration (Le) at the emitter leads to a wideband match at the input. The inductor L1 is used for biasing and loading, and also forms the output matching with R1 and the coupling capacitor Cout to 50Ω impedance. The additional resistive shunt feedback circuit helps further match the gain and noise optimum points. The feedback resistance Rf does not increase the NF if it has high value over 1kΩ [4]. The emitter size of Q1 and Q2 was optimized to acquire high IIP3 (equal to +3.2dBm) and high level of output matching. The input and output return losses are below -15dB and -25dB, respectively. The LNA draws 12.4mA DC current from a 3.3V DC supply.
Fig. 2
LNA schematic
B. Active Rx Band-Pass Filter High frequency MMIC transversal filters usually have, as a major limitation, the need of large resonant elements and high gain amplifier(s). In addition, we know that implementation of microwave filters with distributed elements that could be quite large, or with discrete lumped elements which is expensive, MMIC filters would offer the possibility of both small size and low cost [5][6]. The filter structure of reported in this paper is shown in Fig. 3. It utilizes a variable transversal element to obtain the filtering response by a combination of the transversal technique and tuned amplifier in the main signal path. In addition, in the customary transversal filter structure, the number of complex conjugate pole pairs is always even, while this number becomes odd in the new filter due to the contribution of the tuned amplifier with only one pair of complex conjugate poles [7]. The proposed bipolar tuned amplifier to be used in the new filter should be equivalent to a circuit with a 50Ω
Fig. 3
Active band-pass filter
termination in both sides in order to meet the requirements of the transversal elements. The basic structure of this filter is a conventional lowpass filter that is used on the input. This is followed by a conventional high-pass filter. The characteristic of this filter is that of a conventional lumped element band-pass filter. Then, in continue, two transversal elements are added that one of them was tuned. A design example of band-pass filter that centered @2.45-GHz with 1-dB pass-band ripple, and better than 30-dB rejection @1GHz apart from pass-band edge were developed. Frequency tuning is prepared in terms of 0.35μm SiGe BiCMOS cold MOSFET for capacitors. The active filter mainly composed of one tuned bipolar amplifier and a fixed gain BIPOLAR amplifier. The amplifiers are common-Emitter. The emitter size of Q2 was one less quarter than of that of Q1. The most effective way of improving the gain and NF is increasing emitter size of Q1 and Q2 where NPN254 transistors were used. The circuit draws 28mA DC current from a 3.3V DC supply. The overall consumption power is about 92mW. The 1dB gain compression occurs at -14 dBm for input power. The IIP3 of filter were achieved +6dBm. The filter exhibited a gain of over 6 dB and a noise figure of 12 dB. However the gain of the LNA is high enough for the noise figure of the active Rx filter not to be a critical parameter. The input and output return losses are less than -15 dB from 1.3 GHz to 2.5 GHz and less than -10 dB from 2.38 GHz to 2.63 GHz, respectively. The quality and stability factors were achieved 97 and 14.5, respectively. C. Active Rx Mixer Half of a Gilbert cell is used as the mixer core for Rx mixer topology (Fig. 4). This topology has a single-ended RF input and differential IF outputs that are converted to single-ended operation with a balun circuit (external L1 and L2, and integrated C1) and internal DC blocking capacitor C2. Because of low IF signal frequency, the inductors required could not be realized on-chip. The mixer is separated into two stages: the lower stage represents a common-emitter stage, and the upper part represents the switching stage. The increase of the bias current of Q1 results in the increase of gain and the decrease of NF and also linearity in this single balanced mixer topology. The bias current of Q1 was determined to achieve a tradeoff between these parameters. The input, output and LO ports impedances are all very close to 50Ω.
The RF and LO frequency were swept simultaneously, so that the IF frequency is fixed at 340 GHz. The 1-dB bandwidth was about 1 GHz. The Rx mixer exhibited a conversion gain of +7.2 dB. The resistors of R1 and R2 were chosen equal to 25Ω to realize a tradeoff between linearity and conversion gain. The single balanced mixer has an input-referred third-order intercept point (IIP3) of 9 dBm and a simulated NF of 10.5 dB. The area of transistors Q2 and Q3 was determined a half of that for Q1 to compromise between gain, linearity and LO power(10dBm). The potential advantage of using a micromixer is its low power consumption, where the Rx mixer consumes only 0.97mA at 3.3V DC supply. This active mixer resulted a very low LO to RF coupling that avoids from interfering. The receiver mixer has inductive degeneration (Le) to ground provided by on-chip 1-nH spiral inductors. The degeneration helps achieve the linearity requirements while maintaining lower noise figures in the receiver.
Fig. 5
Tx mixer schematic
and -1.4 dBm, respectively. The Tx mixer consumes 24.4 mA current at 3.3V DC supply. E.
Active Tx Band-Pass Filter The structure and performance of this filter is exactly the same with the one described in section B. This filter acts as an image rejection filter which is followed by DA.
Fig. 4
Rx Mixer schematic
D. Active Tx Mixer The transmitter mixer is a Gilbert-quad-based downconversion design with inductive degeneration on the input differential pair provided by on-chip 0.5-nH spiral inductors, where this topology was chosen to achieve both high linearity and low LO leakage (Fig. 5). The operating frequency of the degeneration inductors should be less than (a) the self-resonating frequency (SRF) of the inductors (Le1 and Le2), (b) the resonating frequency of the network formed by the degeneration inductor (Le1) and the base-to-emitter capacitance of the bipolar transistor (Q1) at the input stage. The degeneration improves overload performance and input matching with only small degradation in mixer noise figure. Q1 and Q2 play a role of balun, and Q3 and Q4 were employed to improve isolation between LO port and IF port. Since the desired output signal of the transmit mixer is at 2.45GHz, on-chip spiral inductors can form LC tuned loads at the quad output to select the 2.45GHz component and attenuate all other outputs. The on-chip load resistors (R3, R4) were used for impedance matching to 50Ω. Doublebalanced configuration we are taking advantage of in this design reach good enough a linearity behavior. In addition, due to the balanced topology of the four quadrant mixer, this circuit performs high port-to-port isolation, and so reduces feedthrough phenomena. The Tx mixer exhibited an up-conversion gain and IIP3 of -0.4 dB
F. Driver Amplifier The design benefits a two stage cascade topology which the design employed for the LNA is also used for the first stage (Fig. 6). The Driver Amplifier exhibited a gain of over +31.3 dB and an OIP3 of +25.1 dBm and a NF of 1.8 dB. DA boosts the output signal from upconversion mixer to a level suitable for an external power amplifier. The second stage at cascade topology was employed to acquire high voltage swings and to improve the linearity and to achieve extended gain. A DC blocking capacitor and a resistor forms the interstage matching. The emitter size of Q3 was one and half of that of Q1, and it was optimized to acquire high gain and high IP3. Onchip decoupling capacitors (Cb1 and Cb2) were employed at each Vcc terminal to prevent oscillation from occurring due to high gain of the amplifier. The DC blocking capacitor C2 with the resistor R2 and also the DC feed inductor L2 forms the output matching to 50Ω impedance. The input and output return losses are less than -19 dB and -25 dB, respectively. The 1-dB bandwidth was about 1.4 GHz.
Fig. 6
Driver Amplifier schematic
Node Compression Curves
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G. Voltage Controlled Oscillator The simple cross-coupled amplifier topology for VCO has severally candidates as shown in [8] in this case. In this project, CMOS topology (Fig. 7(a)) was focused in this work, because other topology in [8] had high current consumption. In this section, we analyze the maximum attainable frequency of oscillation of a typical LC VCO which uses the cross-coupled negative resistance cell. Fig. 7(b) shows a simplified circuit model for a parallel LC oscillator in steady state, where the resistance RP represents the tank loss, REq is the effective negative resistance generated by the active devices, and CEq is the effective shunt capacitance contributed by the active devices in the negative resistance cell. For stable oscillation, the magnitude of the effective negative resistance |REq| has to be smaller than RP . Additionally, for high-frequency operation where CVar is small, the effective capacitance CEq becomes comparable to CVar and significantly limits the maximum attainable oscillation frequency and tuning range[9]. The design goal is achieving to lowest phase noise with 2 GHz oscillation frequency as compared to the other topologies. We used the oscillation frequency, phase noise, and transconductance of integrated LC-tuned VCO equations in [8].For BJT-VCO case, the inductance has to been designed three terminals inductor or two inductors. In this work, two inductors were chosen. For MOS-VCO case, 250μm square inductors with 13.3 nH and diode varactors with 511 fF capacitance were used. The manufacturing process was 0.35-μm SiGe-BiCMOS process with 28 GHz FT NMOS, 15 GHz FT PMOS transistors and 0.35 μm gate lengths CMOSFET .The quality factor (Q) of spiral inductor was around 6.7 at 2 GHz. Varactor diode was consisted with parallel connection of p+ bipolar n-Well diode. The MOS-VCO operates from 1.8 GHz to 2.3GHz with 0V to 3V control voltage. The measured phase noise at 1-MHz offset is 130.320 dBc/Hz @2GHz oscillation frequency and
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Input RF power (dBm) Receiver chain: front-end output IF power versus input RF power
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Receiver chain: Front-end system Gain Compression
output power was -6.658dBm in 2GHz oscillation frequency. The current consumption of CMOS VCO was 636 µA for 2 GHz VCO. III. SIMULATION RESULTS As illustrated in Fig. 8 and 9, the front-end Rx chain achieves a gain of about +27dB and P1dB equal to -43 dBm for input RF power. The receive chain S11 and S21 graphs are shown in Fig. 10, whereas the input impedance matching is close to 50Ω for the entire desired band. The center frequency is at 2.45GHz with the 3-dB bandwidth of 200 MHz. the front-end receiver string exhibited a high gain, an excellent noise figure and proper OIP3 of +26.8 dB, 3 dB, and -8 dBm, respectively. The overall receiver consumption is only 170mW for a 3.3V DC supply. The front-end transmitter presented a gain of about +29.4 dB. The Tx chain OIP3 was over +17.5 at 2.45GHz output RF frequency (Fig. 11). The input and output return losses are achieved below -28 dBm and -19 dBm, respectively. The transmitter consumes a 180mW DC power in a 3.3 volt DC supply. IV. CONCLUSION The 2.4GHz MMIC front-end receiver and transmitter building blocks reported on this paper was realized within a 40GHz SiGe BiCMOS Technology. Also an integrated MOSVCO is developed to cover the entire frequency band of interest with a low current consumption behavior and
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low size of integration. The simulations resulted a good performance of the front-end system such as very low total noise figure (equal to 3dB) of the receive chain and high gain of transmit string. In addition, a low overall power consumption of about 350mW was achieved for the whole system which reaches the requirements for the mobile wireless applications.
REFERENCES [1] [2]
Receiver Chain: Front-end system S-parameters
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Input IF power (dBm) @340MHz Transmitter chain: front-end input-referred thirdorder intercept point (IIP3) versus input IF power
[8]
[9]
Less Besser and Rowan Gilmore, “Practical RF Circuit Design for Modern Wireless Systems” , vol. 1, Artech House, Inc., 2003. J. Laskar, B. Matinpour, and S.Chakraborty, “Modern Receiver Front-ends” , John Wiley & Sons, Inc., 2004. Nam Jin Song, Dohyong Kim, and Jinwook Bum, in "5 GHz SiGe Front-end Components for WLAN Applications", 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits(AP-ASIC2004)I Aug. 4-5,2004, pp. 362-365. B. K. KO et al., “A New Simultaneous Noise and Input Power Matching Technique for Monolithic LNA’s Using Cascode Feedback” IEEE Trans. Microwave Theory Tech., vol. MTT-45 pp. 1627-1630, Sep. 1997. M.J. Schindler, Y. Tajima, “A Novel MMIC Active Filter with Lumped and Transversal Elements” Microwave and MillimeterWave Monolithic Circuits Symposium, IEEE, 1989. Christen Rauscher, “A New Class of Microwave Active Filters”, MTT-S Digest, IEEE, 1994. Kam Weng Tam, Pedro Vitor, and Rui P. Martins, “MMIC Active Filter with Tuned Transversal Element”, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 45, NO. 5, IEEE, 1997. Nobuyuki Itoh, Shin-ichiro Ishizuka, and Kazuhiro Katoh, “Integrated LC-tuned VCO in BiCMOS process”, Toshiba Corporation, Semiconductor Company 580-1. Byunghoo Jung, Student Member, IEEE, and Ramesh Harjani, Senior Member, IEEE, “High-Frequency LC VCO Design Using Capacitive Degeneration”, DECEMBER 2004.
