A Gap Reduction and Manufacturing Technique for ... - Semantic Scholar

JOURNAL OF MICROELECTROMECHANICAL SYSTEMS, VOL. 15, NO. 5, OCTOBER 2006

1139

A Gap Reduction and Manufacturing Technique for Thick Oxide Mask Layers With Multiple-Size Sub-m Openings Reza Abdolvand, Student Member, IEEE, and Farrokh Ayazi, Senior Member, IEEE

Abstract—This paper introduces a technique for the fabrication of thick oxide hard masks on top of a substrate with adjustable opening sizes in the sub- m regime, while the only lithography step involved has m-scale resolution. This thick oxide mask layer with sub- m openings is suitable for etching deep narrow trenches in silicon using deep reactive ion etching (DRIE) tools. Openings of less than 100 nm are realized in a 1.5- m-thick oxide layer, while the original lithographically defined feature sizes are larger than 1 m in width. This method, combined with modified high aspect ratio DRIE recipes, shows a great potential for single-mask batch-fabrication of high frequency low-impedance single crystalline resonators on silicon-on-insulator (SOI) substrates. Dry-etched trenches with aspect ratios as high as 60:1 are fabricated in silicon using the gap reduction technique to realize 200 nm opening sizes in an oxide mask layer. Various resonator structures with sub- m capacitive gaps are also fabricated on a SOI substrate using a single-mask process. Measurement results from high-frequency and high-quality factor (Q) all single crystal silicon resonators are presented. [1684] Index Terms—Deep reactive ion etching (DRIE), gap reduction, high aspect ration trench, sub- m gap.

I. INTRODUCTION N capacitively-transduced microelectromechanical systems (MEMS) devices, reducing the gap size is essential for increasing the capacitive electromechanical coupling. Higher coupling results in higher signal to noise ratio in sensors [1] and lower equivalent motional impedance in electromechanical resonators [2]. Most of the previously reported processes for creating narrow gaps are multimask fabrication sequences involving multiple deposition/etching steps. In these processes, gaps are usually defined by the thickness of a sacrificial layer [2], [3]. Dry etching the sub- m gap is an alternative approach for the above mentioned processes that has not received much attention so far [4], [5]. Various limitations can be listed to justify the lack of interest in the dry etching of narrow gaps. Limited aspect ratio of the trenches fabricated using deep reactive ion etching (DRIE) techniques is one of the most important restrictions. The other issue is the creation of DRIE masks that demands for state of the art, expensive lithography equipment

I

Manuscript received September 1, 2005; revised December 26, 2005. This work was supported by the DARPA NMASP program. Subject Editor K. Böhringer. The authors are with the School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA 30332 USA (e-mail: rezaa@ece. gatech.edu; [email protected]). Digital Object Identifier 10.1109/JMEMS.2006.879668

to define opening sizes in the deep-sub- m regime. The limited thickness of the masking layer containing deep-sub- m opening sizes also reduces the applicability of dry-etched sub- m gaps. This is because the depth of the etched trench can be restricted by the mask thickness and not the DRIE tool due to the selectivity of the etching process to the masking layer. Although these fundamental problems seem challenging to tackle, the inherent simplicity of the direct etching approach is a strong motivation for pursing the idea. To overcome these limitations, significant improvements in higher aspect ratio DRIE process and cost-effective easy-to-fabricate thick mask formation methods are necessary. The application of a thin sacrificial polysilicon layer deposited on the sidewalls of a trench etched in oxide was the initial effort studied in our group to propose a solution for mask formation [6]. Single crystal silicon beam resonators with dry-etched narrow vertical gaps were successfully implemented through the usage of this method. However, our previous work was a feasibility study, mainly targeted toward demonstration of deep-sub- m trench etching using the Bosch process and could not really simplify the fabrication process flow for arbitrary-shaped devices. It required three masking steps, and trenches would only appear in single-sized adjacent pairs, limiting its applicability. The work presented here is the first single-mask process that effectively enables low-cost implementation of high-performance capacitive micro-electromechanical devices with multiple-size deep-sub- m gaps. Preliminary results were initially introduced in [7].

II. THICK OXIDE MASK FORMATION The selectivity of the DRIE process to the masking layer is of great importance. Most silicon DRIE processes demonstrate higher selectivity to silicon dioxide than to organic materials (photoresist). Also, for low temperature cryogenic RIE processes where organic materials cannot be used as a mask due to the cracking of the film, oxide is a common choice for the masking layer. In order to achieve high aspect ratio structures, the oxide mask with sub- m feature sizes must be thick enough to withstand long DRIE process. In this work, a thick layer of oxide with sub- m features is formed by oxidizing a polysilicon layer with m-sized patterned features. Fig. 1 shows a brief schematic diagram of the process flow. The process begins with the deposition of a thin layer of low-pressure chemical vapor deposited (LPCVD) nitride that

1057-7157/$20.00 © 2006 IEEE

1140


Fig. 1. Brief schematic process flow of the thick oxide mask formation with multiple-size sub-m openings (gap reduction technique).

prevents the oxidation of the silicon substrate layer in subsequent process steps. A thin-film polysilicon layer is then deposited and patterned. The smallest feature size on the polysilm, typically). icon layer is determined by the lithography ( Finally, the patterned polysilicon is thermally oxidized in an oxidation furnace to form a thick oxide mask for the DRIE step. Meanwhile all the openings are reduced in size due to the enlargement of oxidized polysilicon in the lateral direction (oxide times thicker than the polysilicon consumed). Some poris tion of the polysilicon layer may remain preserved under the oxidized layer and will be removed after silicon trench etching. The final opening size in this process depends on the initial opening size in the polysilicon layer and the subsequent oxidation step. As a design guideline for fabrication of a specific final opening size, the actual opening size in the polysilicon layer should be measured and the difference between the measured value and the targeted opening size is the thickness of the grown -nm openings have been reoxide required. For example, alized by growing 1- m oxide on a polysilicon layer with initial m (1.4- m-thick polysilicon layer). measured opening of To study the effect of the polysilicon thickness on the lateral expansion of the oxide in the openings, a process simulator (CSUPREM) was used [8]. A silicon layer with variable thickness on top of a nitride layer is oxidized at 1000 C for 20 min and lateral expansion results are plotted in Fig. 2. Theses results suggest that the lateral expansion is not a function of the initial polysilicon thickness. Therefore, precise control of the polysilicon thickness is not required to achieve accurate opening size. The enabling features of this technique are as follows. 1) A cost-effective oxide mask with deep-sub- m feature sizes can be batch fabricated using conventional optical lithography equipments. 2) The oxide masking layer with deep-sub- m openings can be as thick as a few ms that facilitates deep trench etching in subsequent DRIE step. 3) Multiple-size sub- m gaps can be defined in a single step by varying the size of the original openings in the polysilicon mask. This feature is not available in other small gapformation techniques based on sacrificial layers. A fabricated oxide mask with two sub- m openings is shown in Fig. 3. The mask has been consequently used to etch a trench in the silicon substrate. In our method, the accuracy of the final opening size depends directly on the accuracy of the lithographically-patterned opening size in the polysilicon layer. Therefore, uniform creation of sub-100-nm openings in the oxide mask

Fig. 2. Lateral expansion of a silicon layer with various thicknesses, oxidized for 20 min at 1000 C simulated in CSUPREM [7].

Fig. 3. SEM picture of multiple sub-m openings in the oxide mask used to etch trenches in silicon.

may become difficult because of the variations in lithography across a wafer. However, a small variation in the original recipe can partially resolve the encountered issue, in case sub-100 nm openings are desired. A thicker deposited polysilicon followed by a longer oxidation step results in closing of the openings all over the wafer [Fig. 4(a)]. To define the very small opening size, an accurately-timed buffer oxide etch (BOE) step will be performed next, and in this way the opening sizes are defined with more uniformity across the wafer. SEM pictures of Fig. 4(b) and (c) show cross sectional view of the closed opening in Fig. 4(a), after a 30 and 60 s BOE step, respectively. Measuring the opening size on different spots of a single wafer showed less than 50 nm total variation after a 30 s BOE step. There is another important advantage in defining the opening sizes by a timed BOE step. The edges of the patterned polysilicon opening may not be very smooth, mainly because of the rough edges of the resist layer being transferred to the poly layer. This

ABDOLVAND AND AYAZI: A GAP REDUCTION AND MANUFACTURING TECHNIQUE FOR THICK OXIDE MASK LAYERS

1141

Fig. 4. SEM pictures of: (a) a closed opening filled with oxide, (b) the same opening after a 30 s BOE step, and (c) the same after a 60 s BOE step.

roughness will also appear in the oxidized polysilicon layer and introduces striation on the sidewalls of the etched trench (Fig. 5). The timed BOE step at the end can potentially reduce the roughness of the mask opening and consequently smoother sidewalls are expected. III. TRENCH ETCHING The Bosch process is widely used to etch high aspect ratio trenches in silicon [9]. However, the application of recipes developed for m-scale trenches in the sub- m domain may result in excessive undercuts as well as rough and exceedingly scalloped (relative to the gap side) trench sidewalls. Numerous approaches have been studied to reduce the sidewall roughness and increase the aspect ratio of trenches fabricated using the Bosch process [10], [11]. All these efforts target highly anisotropic etching step and efficient sidewall passivation. These can be partially accomplished by any of the following modifications. 1) Reducing the overall cycle time while keeping the (etch-topassivation) time ratio constant. This reduces the roughness of the sidewalls by decreasing the isotropic etch time at the bottom of the trench before the next passivation step protects the sidewall. 2) Increasing the RF bias voltage that elevates the plasma ion flux and energy, and improves the directionality of the plasma reactive particles. This increases the availability of plasma species at the bottom of a trench with a narrow opening. However, too much increase in bias voltage causes visible bowing in the trench profile [12]. 3) Reducing the chamber pressure, which increases the mean free path of the plasma particles and improves directionality of energetic ions toward the target. The SEM pictures in Fig. 6 present the trenches etched in STS advanced silicon etcher (ASE) tool using the recipes that incorporate all the aforementioned modifications. Recipe parameters are summarized in Table I. Results show significant improvement in sidewall smoothness with acceptable aspect ratios . The etching/passivation time has the major contribution in the sidewall profile improvement. The scalloping size nm and the undercut are reduced to less than 100 nm for opening sizes (compared to 200 nm while the etching/passivation time is 8/6). However, the trench width is always greater at the mask opening and the trench is tapered at the bottom.

Fig. 5. Effect of rough oxide mask edges on the sidewalls of the etched trench.

These are implications of overetching the passivation layer on the sidewall near the top and underetching at the bottom of the trench. Further reduction of the chamber pressure and increase of the bias voltage might facilitate enhanced trench profiles with higher aspect ratios. However, aspect ratio values greater than 30 are seldomly reported at the sub- m regime using the basic Bosch process. One way to significantly improve the highest achievable aspect ratio using Bosch-type recipes is to optimize the so called depassivation step that involves etching the passivation layer at the bottom of the trench. In two-step Bosch recipes, the depassivation is performed during the initial portion of the etching step. To introduce an individual depassivation step to the recipe, a third plasma pulse can be added in between the two passivation and etching steps [13]. Interestingly, the application of a short oxygen plasma pulse as a depassivation step has proven to be very successful in etching sub- m trenches with very high aspect ratios [14]. Presumably oxygen plasma species can etch the polymer passivation layer much faster at the bottom of the trench without attacking the sidewalls significantly. However, application of oxygen plasma prohibits the usage of organicbased masking material, which is a drawback in general but promotes the mask making method outlined in this paper.

1142


Fig. 6. SEM pictures of 125 nm and 240 nm wide trenches with aspect ratios 20 : 1 etched in silicon using the basic two-step Bosch recipe.

TABLE 1 BOSCH PROCESS RECIPE PARAMETERS USED TO ETCH SUB-m TRENCHES IN STS ASE TOOL

Fig. 7. SEM picture of a 12-m-deep 210-nm-wide trench etched in ALCATEL AMS 200. (AR 60 : 1).

The efficiency of the triple pulse recipe developed by Alcatel (SHARP) is investigated by etching trenches on the wafers covered with 0.8- m-thick oxide masks and 200-nm opening size fabricated using the gap reduction method. As shown in Fig. 7, 200-nm-wide trenches with aspect ratios as high as 60:1 have minute process. Because of the limited been achieved in a , thicker oxide silicon to oxide selectivity of the process is required to perform longer process time. IV. SINGLE MASK DEVICES ON SOI The oxide mask formation technique proposed in Section II offers a method for creating various sub- m as well as m-sized openings using a single optical patterning step. This feature enables the fabrication of capacitively-transduced MEMS devices using a single-mask process on SOI. The schematic process flow is shown in Fig. 8. The process is the same as what was described earlier in this paper to create the oxide mask. Trenches are etched down to the buried oxide layer of the SOI substrate. The oxide and nitride layers are removed and finally a wet HF release step is performed. Unlike the processes that create small gaps by removing the sacrificial oxide layer, the HF release step in this process is short (enough to remove the oxide beneath the movable structure). V. FABRICATION AND TEST RESULTS The single-mask process was used to fabricate electromechanical resonators with sub- m capacitive transduction gaps. Various resonators with different structural design were drawn on the mask to cover a broad range of frequencies. The simplicity of the process flow along with the all single crystal silicon resonator structure assures a very high yield process, providing low-defect devices with repeatable performance. This feature makes the process a remarkable candidate to study

Fig. 8. Schematic process flow of the single-mask reduced-gap process.

loss mechanisms in micromachined resonators. Fig. 9 shows fabricated IBAR resonators [15] designed to perform in the low VHF band. The two extended areas on either end (resembling the I shape) of these block resonators are designed to provide more transduction capacitance and reduce the motional impedance of the resonating structure. The gap size for these devices is measured to be between 250 and 400 nm for 5 to 10- m-thick devices. The resonators are directly connected to a network analyzer in a two-port configuration in a vacuum chamber. Frequency response plots measured from devices in Fig. 9 are shown in Fig. 10 correspondingly. The large difference between the measured Q of the 140 m long IBARs of Fig. 9(a) and (b) is noticeable considering that these two resonators are only different in the size of their support-beam.

ABDOLVAND AND AYAZI: A GAP REDUCTION AND MANUFACTURING TECHNIQUE FOR THICK OXIDE MASK LAYERS

Fig. 9. SEM pictures of fabricated IBAR resonators on a 10-m-thick SOI substrate with support beam. (b) 140-m-long with 20 m (l) 6 m (w) support beam. (c) 50-m-long.

2

1143

400 nm gap size. (a) 140-m-long with 20 m (l) 2 10 m (w)

Fig. 10. Frequency response plots corresponding to devices in Fig. 9 (one-to-one match).

Fig. 11. SEM pictures and frequency response plots measured from SiBAR resonators fabricated on a 5 m thick SOI substrate with 40-m-wide, 80-m-long. (b) 20-m-wide, 80-m-long.

Identical devices on different dies showed almost the same quality factor values (less than 5% variation). This observation solidly confirms that measured quality factors are limited by geometry-dependent loss mechanisms such as loss of energy through the support and not by randomly process-dependent deficiencies. The measured motional impedance of the device with the highest Q (75000) was recorded to be the lowest (46 k ) amongst the others (as expected). Another class of resonators called SiBARs [16] was also fabricated and tested using the single-mask process. These devices are designed to perform at higher frequencies compared to IBARs. The laterally extended capacitive gap area in SiBAR resonators reduces the motional impedance of the device in higher range of frequencies. Two fabricated 80- m-long

250 nm gap size. (a)

SiBARs with measured resonance frequencies of 105 MHz (40- m-wide) and 205 MHz (20- m-wide) are shown in Fig. 11. Comparing the measured motional impedance of these devices at 50-V polarization voltage with that of their counterparts fabricated through a sacrificial layer based process (HARPSS) [16] proves the single-mask process practical and viable for the implemention of high-frequency silicon MEMS resonators. This is even more the case considering that most of the reported high frequency capacitive MEMS resonators use capacitive gaps with a less than 60:1 aspect ratio [17], which has been demonstrated in this paper. Therefore, with proper resonator design and scaling down of the mask opening size to 100 nm while keeping the trench aspect ratio larger than 50:1, UHF resonators are easily achievable.

1144


VI. CONCLUSION A simple cost-effective process for fabrication of thick oxide masks with deep-sub- m openings was presented. Less than 100 nm wide openings in 1.5 m thick oxide were demonstrated. Modified Bosch and tripled-pulse DRIE recipes were implemented to etch high aspect ratio trenches in silicon using the oxide mask. A single mask process was used to fabricate all single crystal silicon resonators with narrow dry-etched capacitive transduction gaps. Measured frequency response plots from fabricated devices were presented with frequencies as high as 205 MHz and quality factor values as high as 75 000. These results illustrate the great potential of the single-mask process for implementation of high frequency capacitive MEMS resonators, as well as other MEMS device.

[11] M. Chabloz, “Improvement of sidewall roughness in deep silicon etching,” Microsyst. Technol., vol. 6, pp. 86–89, 2000. [12] M. Boufnichel, “Profile control of high aspect ratio trenches of silicon. I. Effect of process parameters on local bowing,” J. Vac. Sci. Technol. B 20, pp. 1508–1513, Jul./Aug. 2002. [13] M. A. Blauw, “Advanced time-multiplexed plasma etching of high aspect ratio silicon structures,” J. Vac. Technol., vol. B 20, pp. 3106–3110, 2002. [14] M. Puech, “A novel plasma release process and a super high aspect ratio using ICP etching for MEMS,” in Proc. SEMICON, Japan, Dec. 2003. [15] G. K. Ho, “Low-motional-impedance highly-tunable I resonators for temperature-compensated reference oscillators,” in Proc. MEMS’05, Miami, FL, 2005, pp. 116–120. [16] S. Pourkamali, “Vertical capacitive SiBARs,” in Proc. MEMS’05, Miami, FL, 2005, pp. 116–120. [17] J. Wang, Z. Ren, and C. T.-C. Nguyen, “Self-aligned 1.14-GHz vibrating radial-mode disk resonators,” in Proc. Transducers’03, Jun. 2003, pp. 947–950.

ACKNOWLEDGMENT

Reza Abdolvand (M’02) was born in Shiraz, Iran, in 1976. He received the B.S. and M.S. degrees in electrical engineering from Sharif University of Technology, Tehran, Iran, in 1999 and 2001, respectively. He is currently working toward the Ph.D. degree with the Integrated MEMS group at the Georgia Institute of Technology, Atlanta. His research interests are in the areas of integrated microresonator fabrication and characterization with applications in RF circuits and sensory systems, as well as high performance inertial sensor design and

The authors would like to thank Alcatel Micromachining Systems for the valuable collaboration in etching samples. They would also like to thank the staff at the Microelectronic research Center Cleanroom at Georgia Tech for their support. REFERENCES [1] B. V. Amini, “A high resolution, stictionless, CMOS compatible SOI accelerometer with a low noise, low power, 0.25 m CMOS interface,” in Proc. IEEE MEMS‘04, Jan. 2004, pp. 572–575. [2] S. Pourkamali and F. Ayazi, “18 m thick high frequency capacitive HARPSS resonators with reduced motional resistance,” in Proc. SolidState Sensors, Actuators, Microsystems Workshop, Hilton Head, SC, Jun. 2004, pp. 392–393. [3] J. R. Clark, “High-Q VHF micromechanical contour-mode disk resonators,” in Proc. IEEE IEDM, San Francisco, CA, Dec. 11–13, 2000, pp. 399–402. [4] W.-C. Tian and S. W. Pang, “Released submicrometer Si microstructures formed by one-step dry etching,” J. Vac. Sci. Technol. B 19, pp. 433–438, Mar./Apr. 2001. [5] T. Mattila, “A 12MHz Micromachined bulk acoustic mode oscillator,” Sensors Actuators A, vol. 101, pp. 1–9, Sept. 2002. [6] S. Pourkamali and F. Ayazi, “Fully single crystal silicon resonators with deep-subm dry-etched transducer gaps,” in Proc. IEEE MEMS ’04, Jan. 2004, pp. 813–816. [7] R. Abdolvand and F. Ayazi, “Single-mask reduced-gap capacitive micromachined devices,” in Proc. IEEE Microelectromechanical Systems Conf. (MEMS’05), Miami, FL, Jan. 2005, pp. 151–154. [8] , [Online]. Available: http://www.crosslight.com/Product_Overview/ brochure/csuprem_brochure.pdf [9] F. Laemer and A. Schilp, “Method of anisotropically etching silicon,” U.S. Patent 5501893, of Robert Bosch GmbH. [10] B. Volland, “Dry etching with gas chopping without rippled sidewalls,” J. Vac. Sci. Technol. B 17, pp. 2768–2771, Nov./Dec. 1999.

fabrication.

Farrokh Ayazi (S’96–M’99–SM’05) received the B.S. degree in electrical engineering from the University of Tehran, Tehran, Iran, in 1994, and the M.S. and Ph.D. degrees in electrical engineering from the University of Michigan, Ann Arbor, in 1997 and 2000, respectively. He joined the Faculty of the Georgia Institute of Technology, Atlanta, in December 1999, where he is currently an Associate Professor in the School of Electrical and Computer Engineering. His research interests are in the areas of integrated micro- and nanoelectromechanical resonators, RF MEMS, MEMS inertial sensors, VLSI analog circuits and techniques, and microfabrication technologies. Prof. Ayazi is a 2004 recipient of the National Science Foundation CAREER award, the 2004 Richard M. Bass Outstanding Teacher Award (determined by the vote of the ECE senior class), and the Georgia Tech College of Engineering Cutting Edge Research Award for 2001–2002. He received a Rackham Predoctoral Fellowship from the University of Michigan for 1998-1999. He is a Subject Editor for the JOURNAL OF MICROELECTROMECHANICAL SYSTEMS and serves on the Technical Program Committee of the IEEE International Solid-State Circuits Conference (ISSCC).