A High-Density Time-to-Digital Converter Prototype Module for BES III ...

IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 60, NO. 5, OCTOBER 2013

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A High-Density Time-to-Digital Converter Prototype Module for BES III End-Cap TOF Upgrade Huanhuan Fan, Changqing Feng, Weijia Sun, Chunyan Yin, Shubin Liu, and Qi An

Abstract—This paper describes a high-precision time measurement module for the end-cap time-of-flight (ETOF) upgrade of the Beijing Spectrometer (BES III). ETOF is scheduled to be upgraded with the multi-gap resistive plate chambers (MRPCs) instead of a scintillator. The new ETOF of BES III will have 1728 readout channels, which is a big challenge for the readout electronics. The time resolution of the readout electronics system is required to be better than 25 ps. A 9U VME module with 72 time measurement channels is designed to perform the time measurement. The signals, which are produced by the detector and then amplified and discriminated by the attached frontend electronics, are sent to this module. The module, which is named TDIG, uses the CERN HPTDC to achieve high-precision time measurement. There are nine HPTDC chips on the module, and each provides eight channels to realize 72 channels. A series of experiment tests show that the time resolution of the TDIG module is better than 20 ps. We have constructed a beam test system composed of six plastic scintillators, two MRPC modules, and ETOF prototype electronics, which testifies to the time resolution expected. An overall time resolution of less than 45 ps for beam events has been achieved. Index Terms—BES III, time of flight (TOF), time-to-digital converter (TDC).

I. INTRODUCTION

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HE Beijing Electron Positron Collider (BEPC) and the Beijing Spectrometer (BES) [1], [2] are upgraded to BEPC II and BES III [3]–[5], respectively. In the BES III, the time-of-flight (TOF) system plays a critical role in performing particle identification (PID) as well as fast triggers for charged particles. It is based on plastic scintillator bars read out by fine mesh photomultiplier tubes directly attached to the two end faces of the bars and consists of one barrel (BTOF) and two end caps (ETOF). There are a total of 352 PMTs in the barrel, and 96 PMTs in the end cap. This represents an amount of 448 signals to process. The readout system of the TOF system has achieved a timing resolution of 25 ps after time-walk and Manuscript received July 01, 2012; revised October 27, 2012 and January 15, 2013; accepted February 25, 2013. Date of publication April 05, 2013; date of current version October 09, 2013. This work was supported by the Knowledge Innovation Program of the Chinese Academy of Sciences (KJCX2-YW-N27), the National Natural Science Foundation of China (No. 10970033). The authors are with the State Key Laboratory of Particle Detection and Electronics, University of Science and Technology of China, and Anhui Key Laboratory of Physical Electronics, Department of Modern Physics, University of Science and Technology of China, Hefei, Anhui 230026, China. (e-mail: [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TNS.2013.2251003

integral nonlinearity (INL) corrections. The amplitude-dependent time-walk correction is accomplished by measuring corresponding pulse height. Achieved pulse-height resolution is better than 10 mV in a dynamic range 180–5000 mV [6]. The total time resolution is better than 90 ps (for BTOF) and 138 ps (for ETOF), which enables the BES III system to achieve the physical goal of a 95% confidence level and K separation for momenta up to 1 GeV/c. In order to enhance the capability of PID, a 95% confidence level and K separation for momenta is required to go up to 1.4 Gev/c from 1 Gev/c. It means that each measurement channel of the ETOF system should have a total time resolution better than 80 ps. To satisfy the requirement, the system specification of the ETOF electronics calls for a time resolution of better than 25 ps. The whole project of the ETOF system upgrade is under design at present. The time-of-flight array for the upgrade of the ETOF system will be built using multi-gap resistive plate chambers (MRPCs) [7], [8], which has been used in many large experiments successfully, such as ALICE TOF at LHC [9], STAR TOF at RHIC [10], for its good time resolution, high efficiency, and high counting rate. After upgrade, the whole ETOF system will consist of 72 MRPC modules, which leads to a total of 1728 readout channels. That will be a big challenge for the readout electronics. The whole electronics system mainly consists of 72 front-end electronics (FEE) modules, 24 time-to-digital converter (TDIG) modules, two coincidence-threshold-test-power (CTTP) modules, and two clock master modules. They are housed on two VME64xP crates on average. One crate is located in the east of the BES III for the east end-cap TOF, and the other is in the west for the west end-cap TOF. The top-level diagram of the ETOF electronics is shown in Fig. 1. The FEE module, whose function is mainly amplifying and discriminating the signals coming from MRPC, is based on the NINO ASIC technology [11], [12], which can fully exploit the excellent timing properties of MRPC. The detector is connected to the input of the FEE modules with a short transmission line to reduce signal attenuation. The output pulses of the NINO ASIC have fast edges and the width of them is dependent on the input charge (nonlinear dependence). Thus, the signal charge can be measured by time-over-threshold (the time of the leading and trailing edge of the pulse). Instead of measuring amplitude, this can be used to perform time-walk correction and highly simplifies the front-end circuit. The CTTP module receives 144 pairs of OR differential signals from the FEE modules to do coincidence processing and forms the fast hit signals, which are transmitted to the TOF

0018-9499 © 2013 IEEE

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Fig. 1. The top-level diagram of the ETOF electronics.

trigger subsystem [13] over the optical fiber. This module also provides power, test signals, etc., to FEE modules. For the end-cap TOF electronics after upgrade will continue to use a high-performance time-to-digital converter (HPTDC) to achieve time resolution of less than 25 ps, the TOF clock system for BES III [14] will be used to provide the very high accurate clock. It provides a precise 40-MHz clock signal, and the clock jitter is less than 20 ps (root mean square), which could ensure the 25-ps time resolution. The TDIG module receives the signals from FEEs to accomplish the digitalization. II. DESCRIPTION The TDIG module is based on 9U VME and mainly consists of four components: signals receiver, time measurement, FPGA part, and CPLD part. Fig. 2 shows the module’s schematic diagram. A. Signal Receiver The signals from the FEE modules are fed into the TDIG module over cables. Because the TDIG module is several meters away from the ETOF detector, both the dedicated cable for transmitting LVDS signals and the LVDS buffer are applied in the design to ensure the signal quality. Considering the feature of the signals, we finally select the connector VRDPC-68-01-M-RA and the shielded differential cable VPSTP-24-5000-01from SAMTEC. The connector and

cable concentrate on receiving and transmitting LVDS signals and are able to shield noise very well due to the dedicated ground pins. In addition, each connector has up to 24 pairs of inputs that effectively increase integration level. B. Time Measurement Time measurement is the key to the TDIG module. As mentioned above, the signals from MRPC are digitized using the CERN HPTDC technique [15], [16]. The HPTDC chip can be programmed into four different operation modes. Since the TDIG module is required to achieve a time resolution better than 20 ps, the HPTDC chip is operated in the very high resolution mode. Nine HPTDC chips are used to achieve 72 channels time measurement in each TDIG module. However, when HPTDC chip is operated in the very high resolution mode, the time bins’ nonlinearity caused by unequal bin widths in the resistance–capacitance (RC) tapped delay lines, unequal bin widths in the delay-locked loop, and the coarse clock crosstalk from the logic part to time measurement part of the chip will significantly deteriorate the time resolution. Aiming at this problem, an online calibration method is employed to perform the INL error correction. The INL values are stored in a lookup table (LUT) RAM in the Cyclone field-programmable gate array (FPGA) and compensate the raw time measurement data. All the compensation work is implemented by the FPGA logic [16].

FAN et al.: A HIGH-DENSITY TIME-TO-DIGITAL CONVERTER PROTOTYPE MODULE FOR BES III END-CAP TOF UPGRADE

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Fig. 2. A scheme of the time-to-digital converter module.

Fig. 3. Result of simulating the 32-bit data bus of the nine HPTDC chips without a bus driver (the nine chips share the data bus).

C. Part of FPGA The primary time measurement data directly outputted by the nine HPTDC chips are forwarded to a Cyclone III FPGA to be compensated online. Then, they are packed into a TOF 64-bit data format, including the information of crate slot number, trigger number, and time measurement. Finally, the data are stored in the FPGA readout first-in first-out (FIFO) and are then transmitted to the VME master in chained block transfer (CBLT) D64 mode. All the data processing logic is implemented in one Cyclone III FPGA. D. Part of CPLD This part achieves the next several functions: 1) configuring FPGA online by reading the FPGA configure logic from

Fig. 4. Result of simulating the 32-bit data bus of the nine HPTDC chips with a bus driver (the nine chips share the data bus).

FLASH; 2) communicating with FPGA and transmitting the FPGA data to PC via VME bus; and 3) serving as VME interface and forwarding the packed data to a VME master card in CBLT D64 mode.

III. MANAGEMENT OF THE NINE HPTDC CHIPS Nine HPTDC chips are applied in this module to optimize the system integration level, but it also increases the difficulty of design and reduces the reliability. The layout of this part is directly related to the signal integrity and the reliability of the data transmission. The simulation related to this part was conducted before PCB fabrication.

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Fig. 6. Waveform of pre-emulation of the nine-HPTDC-chip data bus.

Fig. 5. Block diagram of the wiring of the nine HPTDC chips data bus.

The presimulation is carried out by the ADS software of Agilent Technologies. The signal quality of the 32-bit data bus between nine HPTDC chips and FPGA is considered specially. Some attempts to use different simulation models are made as follows. The model that nine chips share the data bus and are directly connected to FPGA without any buffer was first simulated. The result is shown in Fig. 3. The signal’s rise time is greater than 10 ns, and the signal reflection is obvious. It proves that the design cannot meet the requirement of signal integrity and is unavailable. Then, a data bus driver (SN74LVTH162245) is added to improve the signal quality. The bus driver is placed as close as possible to the FPGA. Fig. 4 is the waveform of this simulation. The rise time is reduced to about 2 ns, and the signal reflection magnitude is also reduced markedly. Based on the results, the data bus driver is quite necessary and useful to improve the signal quality. Some other models with bus driver were also simulated respectively so that every two, three, four, or five chips share a common data bus, which is followed by a bus driver. The results show that the signal quality of these models is almost the same. Considering all aspects, we adopt the scheme as a tree structure: every three HPTDC chips share the data bus, which is subsequently driven by a bus driver, and then the three bus drivers share the data bus and are connected to the FPGA. Fig. 5 simply shows the layout design of the nine HPTDC chips data bus. Fig. 6 is the waveform of the presimulation. The corresponding result of postsimulation with the SigXplorer tool offered by Cadence is shown in Fig. 7. From the results, we can see that the signal’s quality is enough to match the requirement of signal integrity.

Fig. 7. Waveform of aft-emulation of the nine-HPTDC-chip data bus.

Fig. 8. Timing diagram of the token-ring data transmission.

The token ring is introduced to control the arbitration and data transmission. The timing diagram of the data transmission is shown in Fig. 8. The token ring is sent from the master HPTDC chip. In this design, one HPTDC chip is programmed as master and others as slaves. To enhance the flexibility of configuration and satisfy the signal integrity, the nine HPTDC chips are separated into three groups to be configured. Every three HPTDC chips share one JTAG interface, and there are three independent configure


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Fig. 12. Statistical spread of the cable delay measurements, where (a) shows the leading time resolution (channel 0 and channel 2 of HPTDC#4) and (b) shows the trailing time resolution (channel 0 and channel 7 of HPTDC#9).

Fig. 9. Schematic diagram of the HPTDC chips configure chain.

Fig. 13. Statistical spread of the cable delay measurements combing with FEE module, where (a) shows the leading time resolution (channel 0 and channel 4 of HPTDC#7) and (b) shows the trailing time resolution (channel 0 and channel 7 of HPTDC#9).

Fig. 10. INL curve of HPTDC (channel 0 of HPTDC#4).

Fig. 14. Every channel’s time resolution of HPTDC#4, HPTDC#5, and HPTDC#6; the HPTDC#5 and HPTDC#6’s symbols of the channel 2 and channel 8 are overlapping.

IV. TEST RESULT OF PERFORMANCE A. Characterization of Nonlinearity

Fig. 11. Block diagram of the test stand.

chains in total. Fig. 9 shows the schematic diagram of one configure chain. Before configuring HPTDC chips, the configure data are stored in the FPGA RAM. When the FPGA receives the command of configuring HPTDC chips, FPGA starts the configuring course. The HPTDC chips’ status and initialization can also be achieved by JTAG bus.

The code density test is performed to test the HPTDC chip’s integral nonlinearity. Fig. 10 shows the INL curve of one channel of one HPTDC chip. The line presents the INL without calibration, and it is in the range 2/9LSB. The line is the INL after calibration, and it is in the range 3/1LSB. With the software calibration, the INL can be further improved. B. Timing Performance The cable delay method [17], [18] is adapted to test this module’s timing performance. The test platform diagram is shown in Fig. 11. The TEK AFG3252 signal generator provides two relevant TTL signals. The signals have 2.5-ns transition time in both leading edge and trailing edge. The signal delay time

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Fig. 15. Block diagram of the beam test system.

between the two channels could be adjusted. The TTL signals are converted to LVDS level by test module and finally sent to the TDIG module to be digitized. In addition, the generator can also provide a synchronous trigger signal to the TDIG module. First, we fix the delay time to test all channels’ timing precision; second, we vary delay time from 25 to 25 ns with the step length of almost 2 ns to cover the whole clock period (25 ns). Fig. 12. shows the statistical spread of the cable delay measurements, where (a) shows the leading edge time resolution (channel 0 and channel 2 of HPTDC#4) and (b) shows the trailing edge time resolution (channel 0 and channel 7 of HPTDC#9). Thus, the time resolution of the TDIG module is better than the design specification of 20 ps. Then, we tested the TDIG module’s performance combined with the front-end electronics. We use the FEE module instead of the test module in Fig. 11 to convert the TTL signals to LVDS signals. Fig. 13(a) and (b), respectively, shows the leading edge and trailing edge time resolution, which are all about 15 ps much better than the design specification of 25 ps. Each channel’s time resolution of the HPTDC#4, HPTDC#5, and HPTDC#6 is shown in Fig. 14. Channel 1 is a reference in all the tests. All the results are better than 20 ps and meet the requirement. C. Beam Test The beam test has been done with the FEE modules and the MRPC detector in IHEP in June 2011. The block diagram of the beam test system is presented in Fig. 15. The four small scintillators serve as time reference, and their output signals are finally sent to the TDIG module and the QDC module, respectively. The purpose of the charge measurement is to calibrate the time walk of the time measurement. The common trigger comes from the coincidence of the signals of the six plastic scintillators, containing two big ones and four small ones. The MRPC detectors’ signals are digitized in the TDIG module after being dealt by the FEE modules. The measured timing data is fetched to the PC via VME bus.

Fig. 16. One result of the beam test in Beijing in June 2011, in which the total time resolution is better than 45 ps and the efficiency is about 100%.

During the whole test, we conducted a voltage scan, a threshold scan, and a position scan to test the performance of the MRPC detector. Fig. 16 shows one result of the beam test, which is under the following conditions that the positive and negative high voltage of the MRPC detector are 7200 V and 7200 V, and the threshold of the FEE module is 210 mV. The -axis presents the hit position where the beam targets the MRPC detector. Each MRPC detector has 12 pads, and the performance differences of most pads are nuanced enough, it is unnecessary to take too long to test every pad’s performance. In the end, five typical pads are selected to be tested. The left -axis presents the time resolution (the square dots) of the whole beam test system, and the right -axis presents the efficiency (the round dots) of the corresponding pad. This result presents that all the total time resolution containing the MRPC detector, the FEE module, and the TDIG module is better than 45 ps and the efficiency is about 100%. The requirement of the end-cap TOF upgrade can be met.


V. CONCLUSION A 72-channel time-to-digital converter module is implemented based on the 9U VME interface. The CERN HPTDC ASIC technique is applied to achieve the time resolution of better than 20 ps. Lots of tests are taken to detect the module’s time performance, including the test combing the front-end electronics and the beam test. All the test results present that the time resolution of the module can meet the requirement. ACKNOWLEDGMENT The authors would like to thank X. Jiang and H. Dai for providing the front-end modules and C. Li, Y. Sun, and S. Yang for providing the MRPC modules. They also want to thank all the collaborators of the beam test for their useful suggestions and support. REFERENCES [1] J. Z. Bai et al., “The BES detector,” Nucl. Instrum. Methods A, Accel. Spectrom. Detect. Assoc. Equip., vol. 344, no. 2, pp. 319–334, May 1994. [2] J. Z. Bai et al., “The BES upgrade,” Nucl. Instrum. Methods A, Accel. Spectrom. Detect. Assoc. Equip., vol. 458, no. 3, pp. 627–637, Feb. 2001. [3] F. A. Harris, BES Collaboration, “BEPCII and BESIII,” Nucl. Phys. B (Proc. Suppl.), vol. 162, pp. 345–350. [4] W. Li, BES Collaboration, in Proc. 4th Flavor Phys. CP Violation Conf. (FPCP 2006), Vancouver, BC, Canada, Apr. 9–12, 2006 [Online]. Available: http://fpcp2006.triumf.ca/agenda.php [5] BES Collaboration, “The construction of the BESIII experiment,” Nucl. Instrum. Methods, vol. 598, no. 1, pp. 7–11, Jan. 2009.

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