A High-Linearity, 17 ps Precision Time-to-Digital Converter Based on ...

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 60, NO. 3, MARCH 2013

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A High-Linearity, 17 ps Precision Time-to-Digital Converter Based on a Single-Stage Vernier Delay Loop Fine Interpolation Bojan Markovic, Member, IEEE, Simone Tisa, Federica A. Villa, Alberto Tosi, and Franco Zappa, Senior Member, IEEE

Abstract—This paper presents a time-to-digital converter (TDC) architecture capable of reaching high-precision and high-linearity with moderate area occupation per measurement channel. The architecture is based on a coarse counter and a couple of two-stage interpolators that exploit the cyclic sliding scale technique in order to improve the conversion linearity. The interpolators are based on a new coarse-fine synchronization circuit and a new single-stage Vernier delay loop fine interpolation. In a standard cost-effective 0.35 m CMOS technology the TDC reaches a dynamic range of 160 ns, 17.2 ps precision and differential non-linearity better than 0.9% LSB rms. The TDC building block was designed in order to be easily assembled in a multi-channel monolithic TDC chip. Coupled with a SPAD photodetector it is aimed for TCSPC applications (like FLIM, FCS, FRET) and direct ToF 3-D ranging. Index Terms—Coarse-fine architecture, delay-locked loop (DLL), single photon avalanche diode (SPAD), TCSPC, time interval measurement, time-of-flight, time-to-digital converter (TDC), Vernier delay line.

I. INTRODUCTION

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RIGINALLY developed for nuclear science experiments, circuits capable of measuring time intervals nowadays find use in a wide variety of applications. They are commonly employed for scientific experiments [1]–[3], optical distance measurements [4]–[7], positron emission tomography [8], [9], test instrumentation [10], [11], space science instruments [12], and more recently also for clock and data recovery and all-digital frequency synthesis in telecommunication systems [13]–[19]. A time interval is usually defined by two electrical pulses (START and STOP pulses), and the simplest way to measure it is to enable a counter by means of the START signal and then count a very high frequency clock [3] until the arrival of the STOP signal. The time resolution of this approach is given by the clock period; hence for sub-nanosecond resolution more than 1 GHz clock is required. Therefore, other methods have been proposed, classified as digital (if they perform direct conversion from time interval to Manuscript received July 11, 2011; revised November 18, 2011, February 09, 2012; accepted March 06, 2012. Date of publication January 11, 2013; date of current version February 21, 2013. This work was supported in part as the “MiSPiA” project within the ICT theme of the EU Seventh Framework Programme (FP7, 2007–2013) under Grant 257646. This paper was recommended by Associate Editor H. Luong. The authors are with the Dipartimento di Elettronica e Informazione, Politecnico di Milano, Milan I-20133, Italy (e-mail: [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TCSI.2012.2215737

digital code) or analog (if they pass by an intermediate step of conversion to an analogue voltage) [20]. The former ones are called time-to-digital converters, while the latter ones are often referred to with names more specific to the conversion method used (e.g., time-to-amplitude converter). Generally speaking, analogue methods allow better resolutions than the digital ones, however, digital methods are easier to implement in integrated circuits and are less sensitive to temperature variations and external disturbances, which makes them preferred choice for compact multi-channel implementations. Examples of analogue time-interval measurement methods are time-stretching followed by a counter [6], [21] and time-to-amplitude converter (TAC) followed by an analog-to-digital converter (ADC) [7], [8], [22]. The most used digital time-interval measurement techniques are: pulse-shrinking delay line [12], [19], [23], tapped delay line [1], [2], [14], and Vernier delay line [10], [16], [24], [25]. In order to guarantee good stability and intrinsic calibration for process, voltage and temperature (PVT) variations, integrated circuit implementations of methods based on delay lines make use of voltage-controlled delay cells, whose propagation delay is locked to a fraction of a reference clock period by means of a phase-locked loop (PLL) [2] or a delay-locked loop (DLL) [1], [4], [5], [12], [15], [23]–[27]. More recent digital techniques for time-interval measurements make use of time amplifiers [10], [28], [29] to amplify (i.e., extend) time residues, thus relaxing the resolution requirement for the successive time-measurement circuits. If both long dynamic range and high resolution are required, the interpolation technique is employed [1], [4]–[8], [14], [17], [19], [21], [26], [27], [30]–[32], which makes use of a coarse counter and interpolators. The counter accumulates the number of reference clock periods within the time interval to measure, thus providing a long dynamic range. The interpolator subdivides and resolves a clock period into smaller time-bins, thus providing high time resolution to the converter. Aim of our research was to design a TDC architecture suitable for one-chip multi-channel implementation inside an array of single-photon avalanche diodes (SPAD) [26], [30]–[36] targeted at time-correlated single photon counting (TCSPC) [37] applications, where very faint (at the single photon level) and very fast (at picoseconds level) optical signals must be acquired, but also for direct time-of-flight (ToF) 3-D ranging measurements. The main challenges for this work were imposed by demanding requirements of TCSPC technique: resolutions around tens of picoseconds and differential non-linearity (DNL) better

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Fig. 1. TDC using both START and STOP interpolators in order to resolve the events within the clock period implements the sliding scale technique. For the same time interval T the START and STOP events occur in different regions of the START/STOP interpolator characteristics, therefore the overall linearity of the converter is significantly improved.

than 1%. In order to reach high resolution a two-stages interpolation is used. The coarse-fine interpolation exploits a new synchronization circuit. In order to achieve high linearity the sliding scale technique and a new one-stage Vernier delay loop fine interpolation are employed. The prototype TDC, fabricated in a standard low-cost 0.35 m high-voltage (HV) CMOS technology, reaches a dynamic range (i.e., the maximum time interval that can be measured unambiguously) of 160 ns, a precision (also referred to as singleshot precision), i.e., the standard deviation of the distribution of measurement results around the mean value when a constant time interval is measured repeatedly for a large number of times, of 17.2 ps, and differential non-linearity (DNL) better than 0.9% LSB rms. This paper is organized as follows. Section II introduces the sliding scale technique used to improve the linearity of the converter. The architecture of the developed TDC is described in detail in Section III. The prototype circuit and the experimental characterization are presented and discussed in Section IV. Finally, Section V summarizes and concludes this work. II. SLIDING SCALE TECHNIQUE As one of the main challenges of this work was to design a converter with very low DNL, the TDC was conceived in a way to overcome the effects of inevitable mismatches which cause non-linearity of an interpolator. This is archived by employing two interpolators, one for the START and the other for the STOP event, implementing this way a technique for linearity improvement. In fact, two different interpolation approaches are possible. In the first approach, START (or STOP) signal is synchronous to a reference clock and only one interpolator is required to measure the time elapsed between the arrival of STOP signal and the first successive clock edge. In the other approach, both START and STOP signals are asynchronous to the reference clock [4]–[7], [27]. The coarse counter is enabled by START pulse and then disabled by STOP signal, while the START and the STOP interpolator measure the time elapsed between the arrival of START and STOP pulses and the following reference clock rising-edge. The result of the conversion is the sum of the time delay measured by the coarse counter plus the

difference between the time delays measured by the START and the STOP interpolators, respectively. Although this second approach requires two interpolators instead of one, it inherently provides the capability to implement a known technique that significantly improves the linearity of the converter, namely the sliding scale technique, introduced by E. Gatti [38] in high precision ADC systems. In such systems, it consists in adding a random value to the signal applied to the ADC analog input and then subtract it from the ADC digital output. As the same quantity is added and subtracted, the overall result is again the conversion of the input signal; however, since the conversion of the same input signal is performed in different regions of the converter range, depending on the random number used, the effective linearity of the converter is improved. In a TDC, if START signal is synchronous to the clock, the same time interval is always converted using the same region of the converter range. Instead, with asynchronous START and STOP signals, the same time interval is converted using different regions of START and STOP interpolator ranges as shown in Fig. 1. The time difference (i.e., delay) between START pulse and the reference clock results in a random signal, which is added to STOP conversion but it is eliminated in the final conversion, after subtraction of START and STOP interpolation results. The sliding scale technique can be implemented also in TDCs with a single interpolator [17], however, in that case, an additional scrambling circuitry is required. The linearity improvement is proportional to the number of averaged bins which is in turn determined by the range of the random signal. In the case of classic sliding scale ADC, such range is limited by the amplitude of the analog input signal and the ADC full scale range (FSR). However, this limitation can be overcome by allowing the folding of ADC input within the FSR, thus resulting in the so-called cyclic sliding scale technique [39]. In TDCs with asynchronous START and STOP signals, the cyclic sliding scale technique is inherently implemented. All bins of the STOP interpolator are averaged between them, thus significantly improving the effective linearity of the converter. However, the ideal linearity is not reached because the “random signal” distribution, described by the START interpolator probability density function, is not uniform, thus not averaging all bins of the STOP channel with equal weights (this reasoning

MARKOVIC et al.: A HIGH-LINEARITY, 17 PS PRECISION TIME-TO-DIGITAL CONVERTER

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can be repeated equivalently by exchanging START and STOP interpolators). The improvement of linearity is paid in terms of a more complex structure (two interpolators instead of one) and a higher quantization error. As the measurement of a time interval is obtained as difference between START and STOP measurements, the quantization error is (1) is the resolution of the START interpolator, is the resolution of the STOP interpolator and LSB is the equivalent resolution of the TDC. Furthermore, the singleshoot precision is also degraded by the integral non-linearity (INL) of the interpolators. In fact, the sliding scale transforms the interpolators nonlinearities into random variables which are added to the measurement jitter. The single-shoot precision of a TDC based on a counter and two interpolators can be written as

were

(2) were is the quantization error described in (1), and are the standard deviations of the INLs of the START and STOP interpolator respectively, is the jitter of the reference clock and is the additional jitter of the signals within the TDC. III. TDC ARCHITECTURE A. Global Architecture The designed TDC makes use of a 4 bit coarse counter and ns), thus a 100 MHz reference clock (clock period is reaching a dynamic range of 160 ns. In order to provide high resolution and to improve linearity by means of the cyclic sliding scale technique, two interpolators are used to resolve the time delay elapsed between the START (and the STOP) pulse and the reference clock rising edge. Since the two interpolators are identical, hereafter the input event (either START or STOP) will be referred to as HIT. Furthermore, in order to reach high interpolation factor with small area occupation, both interpolators make use of two interpolation stages: the first coarse stage (not to be confused with the external coarse counter) employs 16 different phases of the reference clock to detect in which one of the 16 sub-periods the HIT event occurred; the second fine interpolator stage resolves the time elapsed between two successive clock phases sub-divided in 62 bins. The overall interpolation factor is the product of coarse and fine ones, namely . Therefore the time-resolution of the TDC is ps. Fig. 2 illustrates the operation principle of the developed TDC. The coarse counter output is proportional to the time , given by the reference clock period multiplied by the number of reference clock rising edges between START and STOP. The START and STOP interpolators provide the time elapsed between the corresponding HIT pulse and the reference clock rising edge. In particular, the first coarse interpolation stage measures the time elapsed between the first clock phase successive to the HIT pulse and the successive reference clock

Fig. 2. TDC operation principle. A counter counts the cycles of a 100 MHz clock, between START and STOP events, while START and STOP interpolators resolve the START and STOP occurrence, respectively, within one clock period. Both interpolators use two stages of interpolation: the first coarse one with an interpolation factor of 16, while the second fine one of 62. Eventually the clock period is subdivided in 992 bins.

rising edge (i.e., and for START and STOP, respectively). The time interval elapsed between the HIT pulse and the successive clock phase (i.e., and for START and STOP, respectively) is fed to the fine interpolator as the time elapsed between HIT_ASYNC and HIT_SYNC pulses, through a synchronizer. Time intervals and are then measured with 10 ps resolution by the fine interpolation stages, resulting in and . The overall time-interval T measurement result is given by the sum of times measured by the coarse counter and the START interpolator minus the time measured by the STOP interpolator: (3) Block schematics of the TDC is shown in Fig. 3. Three DLLs are used to generate a multiphase clock and to properly bias the fine interpolators. A 4 bit coarse counter and two 11 bit START and STOP interpolators are used to measure time-intervals with long dynamic range and high precision. The two interpolators are composed of a 4 bit coarse and a 7 bit fine interpolation stages and a synchronizer circuit. The various blocks are described in depth in the followings. B. Coarse Interpolator The coarse interpolator is a DLL-based multiphase clock interpolator. A DLL (shown in Fig. 4) uses a voltage-controlled delay line (VCDL) made of cells with variable propagation delay , in which the 100 MHz reference clock propagates. The overall delay of the VCDL is locked to the reference clock period by means of a phase-detector (PD) and a

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Fig. 3. TDC block schematics. Three DLLs are used to generate a multiphase clock and to properly bias the fine interpolators. A 4 bit coarse counter and two 11 bit START and STOP interpolators are used to measure time-intervals with long dynamic range and high precision. The two interpolators are composed of a 4 bit coarse and a 7 bit fine interpolation stages and a synchronizer circuit.

Fig. 4. Coarse DLL schematic. A phase-detector (PD) and a charge-pump (CP) are used to match the propagation delay of a voltage-controlled delay line (VCDL) to the period of the reference clock. The 16 outputs of the VCDL provide the multiphase clock for the following stages.

charge-pump (CP). Input buffers and load matching are used to guarantee that every cell of the VCDL is driven in the same way and drives the same load, so that all propagation delays introduced by VCDL cells are exactly the same, aside from statistical process mismatches. Therefore, the outputs of the 16 delay cells that compose the VCDL are multiphase clock signals delayed one from the successive one by a fixed value ps, that is stabilized in respect to PVT variations. The state of this set of multiphase clocks is sampled in correspondence of the HIT event by the coarse interpolator. The sampling is performed by means of arbiter circuits. The outputs of the 16 arbiters are then converted into a binary code by means of an encoder and the value is stored in 4 bit coarse interpolator output register, as shown in Fig. 5(b).

Fig. 5. Synchronizer circuit schematics. (a) Common implementation of the synchronizer based on multiphase sampling of the HIT signal, by means of flipflops. (b) Employed synchronizer circuit based on the selection of clock phases following the HIT signal, by means of arbiter circuits.

C. Synchronizer Task of the fine interpolator is to measure the time interval between the HIT signal and the first successive clock phase. Therefore, a “synchronizer” circuit capable of extracting the first one among the multiphase clocks successive to the HIT signal is required. The phase successive to the HIT signal represents the HIT signal synchronized to the multiphase clock, thus it is named HIT_SYNC, while the HIT signal provided to the fine interpolator is named HIT_ASYNC. Ideally HIT_ASYNC should be identical to the HIT signal itself, however, since the process of extraction of the successive clock phase implies some latency, in Fig. 2, the resulting HIT_SYNC is a delayed version of the target clock phase, therefore, the same delay has to be applied to the HIT signal, thus giving rise to the HIT_ASYNC signal. In this way, the time interval between HIT_ASYNC and HIT_SYNC, which is fed to the fine interpolator, is the same


time interval between the HIT signal and the successive clock phase. A standard approach [4]–[8], [21], [25]–[27] for synchronization of an asynchronous HIT event consists in sampling the HIT signal with N D-type flip-flops in correspondence of the N clock phases (in our case ). The flip-flops outputs are fed to a pseudo-nMOS OR gate which extracts the first clock phase that samples the high value of the HIT signal. In order to avoid problems when the HIT signal commutation occurs close to the edge of a clock phase (i.e., when the setup time constrain is not fulfilled), which could lead to an increase of flip-flop propagation delay and, possibly, also to a metastable state, other flip-flops are added in series to the ones sampling the HIT signal, thus giving them one clock period to resolve their state. A common implementation of the synchronizer circuit is shown in Fig. 5(a). This solution adds an offset of one clock period to the path of the HIT_SYNC signal, therefore the total delay between the clock phase successive to the HIT pulse and the HIT_SYNC signal is the sum of the propagation delay of the second flip-flop and of the pseudo-nMOS OR gate plus one period of reference clock. This delay should be replicated also on the HIT_ASYNC signal path, but as HIT_ASYNC cannot be synchronized to the clock like HIT_SYNC, calibration of the propagation delay of the synchronizer asynchronous branch is required. If the fine interpolation stage is based on analog techniques [6]–[8] (i.e., time-stretching or TAC) the offset of one clock period can be convenient as it shifts the time-residue to be measured away from the initial part of the conversion characteristic of the analog interpolator, which usually has poor linearity. However, in the case of digital fine interpolation stage, the presence of an offset of one clock period implies the necessity of large extension of fine interpolator dynamic range with a consequent large increase in area occupation and conversion time. The offset can be reduced to a fraction of clock period by shifting the clock phases of the second flip-flops in respect to clock phases of the first flip-flops [4], [5], [25], [27], however, the calibration of delay of the HIT_ASYNC path is in still necessary. This is achieved by tuning a voltage, Fig. 5(a), that controls the delay of a delay line present in the HIT_ASYNC path. In order to avoid either additional calibration circuitry or manual calibration of the synchronizer, we conceived the new synchronizer shown in Fig. 5(b), where no synchronizing elements (i.e., flip flops) are present in the HIT_SYNC path. In this way the HIT_SYNC delay is given only by the intrinsic propagation delay of cells along that path, hence it can be easily replicated in the HIT_ASYNC path too, by simply adding the same cells to that path. The synchronizer makes use of coarse interpolator arbiters. The arbiters determine which clock phases are successive to the HIT event, i.e., that are low when the HIT pulse arrives, and close the corresponding p-MOS switches. Therefore, the pseudo-nMOS OR gate commutes in correspondence of the first clock phase that rises after HIT. Buffers are added before the switches to delay the clock phases, thus guaranteeing that the arbiter has performed its function and the switch is completely commutated when a phase edge arrives at the switch. Therefore, the different commutation times of arbiters for nearly coincident input signals do not influence the propagation delay of the HIT_SYNC path, which remains fairly

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Fig. 6. Modifications of the classic Vernier delay line method. (a) Vernier delay loop based on circulation of local START (HIT_ASYNC) and local STOP (HIT_SYNC) signals through two loops, whose cells have slightly different propagation delays, until local STOP pulse overtakes the local START pulse. (b) Single-stage Vernier delay loop based on two loops with only one time-resolving element each, with consequent improvement of conversion linearity.

constant. Arbiter circuits, implemented as latching comparators, are used instead of conventional flip-flop circuits in order to reduce time-offset created by the mismatch in the data and clock propagation path, which in conventional flip-flops do not match well. The propagation delay on the HIT_SYNC path is given by the delay of a buffer, a MOS switch and the OR gate, therefore these delays are replicated also in the HIT_ASYNC path. In this way, apart from statistical mismatches, the delays of HIT_SYNC and HIT_ASYNC paths will match with no need of additional calibration circuits or manual calibration. D. Fine Interpolator Since the goal resolution (10 ps) is well below the propagation delay of a single logic cell in the target technology (0.35 m CMOS), a possible implementation of the fine interpolator could be a Vernier delay line which exploits the difference of propagation delays of two cells to set the conversion resolution. This method is based on two delay lines in which the HIT_ASYNC (i.e., local START) and HIT_SYNC (i.e., local STOP) signals propagate. The propagation delay of the cells in the HIT_SYNC line is shorter than the propagation delay of cells in the HIT_ASYNC line. Therefore, the HIT_SYNC signal, which initially is in late in respect to HIT_ASYNC, gradually reaches HIT_ASYNC signal and the corresponding cell number represents the result of conversion, stored in a thermometric code. However, this approach has two important drawbacks: it requires a high number of cells with consequent high

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Fig. 7. Detailed schematics of the fine interpolator with one time-resolving delay cell and other 4 cells per loop used to fix the total loop propagation delay to about 2 ns. The SR flip-flop and the three additional delay cells are necessary to regenerate the pulse-width of about 1 ns at every cycle.

Fig. 8. Two fine DLLs composed of 31 and 32 delay cells used to fix the propaps and ps, gation delays of the fine interpolator cells to ps (i.e., the least-sigthus resulting in a TDC time-resolution of nificant bit, LSB).

chip area occupation, and it highly suffers from mismatches between cells, thus resulting in a poor linearity. Therefore, a modified Vernier delay line can be used for reducing area occupation, by folding it in two delay loops [13], as shown in Fig. 6(a). This way the two pulses do not propagate through two very long delay lines, but instead they cycle within two much shorter delay loops. The cycling is stopped when the HIT_SYNC pulse overtakes the HIT_ASYNC one. The result of conversion is the number of cycles (stored in the counter) necessary for this to happen and the number of cells (stored in the registers) in the last cycle after which this happens. This approach does reduce not just the number of delay cells, but also the number of flip-flops required to store the conversion result as a part of the result is in a much less area-demanding binary scale (content of the counter). Unfortunately, this approach still suffers from non-linearity effects of the statistical mismatches between delay cells. In this work, the two delay loops are furthermore reduced to only one stage, as shown in Fig. 6(b), thus squeezing area occupation and gaining a high benefit in terms of conversion linearity. In fact, area occupation is the lowest as, ideally, only

Fig. 9. Voltage-controlled delay cell used in fine DLLs and fine interpolators. (a) Schematics based on the control of the current used for charging/discharging the node of the MOS diode. (b) Post-layout simulation of delay-voltage characteristics at different temperatures, showing the control voltages needed to lock the propagation delay to the desired values.


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Fig. 11. TDC calibration. The calibration is performed by determining the effective resolutions of START and STOP interpolators and by identifying coarse interpolators bin-widths.

Fig. 10. (a) Microphotograph of the prototype chip fabricated in a standard 0.35 m CMOS technology, containing START and STOP measurement channels and three DLLs used to compensate process, voltage and temperature variations. (b) Layout of the STOP channel containing a SPAD photodetector, the coarse counter and the STOP interpolator, composed of fine and coarse interpolation stages and a synchronizer circuit.

one delay cell per loop is required (practically, since the minimum loop delay constraints must be satisfied, additional cells are necessary), and the result of conversion is completely stored in a binary code, thus further minimizing the number of required flip-flops. Furthermore, as the loops are composed of only one time-resolving cell, the statistical mismatches between two loops does not result in non-linearity of the fine interpolator, but just in gain error (LSB different from nominal one), which can be easily taken into account in post-processing. Low area occupation and high linearity of this approach are paid in terms of a longer conversion time. There are some constraints on durations and of the pulses cycling in the two loops. The constraint on the maximum duration is that it has to be shorter than the total propagation delay of the loop, i.e., the pulse in a certain point of the loop has to go low before its rising edge reaches that point again. The minimum duration of the pulse cycling in the HIT_ASYNC loop is given by the maximum time difference between HIT_ASYNC and HIT_SYNC, that is 625 ps. This is due to the necessity that when HIT_SYNC signal enters the loop the value at the comparison node in the other loop (D input of the flip-flop) has to be still high, otherwise the cycling will be interrupted immediately. On the other hand, the minimum value of is given only by the minimum pulse-width necessary to force the flip-flop to sample the value in the other loop. However,

for symmetry reasons the two pulse-width are sized equal, and taking some margin of safety, their value is chosen to be around 1 ns. The total propagation delay of the two loops is chosen to be around 2 ns. The detailed schematic of the fine interpolator is shown in Fig. 7 and some differences in respect to the basic structure of Fig. 6(b) can be noted. Besides the two delay cells biased by control voltages and that provide the time-resolving capability, other delay cells are present in the loops, all biased at a voltage . They have two roles: to fix the total delay of the loops to about 2 ns and to drive time-resolving cells in the same way as in the fine DLLs. Furthermore, at every cycle two SR flip-flops regenerate the pulse-width to the value of 1 ns, fixed by delay cells present along the path between S and R inputs of the flip-flops. In order to detect the instant when the HIT_SYNC pulse overtakes the HIT_ASYNC one and to interrupt the two loops, we employed an arbiter circuit instead of a flip-flop D. The reason is twofold: faster response and symmetrical loading of the two loops, thus not altering the resolution of the interpolator. Statistical mismatches between the two loops do not cause non-linearity to the fine interpolation conversion characteristic, instead they cause variations of the effective LSB of the interpolator. Even if a 6 bit counter is enough for the nominal LSB (the maximum number of cycles in the loop being 62), we opted for a 7 bit to guarantee correct operation of fine interpolator even if the effective LSB results shorter than 10 ps. E. Fine Interpolator Bias Circuit The role of the fine interpolator is to interpolate the quantization step of the coarse interpolator. To achieve this, the two delay cells that determine the resolution of the fine interpolator

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Fig. 12. Results of time-interval measurements with calibration, for different TDC chips. The effective resolution of the START interpolator varies by a couple of picoseconds around 10 ps, while the STOP interpolator resolution varies by a couple of picoseconds around 25 ps.

tors as it provides more linear delay-voltage characteristic. The designed delay cell exhibits a very linear delay-voltage characteristic, as it can be seen from Fig. 9(b) which shows the post-layout simulation of the fine delay cell characteristic at different temperatures. IV. PROTOTYPE CIRCUIT AND EXPERIMENTAL RESULTS A. Prototype Chip

Fig. 13. Examples of time-interval measurements performed directly with START and STOP fine interpolators. Two fine interpolators perform the conversion of the same time-intervals (200 ps and 700 ps) and the results of conversion with applied calibration are the same.

must show precise propagation delays. Since the delay of a logic cell is heavily influenced by PVT variations, it is not a good design practice to rely on propagation delay at nominal conditions, because such delay could be subjected to high variations, which would eventually impair the resolution of the TDC. Therefore, the delay cells of the fine interpolator are implemented as voltage-controlled delay cells, and the control voltage is provided by two DLLs shown in Fig. 8. The VCDL of the first fine DLL is composed of 31 delay cells, thus setting the propagation delay to ps, while the second fine DLL has 32 cells, thus the propagation delay is ps. The control voltages and that set the propagation delays of the DLL cells feed also the voltage-controlled delay cells of the START and STOP fine interpolators, thus, the time-resolution of the TDC is set to ps. Schematic of the voltage-controlled delay cells of the fine DLLs and interpolators is shown in Fig. 9(a). The delay cell is composed of two inverters whose variable propagation delay is obtained by controlling the current that charges/discharges the node of the MOS diode, with such a current being steered away from the current available to charge/discharge the inverter output node. This implementation was used instead of a conventional solution based on the use of current-starved transis-

The developed TDC has been fabricated in a standard 0.35 m HV CMOS technology. The HV technology was used as it is suitable for fabrication of SPAD photodetectors. Fig. 10(a) shows a microphotograph of the TDC chip. The chip contains one START and one STOP channel and the additional bias circuitry. The START channel is essentially the START interpolator. The bias circuitry is composed of the three DLLs (one coarse and two fine) necessary to stabilize the TDC in respect to PVT variations. The STOP channel, whose layout is shown in Fig. 10(b), contains the STOP interpolator, the coarse counter and also a SPAD photodetector and its associated analog sensing and quenching circuitry. Therefore, as a STOP signal, other than receiving a STOP pulse from outside the chip, it is possible to exploit the pulse provided by the SPAD detector in correspondence to the detection of a photon. The compact 250 m 250 m STOP channel represents the TDC basic building block that has to be replicated for each measurement channel in a multi-channel monolithic TDC chip. On the other hand, the bias circuitry is common to all measurement channels. The same can apply to the START channel: only one START channel is needed in an array of TDC channels if the application requires just one START signal common to all measurement channels, as in many time-resolved applications. B. TDC Data Processing The result of a time interval measurement is given by

(4)


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Fig. 14. Measurements on TDC precision, performed along all TDC dynamic range of 160 ns. Examples of precision measurement histograms are shown at the top measurements of the figure, while the plot shows the standard deviation over the full TDC dynamic range. Standard deviation at each point is computed with taken. The average standard deviation is 17.2 ps.

where

is the 4 bit result of coarse counter measurement, and ns is the period of the reference clock, are the 4 bit results of START and STOP coarse interpolator measurements, and are the 16 1 vectors of START and STOP coarse interpolator values (where is the nth element of the vector with nominal value equal to ps), and are the 7 bit results of START and STOP fine interpolator measurements (with nominal range from 0 to 61) and and are the resolutions of START and STOP fine interpolators (with nominal value of and 10 ps). The numbers are the raw data provided by TDC and has to be processed as in (4) to obtain the result of the time-interval measurement. The unavoidable statistical mismatches among delay cells of the two loops of the fine interpolator and among cells of the two fine interpolators and the two fine DLLs cause the effective resolutions of two interpolators to differ from the nominal value. Furthermore, the mismatches between coarse DLL cells cause the non-linearity of the coarse interpolators. However, it is possible to extract their real values and take them into account (i.e., calibrate the TDC) when processing TDC data. With both START and STOP pulses asynchronous with the reference clock, by measuring a single time interval, the two interpolators use all their dynamic range, therefore the values of and can be determined. This is achieved by identifying the number of fine interpolator codes present for each one of 16 coarse interpolator codes (in nominal conditions for each coarse code there are 62 fine codes present). By summing this numbers we obtain the total number (nominally ) of LSBs in a clock period . Therefore the

Fig. 15. Time-interval measurements performed with power supply varying % while keeping the same calibration. The results from 3.3 V to 3.8 V of conversion are the same in all cases and also the precision is nearly the same thanks to the three DLLs, which make TDC fairly insensitive to PVT variations.

LSB is obtained by dividing the by this number (nominally ps). Furthermore, the bin-widths of coarse interpolator codes are found by multiplying the number of fine codes present for that coarse code by the value of LSB (nominally for each coarse code we have ps). This means that the fine interpolator is able to partially compensate the non-linearity of the coarse interpolator, as the

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Fig. 16. Linearity of the START and STOP interpolators. Thanks to the single-stage Vernier delay loop interpolators the resulting linearity is good. Time-bins with higher DNL are present only at the boundaries between coarse interpolator regions. The DNL rms value for the STOP interpolator is 6.7% LSB, while for the STOP interpolator it is 7% LSB.

coarse bin-widths are “measured” by the fine interpolator. The and are found as the cumu16 values of vectors lative sums of the calculated coarse code bin-widths. The calibration process is illustrated in Fig. 11. It has to be performed once for a chip and it is given by 34 values: two 16 1 vectors and and two values and . Fig. 12 shows the results of calibration of four different TDC chips. As it can be seen, the effective resolution of the START interpolator in all chips varies by a couple of picoseconds around the nominal value of 10 ps, while the resolution of the STOP interpolator is around 25 ps. This is probably due to the fact that the layout of the START interpolator delay cells is oriented as the layout of fine DLLs cells while the layout of the STOP interpolator is mirrored. Therefore, the matching between STOP interpolator delay cells and fine DLLs cells results to be worse as a consequence of mask misalignment and/or gradient variation of process parameters. This issue will be solved simply by orienting also the STOP interpolator as the fine DLLs. C. Measurements The TDC chips are bonded into QFP packages and mounted with sockets to a custom PCB, which is then connected in piggyback to a board with a Xilinx Spartan 3 FPGA. The FPGA controls the TDC, reads the raw data and transfers it to a remote PC via USB interface. A 100 MHz external reference clock is provided to the TDC board. For precision measurements the START and STOP signals where generated by splitting the output of a pulse generator into two coaxial cables of different lengths. All the following measurements are performed with the

TDC chip labeled as Chip 4 in Fig. 12. However, as can be seen also from Fig. 12, all other chips have very similar performances. The prototype TDC is provided also with direct access to fine interpolators, for test purposes. This is used to verify their operation. The two fine interpolators were operated for measuring in parallel the same time-interval. Fig. 13 shows examples of time-interval (around 200 ps and 700 ps) measurements performed directly with the fine interpolators. The fact that the results of conversion are nearly the same is a proof of their correct calibration. Moreover, as signals cycle inside the loops the jitter introduced by the fine interpolators should accumulate, resulting in a lower precision when more cycles are necessary for conversion. However, two different fine interpolators (with different resolutions of 9 ps and 25 ps) measure different time-intervals with nearly the same precision. This indicates that the main limit on TDC precision is to be found outside its core, that is in the signal and clock coupling and I/O pad drivers power supply disturbances. The dynamic range of the TDC is 160 ns. As dynamic range is limited only by the number of bits of the coarse counter, it can be easily extended simply by adding bits to the counter. The dead time is about 150 ns, thus, when measuring time intervals up to its full dynamic range, the maximum sampling rate of the TDC is about 3 Msamples/s. The precision of the TDC was measured along all its 160 ns dynamic range, as shown in Fig. 14. At each point, the standard deviation is computed with measurements of the same time-interval. From Fig. 14, some precision deterioration trend can be seen for increasing time intervals. This is probably due to


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Fig. 17. Linearity measurements of the TDC. By means of uncorrelated START and STOP pulses, uniformly distributed time-intervals were measured on an events per time-bin ( ps), then the histogram of measured time-intervals was build and DNL and INL linearity information was average of % LSB. (b) Integral non-linearity trend with rms value of extracted. (a) Differential non-linearity trend with rms value of 0.88% LSB and peak value less than 9.8 ps.

the degradation of STOP signal edges caused by the long coaxial cables used to delay the START signal and define the time-interval to measure. The TDC average standard deviation over all dynamic range is 17.2 ps. The presence of three DLLs makes the resolution and operation of the TDC core fairly insensitive to PVT variations in the operating range of DLLs. This can be seen, in case of power supply voltage variations, in Fig. 15 where the same time-interval was measured with supply voltages varying from 3.3 V to 3.8 V % and maintaining the same calibration (equal to that of all other measurements). The measurement results in all cases are quite the same, as well as the precision, thus proving the correct operation of DLLs. The differential non-linearity (DNL) of START and STOP interpolators is shown in Fig. 16. This non-linearity is the result of device mismatches and signal couplings within the interpolator circuits, without the effects of the sliding scale. It can be seen that thanks to the single-stage Vernier delay loop interpolators the resulting linearity is good: the DNL is less than 5% in the most part of the range, except at the boundaries between coarse regions, where it arrives at maximum to 50%. Furthermore, the cyclic sliding scale technique significantly reduces the global non-linearity of the converter, thus the TDC exhibits an excellent DNL, as it can be seen from Fig. 17(a). For such a measurement, uncorrelated START and STOP signals were used, many measurements were made, a histogram of measured time-intervals was built and, finally, the linearity information was computed. With an average of events per time-bin, the measured root-mean-square (rms) value of DNL is around ps, while the peak 0.009 LSB rms, i.e., 80 fs rms since value is less than LSB. It should be noted that even if the

linearity of TDC were ideal, with events per time-bin the measured DNL would be around 0.006 LSB rms due to the statistical distribution of time-intervals. The integral non-linearity (INL) is shown in Fig. 17(b). Some disturbances, probably due to signal coupling within I/O pad drivers, deteriorate the INL, ps, with however the INL remains limited mainly between a rms value of 9.8 ps. With power supply of 3.3 V the total consumption of the whole chip is less than 80 mW. Such power consumption is dominated by the three continuously running DLLs (around 50 mW from simulation) and the I/O pad drivers, while the effective consumption of the TDC channel is lower (simulation shows less than 15 mW while operating at 3 Msamples/s). Table I compares the measured performances with those of other recent works presented in literature. The proposed TDC shows a wide dynamic range of 160 ns with a state-of-the-art DNL of just 80 fs rms and 10 ps LSB, notwithstanding the standard cost-effective 0.35 m HV CMOS technology employed. V. CONCLUSION We presented a TDC architecture capable of reaching highprecision together with high-linearity and reduced area occupation per channel. TDC chips were fabricated in a 0.35 m HV CMOS technology and their performances were evaluated. The dynamic range of 160 ns is reached by use of a coarse counter while the high resolution of 10 ps is attained thanks to the exploitation of START and STOP interpolators. Moderate area occupation is reached by use of two stages of interpolation, with the second one based on single-stage Vernier delay loops. Thanks to the high-linearity fine interpolator and to the cyclic sliding scale technique, the proposed TDC reaches

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TABLE I COMPARISON TO PREVIOUS WORK

state-of-the-art DNL of less than 0.9% LSB rms. The precision achieved is 17.2 ps rms. The compact 250 m 250 m TDC channel was designed for being easily assembled side-by-side in order to have a singlechip multi-channel TDC array. Even further, the building block consisting of a TDC channel and a SPAD photodetector represent the state-of-the-art “smart-pixel” for advanced imagers for both fluorescence lifetime imaging (FLIM) and 3-D direct time-of-flight (ToF) measurements. REFERENCES [1] C. Ljuslin, J. Christiansen, A. Marchioro, and O. Klingsheim, “An integrated 16-channel CMOS time to digital converter,” IEEE Trans. Nucl. Sci., vol. 41, no. 4, pp. 1104–1108, Aug. 1994. [2] Y. Arai and M. Ikeno, “A time digitizer CMOS gate-array with a 250 ps time resolution,” IEEE J. Solid-State Circuits, vol. 31, no. 2, pp. 212–220, Feb. 1996. [3] O. Sasaki, T. Taniguchi, T. K. Ohsaka, H. Mori, T. Nonaka, K. Kaminishi, A. Tsukuda, H. Nishimura, M. Takeda, and Y. Kawakami, “1.2 GHz GaAs shift register IC for dead-time-less TDC application,” IEEE Trans. Nucl. Sci., vol. 36, no. 1, pp. 512–516, Feb. 1989. [4] J. P. Jansson, A. Mäntyniemi, and J. Kostamovaara, “A CMOS time-todigital converter with better than 10 ps single-shot precision,” IEEE J. Solid-State Circuits, vol. 41, no. 6, pp. 1286–1296, June 2006. [5] A. Mantyniemi, T. Rahkonen, and J. Kostamovaara, “A CMOS time-to-digital converter (TDC) based on a cyclic time domain successive approximation interpolation method,” IEEE J. Solid-State Circuits, vol. 44, no. 11, pp. 3067–3078, Nov. 2009. [6] E. Raisanen-Ruotsalainen, T. Rahkonen, and J. Kostamovaara, “An integrated time-to-digital converter with 30-ps single-shot precision,” IEEE J. Solid-State Circuits, vol. 35, no. 10, pp. 1507–1510, Oct. 2000. [7] E. Räisänen-Ruotsalainen, T. Rahkonen, and J. Kostamovaara, “A high resolution time-to-digital converter based on time-to-voltage interpolation,” in Proc. IEEE Eur. Solid-State Circuits Conf., 1997, pp. 332–335. [8] B. K. Swann, B. J. Blalock, L. G. Clonts, D. M. Binkley, J. M. Rochelle, E. Breeding, and K. M. Baldwin, “A 100-ps time-resolution CMOS time-to-digital converter for positron emission tomography imaging applications,” IEEE J. Solid-State Circuits, vol. 39, no. 11, pp. 1839–1852, Nov. 2004. [9] A. S. Yousif and J. W. Haslett, “A fine resolution TDC architecture for next generation PET imaging,” IEEE Trans. Nucl. Sci., vol. 54, no. 5, pp. 1574–1582, Oct. 2007. [10] M. A. Abas, G. Russell, and D. J. Kinniment, “Embedded high-resolution delay measurement system using time amplification,” IET Comput. Digit. Tech., vol. 1, no. 2, pp. 77–86, Mar. 2007.

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[26] C. Niclass, C. Favi, T. Kluter, M. Gersbach, and E. Charbon, “A 128 128 single-photon image sensor with column-level 10-bit time-to-digital converter array,” IEEE J. Solid-State Circuits, vol. 43, no. 12, pp. 2977–2989, Dec. 2008. [27] J. P. Jansson, A. Mäntyniemi, and J. Kostamovaara, “Synchronization in a multilevel CMOS time-to-digital converter,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 56, no. 8, pp. 1622–1634, Aug. 2009. [28] M. Lee and A. A. Abidi, “A 9 b, 1.25 ps resolution coarse-fine time-todigital converter in 90 nm CMOS that amplifies a time residue,” IEEE J. Solid-State Circuits, vol. 43, no. 4, pp. 769–777, Apr. 2008. [29] B. Tong, W. Yan, and X. Zhou, “A constant-gain time-amplifier with digital self-calibration,” in Proc. IEEE Int. Conf. ASIC, Oct. 2009, pp. 1133–1136. [30] M. Gersbach, Y. Maruyama, E. Labonne, J. Richardson, R. Walker, L. Grant, R. K. Henderson, F. Borghetti, D. Stoppa, and E. Charbon, “A parallel 32 32 time-to-digital converter array fabricated in a 130 nm imaging CMOS technology,” in Proc. IEEE Eur. Solid-State Device Conf., Sep. 2009, pp. 196–199. [31] J. Richardson, R. Walker, L. Grant, D. Stoppa, F. Borghetti, E. Charbon, M. Gersbach, and R. K. Henderson, “A 32 32 50 ps resolution 10 bit time to digital converter array in 130 nm CMOS for time correlated imaging,” in Proc. IEEE Custom Integr. Circuits Conf., Sep. 2009, pp. 77–80. [32] C. Veerappan, J. Richardson, R. Walker, D.-U. Li, M. W. Fishburn, Y. Maruyama, D. Stoppa, F. Borghetti, M. Gersbach, R. K. Henderson, and E. Charbon, “A 160 128 single-photon image sensor with on-pixel 55 ps 10 b time-to-digital converter,” in Proc. IEEE Int. Solid-State Circuits Conf., 2011, pp. 312–314. [33] S. Cova, M. Ghioni, A. Lacaita, C. Samori, and F. Zappa, “Avalanche photodiodes and quenching circuits for single-photon detection,” Appl. Opt., vol. 35, no. 12, pp. 1956–1976, Apr. 1996. [34] F. Guerrieri, S. Tisa, and F. Zappa, “Two-dimensional SPAD imaging camera for photon counting,” IEEE Photon. J., vol. 2, no. 5, pp. 759–774, Oct. 2010. [35] B. Markovic, S. Tisa, A. Tosi, and F. Zappa, “Smart-pixel for 3D ranging imagers based on single photon avalanche diode and time-to-digital converter,” in Proc. SPIE, 2011, vol. 8033, no. 80330A. [36] R. Walker, J. Richardson, and R. K. Henderson, “A 128 96 pixel -based fully digital 3D camera in 0.13 event-driven phase-domain m CMOS imaging technology,” in Proc. IEEE Int. Solid-State Circuits Conf., 2011, pp. 410–412. [37] V. O’Connor and D. Phillips, Time-Correlated Single Photon Counting. London, U.K.: Academic, 1984. [38] C. Cottini, E. Gatti, and V. Svelto, “A new method for analog to digital conversion,” Nucl. Instr. Meth., vol. 24, p. 241, Aug. 1963. [39] E. Gatti, P. F. Manfredi, and D. Marino, “Analysis and characterization of cyclic-scale compensated analog-to-digital converters,” Nucl. Instrum. Methods, vol. 165, no. 2, pp. 225–230, Oct. 1979. [40] S. Henzler, S. Koeppe, D. Lorenz, W. Kamp, R. Kuenemund, and D. Schmitt-Landsiedel, “A local passive time interpolation concept for variation-tolerant high-resolution time-to-digital conversion,” IEEE J. Solid-State Circuits, vol. 43, no. 7, pp. 1666–1676, Jul. 2008. [41] D. I. Porat, “Review of subnanosecond time-interval measurements,” IEEE Trans. Nucl. Sci., vol. NS-20, pp. 35–51, Oct. 1973.

Bojan Markovic was born in Podgorica, Montenegro, in 1985. He obtained the B.Sc. degree cum laude in electronics engineering at Politecnico di Bari, Italy, in 2007 and the M.Sc. degree cum laude in electronic engineering at Politecnico di Milano, Italy, in December 2009. In 2010 he received the Diploma of Alta Scuola Politecnica. Since January 2010 he has been working toward the Ph.D. degree in the Electronics and Information Department at Politecnico di Milano. His current research activity focus on the design and development of time-to-digital converters for TCSPC systems and arrays of single-photon avalanche photodiodes (SPAD).

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Simone Tisa was born in Milano, Italy, in 1977. He received the M.Sc. degree in electronic engineering from Politecnico di Milano in 2001, and the Ph.D. degree from the same university in 2006. He is now Product R&D Manager for electronics design and system integration at Micro Photon Devices, Bolzano, Italy. In 2008 he pioneered the first monolithic 2-D SPAD imager of 32 32 pixels. His main research interests are in the field of single-photon imaging and single-photon timing of fast phenomena, by means of fully integrated arrays of SPADs and associated microelectronics. Federica A. Villa received the B.Sc. degree in biomedical engineering at Politecnico di Milano, Italy, in 2008. In 2010 she received the M.Sc. degree in electronic engineering at Politecnico di Milano, defending the thesis “Design of an Integrated Circuit for Fast-Gating and Active Quenching of a Single Photon Avalanche Diode (SPAD).” She enrolled in the Ph.D. program in electronic engineering at Politecnico di Milano in 2011. In 2010 she interned in the Biochemistry Dept. of University of California, Los Angeles (UCLA). Her present research activity aims at designing a SPAD array for 3-D imaging with direct time of flight method. Alberto Tosi graduated summa cum laude in electronics engineering in 2001 and he received the Ph.D. degree in information technology engineering in 2005, both at Politecnico di Milano, Italy. Since 2006 he has been Assistant Professor in the Dipartimento di Elettronica e Informazione, Politecnico di Milano. In 2004 he was a summer student at IBM T. J. Watson Research Center, Yorktown Heights, NY, working on the experimental investigation of VLSI CMOS circuits by means of single-photon detectors. His research interests focus on the development of silicon and InGaAs/InP single-photon avalanche diodes (SPAD) and associated electronics for scientific and industrial applications. Currently, he is working on the design and development of both silicon (for the visible range) and InGaAs/InP (for the near-infrared range) SPADs. He is also working on arrays of silicon SPADs (and the associated electronics) for 2-D and 3-D applications and on TCSPC electronics. Franco Zappa (SM’07) was born in Milano, Italy, in 1965. He received the M.S. degree in electronic engineering and the Ph.D. degree in electronic and communication engineering from the Politecnico di Milano in 1989 and 1993, respectively. Since 2011 he has been a full Professor of Electronic Systems in the Department of Electronics and Information Science at Politecnico di Milano. His main research activity deals with the design and the development of microelectronic circuits and single-photon detectors (SPAD) and CMOS SPAD imagers for the visible and near-infrared wavelength range, for high-sensitivity luminescence measurements, 2-D image acquisitions, and 3-D depth ranging. In 1994 he presented and patented the design of the first monolithic active quenching circuit electronics for single-photon detection. He is coauthor of about 120 papers published in International peer-reviewed journals and in proceedings of International conferences, and 5 text books on fundamentals of electronics and electronic systems. Dr. Zappa is Coordinating the European Community funded project “MiSPiA: Microelectronic Single-Photon Imaging Arrays for 3-D Safety and Security applications” in FP7. He has been Coordinator and Research Unit Leader of four National funded projects and three EC funded projects. From 2007 he is a Senior Member in the Electron Devices Society and Lasers & Electro-Optics Society of the IEEE. In 2004 he cofunded Micro Photon Devices S.r.L., a spin-off company of Politecnico di Milano, focused on the production and commercialization of SPAD detection modules for photon-counting and photon-timing single photons (http://www.micro-photon-devices.com).