energies Article
A High-Power-Density Single-Phase Rectifier Based on Three-Level Neutral-Point Clamped Circuits Tao Zhou 1 , Zeliang Shu 1, *, Hongjian Lin 1 , Deng Luo 1 , Yajun Chen 2 and Xiaoxiao Guo 3 1 2 3
*
School of Electrical Engineering, Southwest Jiaotong University, Chengdu 610031, China;
[email protected] (T.Z.);
[email protected] (H.L.);
[email protected] (D.L.) State Grid Suining Power Supply Company, Suining 629000, China;
[email protected] Monolithic Power Systems, Shenzhen 518000, China;
[email protected] Correspondence:
[email protected]; Tel.: +86-1388-0905-750
Academic Editor: Jose Alves da Silva Received: 19 March 2017; Accepted: 9 May 2017; Published: 16 May 2017
Abstract: A single-phase three-level converter is suitable for medium-power applications, with an interface voltage that is higher than that of a traditional two-level configuration. The three-level neutral-point clamped converter is adopted using four switches in each bridge arm, which, compared to a two-level rectifier, leads to less voltage stress, a lower switching frequency, and switching loss on switches. The transient current control strategy is designed to control the active power. The single-phase space vector pulse width modulation (SVPWM) with a voltage balance strategy is designed to solve the neutral point voltage fluctuation problem and keep the dc-link voltage stable. A 1.3 kW high-power-density prototype based on SiC MOSFET was built and tested. The experimental results verified the high performance of steady-state and dynamic responses. Keywords: single-phase rectifier; three-level neutral-point clamped converter; SiC MOSFET; space vector pulse width modulation
1. Introduction Due to the existence of non-linear loads such as uncontrolled rectifiers, the significant harmonics and reactive power will be generated and flow into the grid, which will reduce the grid power quality, influence power distribution, cause incorrect operation, and even damage electric apparatuses. A controlled rectifier can control the dc-link voltage stable at a constant value, and lower harmonics and lower total harmonic distortion (THD) exists on the grid side. A power electronic converter requires a high power density and a low harmonic. Several main topologies are found and designed in the industrial acceptance, and various multilevel converter topologies, including the three-level neutral point clamped converter (3L-NPC), modular multilevel converter, and cascaded H-bridge, are widely used in power applications [1,2]. The modulation of the converter becomes complicated when the output voltage of the converter increases [3,4]. However, the fluctuation of neutral point voltage in the 3L-NPC exists if no voltage balancing measures are taken. To solve the fluctuation, auxiliary circuits for balancing the multilevel converter neutral point voltage have been proposed in [5–7]. Auxiliary circuits can achieve a voltage balance, but additional hardware costs also arise. The authors of [8], to cancel the auxiliary circuits, used a balance strategy adjusting the duty time of the redundant vector to solve the fluctuation problem. Peng et al. [9] proposed a smooth switching technique to solve the fluctuation. Along with the development of semiconductor technology, new Wide Band Gap (WBG) semiconductor devices such as SiC devices have gradually come into view [10–14]. SiC devices enjoy a higher bandgap energy, a higher critical electric field, a higher saturation velocity, and superior thermal conductivity directly in comparison with Si devices, which means SiC devices have lower Energies 2017, 10, 697; doi:10.3390/en10050697
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switching loss and no reverse recovery. Moreover, the great heat dissipation ability of SiC devices can Energies high 2017, 3,voltages 697 2 of 11 withstand and high temperatures [15]. Thus, the volume of the power device can be greatly reduced and the efficiency of the system can be greatly improved. switching loss and no reverse recovery. Moreover, the great heat dissipation ability of SiC devices In the traditional traction power supply system, the grid voltage needs to step down from the can withstand high voltages and high temperatures [15]. Thus, the volume of the power device can traction transformer andefficiency the AC voltage can then rectified. In the cascade power electronic be greatly reducedfirst, and the of the system can bebegreatly improved. transformer, the grid voltage is applied directly to the rectifier. voltage of each In the traditional traction power supply system, thecascade grid voltage needsThe to step downstress from the switching device in two-level topology is larger than in the three-level topology; it is necessary traction transformer first, and the AC voltage can thenthat be rectified. In the cascade power electronic transformer, the grid voltage istoapplied directly decrease to the cascade rectifier. TheFurthermore, voltage stress SiC of each to adapt a three-level topology efficaciously voltage stress. devices switching device in two-level topology is larger than that in the three-level topology; it is necessary can withstand high voltage, so SiC MOSFETs are applied in the single-phase three-level topology, to adapt a three-level to efficaciously decrease voltage stress. Furthermore, SiC devices can and the combination of topology SiC devices and three-level topology can effectively reduce the number of withstand high voltage, so SiC MOSFETs are applied in the single-phase three-level topology, and cascade rectifiers. the combination of SiC devices and three-level topology can effectively reduce the number of cascade According to characteristics of the 3L-NPC and SiC devices, a high-power-density single-phase rectifiers. three-level PWM rectifier based on a SiC MOSFET prototype was designed. This system might work According to characteristics of the 3L-NPC and SiC devices, a high-power-density single-phase in thethree-level unity power factor with relatively high efficiency. This paper introduces circuit configuration PWM rectifier based on a SiC MOSFET prototype was designed. Thisthe system might work and the control algorithm of the three-level singe-phase rectifier. The performances of designed in the unity power factor with relatively high efficiency. This paper introduces thethe circuit rectifier were verified with simulations and experiments. configuration and the control algorithm of the three-level singe-phase rectifier. The performances of the designed rectifier were verified with simulations and experiments.
2. Configuration 2. Configuration
The circuit configuration of the single-phase 3L-NPC rectifier is illustrated in Figure 1. The circuit of theLs, single-phase 3L-NPC is illustrated in Figure 1. It diodes, is It is composed of anconfiguration input inductance SiC MOSFET withrectifier an anti-parallel diode, clamped composed of an input inductance Ls, SiC MOSFET with an anti-parallel diode, clamped diodes, a a second-order harmonic filter module, and loads, and the two legs are defined as Sa and Sb . Vdc1 second-order harmonic filter module, and loads, and the two legs are defined as S and S . and Vdc2 represent the voltage of dc-link capacitors, C1 and C2 , respectively. As is well known, each and represent the voltage of dc-link capacitors, C1 and C2, respectively. As is well known, each 3L-NPC arm can output three-level voltage, then the terminal voltage of an H-bridge circuits can 3L-NPC arm can output three-level voltage, then the terminal voltage of an H-bridge circuits can output five-level waveform asas shown Theterminal terminal voltage is divided sections: output five-level waveform shownininFigure Figure 1b. 1b. The voltage is divided into into four four sections: Section I: Vdc/2 Vdc ; Section < Vdc/2 ; Section III: −V/ dc/2 0; Section Section I: 0 and charged when is < 0, while input has no effect on C2 . Energies 2017, 3, 697 3 of 11 State 5: Switches S12 , S13 , S22 , and S23 are on, while the others are off. The input voltage UAB is zero, and input has no effect on C1 or C2 . and C1 is discharged when is > 0 and charged when is < 0, while input has no effect on C2. StateState 6: Switches S12S,12S, S1313,, SS23 andS23S24 while the others are off. Thevoltage input U voltage UAB is (e) 5: Switches 22, ,and areare on,on, while the others are off. The input AB is zero, VC2 ,and andinput C2 ishas charged when i > 0 and discharged when i < 0, while input has no effect on C1 . no effect on C1s or C2. s (f) 6: Switches S13,, SS21 23,, and 24 are on,on, while the others are off. UAB is VC2 StateState 7: Switches S13S,12S, 14 andSS while the others areThe off.input Thevoltage input voltage U, AB is 22 are and C2,isand charged when > 0discharged and discharged when 0, while input when has noieffect on C 1. −VC1 -VC2 C1 and C2 isare when is >is 0< and charged < 0. s (g) State 7: Switches S13, S14, S21, and S22 are on, while the others are off. The input voltage UAB is State 8: Switches S13 , S14 , S22 , and S23 are on, while the others are off. The input voltage UAB is −VC1-VC2, and C1 and C2 are discharged when is > 0 and charged when is < 0. −V , and C2 is discharged when is > 0 and charged when is < 0, while input has no effect on C1 . (h) C2 State 8: Switches S13, S14, S22, and S23 are on, while the others are off. The input voltage UAB is −VC2, Stateand 9: Switches S13 , S14 , S23i,s and S24charged are on,when whileis the othersinput are off. Theeffect input UAB is C2 is discharged when > 0 and < 0, while has no onvoltage C1. zero, and input has no effect on C or C . 2 while the others are off. The input voltage UAB is zero, (i) State 9: Switches S13, S14, S23, and S124 are on, and input has no effect on C1 or C2.
0,
(a)
(d)
(g)
−
−
/2,
(b)
/2,
,
0,
(e)
(h)
−
(f)
/2,
,
(c)
(i)
/2,
0,
Figure 2. (a–i)The nine switching states of the single-phase three-level rectifier.
Figure 2. (a–i) The nine switching states of the single-phase three-level rectifier.
The definition of P is that the two switches of the bridge arm Si (i = 1, 2)—Si1 and Si2—are on, the definition of O isofthat Si2that and S i3 are on,switches and the definition of N isarm that Si3i (i and Si4 2)—S are on.i1 and Si2 —are on, The definition P is the two of the bridge = 1, The effect ofthat eachSstate on the two capacitor voltages was analyzed based on nine switching the definition of O is and S are on, and the definition of N is that S i2 i3 i3 and Si4 are on. states, and the situation where the grid current > 0 is taken as an example, as in Table 1.states, The effect of each state on the two capacitor voltages was analyzed based on shown nine switching State PO charges Capacitor C1 only while State PO has no effect on Capacitor C2, State OP discharges and the situation where the grid current is > 0 is taken as an example, as shown in Table 1. State PO Capacitor C1 only while State OP has no effect on Capacitor C2, State ON charges Capacitor C2 only charges Capacitor C1 only while State PO has no effect on Capacitor C2 , State OP discharges Capacitor while State ON has no effect on Capacitor C1, and State NO charges Capacitor C2 only while State C1 only while State OP has no effect on Capacitor C , State ON charges Capacitor C only while State NO has no effect on Capacitor C1. All four of these2switching states cause fluctuation 2of the neutral ON has novoltage. effect on State NO chargesinCapacitor C2 only while State NO has no 1 , and point TheCapacitor solution ofCthe fluctuation is discussed the next section.
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effect on Capacitor C1 . All four of these switching states cause fluctuation of the neutral point voltage. The solution of the fluctuation is discussed in the next section. Switch Table Energies1.2017, 3, 697state and effect on two capacitors. ↑: charge; ↓ : discharge; ↔ : no effect; Z: zero vector; 4 of 11 SP: small positive vector; LP: large positive vector; SN: small negative vector; LN: large negative vector. Table 1. Switch state and effect on two capacitors. ↑: charge; ↓: discharge; ↔: no effect; Z: zero vector;State SP: small positive vector;SLP: vector; negative vector; LN: large Sa UAB Vc1SN: small V Vector Categories c2 b large positive negative1vector. P P 0 ↔ ↔ Z 2 3 4 5 6 7 8 9
StateP 1 P 2O 3O 4O 5N 6 7N 8N 9
Vc1
O P P P O O O N N N
PN OP NO PN OP N PO ON N
0Vc1 + Vc2 ↔ −Vc1 ↑ 0 + ↑ Vc2 ↓ − 0 −Vc1 − ↔ Vc2 ↔ − − Vc2 ↓ − 0 ↔ − ↔ 0
↑
↔ Categories Vector ↑ Z ↔ SP ↔ LP ↑ SN ↓ Z SP ↓ LN ↔ SN Z
↑ ↔ ↓ ↔ ↔ ↑ ↔ ↔ ↔ ↓ ↑ ↔ ↓ ↔ ↓ ↔
SP LP SN Z SP LN SN Z
3. Control Algorithm and Modulation 3. Control Algorithm and Modulation
The configuration of the control system is shown in Figure 3a. The transient current control The configuration of the control system is shown in Figure 3a. The transient current control strategy utilizes the grid current is , the input voltage us , the dc-link voltage udc , and the dc-link current strategy utilizes the grid current , the input voltage , the dc-link voltage , and the dc-link idc to current generate the modulation signal U ABsignal . The redundant vector select strategy and SVPWM methods to generate the modulation . The redundant vector select strategy and SVPWM use Umethods of two capacitors to generate switch signals. AB and the use voltages and the voltages of two capacitors to generate switch signals.
(a)
(b) Figure 3. (a) Control algorithm; (b) transient current control strategy.
Figure 3. (a) Control algorithm; (b) transient current control strategy.
3.1. Transient Current Control Strategy
3.1. Transient Current Control Strategy
The transient current control diagram is shown in Figure 3b, where
∗
and
are the
The transient current control is shown u∗dcThe andphase-locked udc are the reference reference and actual value of thediagram dc-link voltage, andin Figure is the 3b, gainwhere constant. loop and actual value of the dc-link voltage, and G is the gain constant. The phase-locked loop (PLL) is a (PLL) is a phase lock procedure, which detects p the phase of input voltage. voltage control utilizes (Proportional phase lockThe procedure, whichpart detects thea standard phase of PI input voltage. Integral) controller to maintain the ∗ dc-link voltage, whichpart should be stable and equal to the reference. When controller − > 0, input the The voltage control utilizes a standard PI (Proportional Integral) tothe maintain ∗ current will increase and input power will raise, as shown in Equation (1), so the change in power dc-link voltage, which should be stable and equal to the reference. When udc − udc > 0, the input required is shown by the output of the PI controller, that is, the given value of Is. current will increase and input power will raise, as shown in Equation (1), so the change in power * * required is shown by the output PI I s*1 = of K pthe (udc − ucontroller, udc −is, udc the )dt given value of Is . dc ) + Ki / T (that (1)
.
Z In order to improve the ∗ dynamic∗characteristics of the PI∗ controller, load current feed-forward Is1 = K p (udc − udc ) + Ki /T (udc − udc )dt. (1) control is adopted as in Equation (2), the effective component of a given current is calculated by the input voltage, the dc-link voltage, and the current. The amplitude of the grid current consists of a In order to improve the dynamic characteristics of the PI controller, load current feed-forward feed-forward controller output of Equation (2) and the PI controller output of Equation (1), where the control is adoptedoutput as in Equation (2), the effective component of a given current is calculated by the feed-forward is
input voltage, the dc-link voltage, and the current. The amplitude of the grid current consists of a I s*2 = (2) udc iand dc / Uthe s . PI controller output of Equation (1), (2)where the feed-forward controller output of Equation feed-forward output is Then, the instantons current reference is accumulated as ∗ Is2 = udc idc /Us . (2)
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Then, the instantons current reference is accumulated as ∗ ∗ Is∗ = Is1 + Is2 .
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(3)
The current control part has a fast response As shown in Equation (4), u AB and u compose I s* = I s*1 +ability. I s*2 (3) L . ∗ the uS , ∆i guarantees that the actual current is tracks the reference current Is in real-time, and the and current control has a fast response output is theThe instruction valuepart of modulation signal ability. u AB . As shown in Equation (4),∗ compose the , Δ guarantees that the actual current tracks the reference current of modulation signal and the output is the instruction value .
in real-time,
u AB = us − u L − ∆i u ABu = u=s −ωL u L −IΔ∗i cos ωt . s s L * ∗ tsin ωt − i ) ω Ls IG = ω= u L ∆i ( I s cos p s s
(4) (4)
* Δi = G p ( I s sin ωt − is ) .
3.2. Space Vector Pulse Width Modulation
Spacethe Vector Pulse Width Modulation To 3.2. choose proper switching states for the 3L-NPC, the single-phase three-level space vector diagram is divided into sections. The twoforvoltage vectors selected three-level to synthesize To choose the four proper switching states the 3L-NPC, theare single-phase spaceVvector re f according diagram divided four sections. The in two voltage are selected to synthesize to the section iniswhich it isinto located. As shown Figure 4a,vectors assuming U AB = MU cos ωt, d the voltage cos , according to the section in which it is located. As shown in Figure 4a, assuming U AB is the projection of the vector Vre f on the α-axis, and the length of the vector Vre f = MUd . the voltage is the projection of the vector on the α-axis, and the length of the vector The vector is rotated counterclockwise at the angular frequency ω, where M in in the range of 0–1 is the . The vector is rotated counterclockwise at the angular frequency ω, where the range of 0– modulation ratio. 1 is the modulation ratio.
(a)
(b)
Figure 4. (a) SVPWM reference voltage; (b) redundant vector selection procedure.
Figure 4. (a) SVPWM reference voltage; (b) redundant vector selection procedure. The reference voltage is synthesized by two adjacent vectors. The vector with fewer levels is as a small vector , and the vector withadjacent a large number of levels definedwith as a big vectorlevels is Thedefined reference voltage is synthesized by two vectors. Theisvector fewer . The two adjacent switching state vectors are selected to calculate on-durations via Equation (5) defined as a small vector Vmin , and the vector with a large number of levels is defined as a big vector under the volt-second balance principle. Vmax . The two adjacent switching state vectors are selected to calculate on-durations via Equation (5) . under the volt-second balance principle. (5)
(of the modulation wave, is the reference voltage is the period of the carrier, U AB TS = V + V.max T2 min T operational time of , is the operational time of1 .
is the
TS = T1 + T2
(5)
−
. wave, TS is the period of the carrier, U AB is the reference voltage of the modulation (6) T1 is the − − operational time of Vmin , T2 is the operational time of Vmax . As shown above in Table 1, ( the large vector zero vector will not cause dc-link capacitor −Vmax ABand T1 = U TS Vmin−aVmax voltage unbalance; however, the small vector causes fluctuation . of neutral point voltage. When the U AB −Vmax T small vector is working, one of the twoTcapacitors or discharged, while the other maintains 2 = TS −isVcharged S min− Vmax the same voltage. The small positive vector PO(ON) and small negative vector OP(NO) have opposite
(6)
As shown above in Table 1, the large vector and zero vector will not cause dc-link capacitor voltage unbalance; however, the small vector causes a fluctuation of neutral point voltage. When the small vector is working, one of the two capacitors is charged or discharged, while the other maintains
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the same voltage. The small positive vector PO(ON) and small negative vector OP(NO) have opposite effects on the neutral point voltage, so the control of the neutral point voltage can be achieved by choosing a redundant vector. To analyze the direction of the current flowing through the capacitor, a strategy for solving the fluctuation of the neutral point voltage by using different redundant vectors is shown in Table 2 and Figure 4b. According to the capacitor voltage and grid current, there are four kinds of redundant switch state selections. When none of the redundant vectors are working and the terminal voltage is 0.5Ud , the strategy can choose between States PO and ON(sp). Similarly, when terminal voltage is −0.5Ud , the strategy can choose between States OP and NO(sn). The result of choosing redundant vectors will be put into a register sp(sn), and the state of the register will be sent to synthesize the switching state finally. When any one of those four redundant vectors is working, the state of register sp(sn) remains unchanged. For example, in Figure 4b, when the system starts to work, Vdc1 > Vdc2 and is > 0; if the terminal voltage is 0.5Ud , then sp will be ON; if the terminal voltage is −0.5Ud , the sn will be OP. Table 2. Redundant vector selection. Terminal Voltage
Relation
Current Direction
Vc1 > Vc2 0.5Ud Vc1 < Vc2 Vc1 > Vc2
−0.5Ud Vc1 < Vc2
Vector Selected →
A→B
ON
Vc1 ↓
PO
Vc2 ↑
PO
Vc1 ↑
ON
Vc2 ↓
OP
Vc1 ↓
NO
Vc2 ↑
NO
Vc1 ↑
OP
Vc2 ↓
→
B→A
→
A→B
→
B→A
→
A→B
→
B→A
→
A→B
→
B→A
Result
4. Simulation In order to verify the system’s control strategy adopted above, a 3L-NPC single-phase rectifier shown in Figure 1 is used to conduct a simulation by MATLAB/SIMULINK in this paper, and the simulation parameters are listed in Table 3. Table 3. System and control parameters. Parameters
Values
Input AC Voltage Input Current Input AC Voltage Frequency Output DC Voltage Output Power Power Density The Inductance of Input Side Filter Circuit Switching Frequency
115 V–264 V 15 A (Max) 47 Hz–63 Hz 400 V 1.3 kW (Max) 0.56 W/cm3 0.4 mH 3 mF/0.84 mH 30 kHz
The dynamic response of the system is shown in Figure 5. when load is on or off, output voltage recovers to 400 V within 0.15 s. Input voltage and current is in the same phase; that is, the power factor of the system is close to 1. The bottom of Figure 5 is the terminal voltage. As mentioned earlier, the voltage of two dc-side capacitances, if not controlled, would be unbalanced, which in turn would increase the harmonic component in the output voltage and increase the voltage applied on the power switch transistor, even damage the device or dc-side capacitor. Figure 6 shows the changes in
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the voltage of the two capacitors. There is no voltage equalizing strategy during the 0–0.3 s period, the maximum value of voltage difference between the two capacitors reached 400 V, and after 0.3 s, the voltage difference Energies 2017, 3, 697 gradually disappeared as a voltage equalizing strategy is adopted.7 of 11 Energies 2017, 3, 697
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Figure 5. DC-link voltage, inputvoltage, voltage, and andand terminal voltage. Figure 5. DC-link voltage, input andcurrent current terminal voltage. Figure 5. DC-link voltage, input voltage, and current and terminal voltage.
Figure 6. The DC capacitors voltages with and without equalization control.
6. The capacitors voltages with with and equalization control. FigureFigure 6. The DC DC capacitors voltages andwithout without equalization control.
5. Experiment Results 5. Experiment Results
5. Experiment Results
5.1. Prototype 5.1. Prototype 5.1. Prototype In order to realize the target mentioned above, which includes a control algorithm and high In order to realize the target mentioned above, which includes a control algorithm and high power density, an experimental prototype of the single-phase three-level rectifier was developed. power density, an experimental prototype ofabove, the single-phase three-level rectifier was developed. In The order to realize theintarget which includes control algorithm and high system is shown Figure mentioned 7. It is divided into three parts. The firsta part consists of two SiC The system is shown in Figure 7. It is divided into three parts. The first part consists of two SiC power density, an experimental prototype of the single-phase three-level rectifier was developed. MOSFET bridge arms and a drive circuit. The drive circuit is designed to drive SiC MOSFET stably. MOSFET bridge arms and a drive circuit. The drive circuit is designed to drive SiC MOSFET stably. The second part consists of an7.input EMIthree filter, aparts. voltageThe sensor andpart a current sensor, The system is shown in Figure It isinductor, dividedaninto first consists of atwo SiC The second part consists of an input inductor, an EMI filter, a voltage sensor and a current sensor, a relay, and a secondary filter. The input inductor is designed to filter the grid voltage harmonic and stably. MOSFET bridge and afilter. drive circuit. The drive circuit is to voltage drive SiC MOSFET relay, and aarms secondary The input inductor is designed to designed filter the grid harmonic and store power. The EMI filter is designed to filter out high frequency noise and interference signals The second consists offilter an input inductor, anout EMI filter, a voltage and a current store part power. The EMI is designed to filter high frequency noise sensor and interference signals sensor, contained in the grid while keeping electromagnetic radiation generated by the system from leaking contained in the gridfilter. whileThe keeping electromagnetic radiation generated system from harmonic leaking a relay, and a secondary input inductor is designed to filter by thethe grid voltage and to the grid. The input voltage ( ), grid current ( ), and dc-link voltage ( ) are detected by sensors to the grid. The input voltage ( ), grid current ( ), and dc-link voltage ( ) are detected by sensors store power. The EMI filter is designed to filter out high frequency noise and interference signals as the feedback. Each state of the system is transformed precisely through the switching of the relay. as the feedback. Each state of the system is transformed precisely through the switching of the relay. contained thepart gridis while keeping radiation generated by the system from leaking Thein third the FPGA controlelectromagnetic board, which is designed to control the whole system. The third part is the FPGA control board, which is designed to control the whole system. havevoltage protection in our program. If the input voltage voltage (uor current by aresensors to the grid. We Thealso input (u methods ), grid current (is ), and dc-link ) grid are detected dor We also have protection smethods in our program. If the input voltage grid current are higher or lower than theofexpected valueis limits, the outputprecisely voltage is not in the setting limits, andof the as the feedback. Each state the system transformed through the switching the relay. higher or lower than the expected value limits, the output voltage is not in the setting limits, and the system would be shut down in case heat issues or hazards occur. The third part would is the be FPGA control board, is hazards designed to control the whole system. system shut down in case heatwhich issues or occur. The configuration of the control system is shown in Figure 3a. All control algorithms are configuration ofmethods the control system is shownIfinthe Figure 3a. All control algorithms are is are Weimplemented alsoThe have protection in our program. us or gridindustry current by Verilog-HDL (Hardware Description Language),input one ofvoltage the universal IEEE implemented bythe Verilog-HDL (Hardware Description Language), oneisofnot the in universal IEEE industry higher or lower than expected value limits, the output voltage the setting limits, standard hardware description languages used to describe digital systems and design hardwareand the standard hardware description languages used to describe digital systems and design hardware system realization would be using shut code down in case heat issues or hazards occur. methods. realization using code methods.
The configuration of the control system is shown in Figure 3a. All control algorithms are implemented by Verilog-HDL (Hardware Description Language), one of the universal IEEE industry
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standard hardware description languages used to describe digital systems and design hardware realizationEnergies using code 2017, 3, 697methods. 8 of 11 Energies 2017, 3, 697
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Figure 7. Prototype of the system.
Figure 7. Prototype of the system. Figure 7. Prototype of the system.
5.2. Experiment Results
5.2. ExperimentInResults Figure 8a, the dc-link voltage ( ), terminal voltage ( ), input voltage ( ), and grid current 5.2. Experiment Results ( ) are illustrated. is stable at(u 400),V,terminal and and are in the same phase, so the rectifier works In Figure 8a, the dc-link voltage voltage (U AB ), input voltage (us ), and grid current dc within unity-power factor limits. ofvoltage presents a input low THD in the full In Figure 8a, the dc-link voltageThe ( waveform ), terminal ( ), voltage ( condition ), and gridofcurrent (is ) are illustrated. u is stable at 400 V,V,and u and is are in thesame same phase, soV.the rectifier works (1.3 kW).dcFigure 8b presents the ripple output voltage, isphase, lower so than Figureworks 8c ( )load are illustrated. is stable at 400 andof stheand are in thewhich the3 rectifier within unity-power factor limits. The waveform of i presents a low THD in the condition of full load exhibits the dc-linkfactor voltage ( ),The input voltage ( ofs), and grid current ) when loadcondition step changes within unity-power limits. waveform presents a low( THD in the of full happen, the recovers to the reference voltage within 0.8 s after the load step changes. Figure 8d (1.3 kW).load Figure 8b presents ripplethe ofripple the output voltage, which is lower than 3 V. Figure (1.3 kW). Figure 8bthe presents of the output voltage, which is lower than 3 V. Figure8c 8cexhibits shows thatdc-link the input voltage ( ),) and grid current ( ),) recover to current sinusoidal immediately exhibits the (voltage input and grid ( waveforms ) when step changeshappen, the dc-link voltage (udc ),voltage input (uvoltage current (is ) when loadload step changes s ), and (grid after the load step changes. these experiments illustrate that the the load system has high dynamic happen, the to voltage theAll reference voltage after step changes. Figure 8d the udc recovers to the recovers reference within 0.8 swithin after 0.8 thes load step changes. Figure 8d shows that responses. shows that the input voltage ( ) and grid current ( ) recover to sinusoidal waveforms immediately the input voltage (us ) and grid current (is ) recover to sinusoidal waveforms immediately after the load after the load step changes. All these experiments illustrate that the system has high dynamic step changes. All these experiments illustrate that the system has high dynamic responses. responses.
(a)
(a)
(c)
(c)
(b)
(b)
(d)
(d)
Figure 8. Experiment results. (a) State–state waveforms; (b) output voltage ripple; (c) dynamic waveforms with and without load; (d) detail waveforms at load step change.
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Energies 2017, 10, Figure 8. 697 Experiment results. (a) State–state waveforms; (b) output voltage ripple; (c) dynamic9 of 11
waveforms with and without load; (d) detail waveforms at load step change.
Figure 9a 9a shows shows the the changes changes in in the the power power factor factor (PF) (PF) and and the the efficiency efficiency when when the the rectifier rectifier works works Figure at two different input voltages (115 V/60 Hz and 230 V/60 Hz). In the first case (115 V/60 Hz), the PF at two different input voltages (115 V/60 Hz and 230 V/60 Hz). In the first case (115 V/60 Hz), the PF reaches 0.995 load increases. The PFPF comes to reaches 0.995 at at the the 30% 30%load. load.Then, Then,the thePF PFincreases increasesgradually graduallyasasthe the load increases. The comes the maximum (nearly 0.999) when the rectifier is under full load. As for the efficiency, the PF starts at to the maximum (nearly 0.999) when the rectifier is under full load. As for the efficiency, the PF starts 94.5% under 30% load, then it declines slightly to the 93.5% with 50% load. After that, the efficiency at 94.5% under 30% load, then it declines slightly to the 93.5% with 50% load. After that, the efficiency keeps relatively relatively steady steady until until the the load load increases increases to to 70%. 70%. However, However, it it falls falls dramatically dramatically as as the the load loadrises. rises. keeps The efficiency achieves the lowest point at the full load. In the second case (230 V/60 Hz), the PF goes The efficiency achieves the lowest point at the full load. In the second case (230 V/60 Hz), the PF goes up from from 0.965 0.965 to to 0.993 0.993 as as the the PF PF of of the the first first case, case, and and the the efficiency efficiency fluctuates fluctuates between between 0.963 0.963 and and 0.972 0.972 up through the process of load changing. Generally, PF increases as the load of the rectifier increases and through the process of load changing. Generally, PF increases as the load of the rectifier increases and the PF retains a high value. The efficiency ranges from 0.92 to 0.972, which indicates the efficiency has the PF retains a high value. The efficiency ranges from 0.92 to 0.972, which indicates the efficiency no strong correspondence withwith the load changes. has no strong correspondence the load changes. The experiment test has been done under and the result is shown in The experiment test has been done underthe thesame samepower powerlevel level(1.3 (1.3kW), kW), and the result is shown Figure 9b. The PF drops from 0.999 to 0.99 when the input voltage increases from 115 V to 264 V, which in Figure 9b. The PF drops from 0.999 to 0.99 when the input voltage increases from 115 V to 264 V, coincides with Figure As the9a. input gains,voltage the input current correspondingly. which coincides with9a.Figure As voltage the input gains, the decreases input current decreases As for the THD, the PF starts at 1.7% with a 115 V input voltage. Then, it drops drastically to 1.4% when correspondingly. As for the THD, the PF starts at 1.7% with a 115 V input voltage. Then, it drops the input voltage 120 V.the Afterwards, the THD to 2.7%the when theincreases input voltage increases to drastically to 1.4%iswhen input voltage is 120increases V. Afterwards, THD to 2.7% when the 264 V. In terms of the efficiency, the PF begins at 0.92, and then improves sharply to 0.965 when the input voltage increases to 264 V. In terms of the efficiency, the PF begins at 0.92, and then improves input voltage reaches 200input V. After the light rolling of After the efficiency 240 V,between a slight sharply to 0.965 when the voltage reaches 200 V. the light between rolling of200 the and efficiency dropand appears V input voltage. at 264 V input voltage. 200 240 V,ata 264 slight drop appears Moreover, a comparison experimentbetween between the device device is developed, Moreover, a comparison experiment the Si Si device andand the the SiC SiC device is developed, and andoperation the operation frequency of Si IGBT is 3while kHz, the while the operation frequency of SiC MOSFET is the frequency of Si IGBT is 3 kHz, operation frequency of SiC MOSFET is 30 kHz. 30 kHz. The experiment result is shown in Figure 9c,d. The ITHD of the SiC system is lower than the Si The experiment result is shown in Figure 9c,d. The ITHD of the SiC system is lower than the Si system system at theinput samevoltage input voltage with an increased switching frequency, PFthe of the system at the same with an increased switching frequency, and and the the PF of SiCSiC system is is higher than that system and almost close 1 in different input voltage conditions. higher than that of of thethe Si Si system and almost close to to 1 in different input voltage conditions. The experiments experiments and and the the test test above above verify verify that that the the SiC SiC MOSFET MOSFET single-phase single-phase three three level level rectifier rectifier The can work with a high efficiency, a low THD, and a unity power factor. can work with a high efficiency, a low THD, and a unity power factor.
(a)
(b)
Figure 9. Cont.
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(c)
(d)
Figure 9. Experimental statistics: (a) power factor and efficiency; (b) THD, power factor, and efficiency Figure 9. Experimental statistics: (a) power factor and efficiency; (b) THD, power factor, and efficiency with 100% load; (c) THD comparison between Si and SiC devices; (d) PF comparison between Si and with 100% load; (c) THD comparison between Si and SiC devices; (d) PF comparison between Si and SiC devices. SiC devices.
6. Conclusions 6. Conclusions A high-power-density single-phase 3L-NPC rectifier was built. Its size is shown in Figure 7, and A high-power-density single-phase 3L-NPC rectifier was built. Its size is shown in Figure 7, the power density is relatively high. Through the adoption of a transient current control strategy, the and the power density is relatively high. Through the adoption of a transient current control strategy, SVPWM method, and a redundant vector selection strategy, the goal of a stable dc-link voltage, a the SVPWM method, and a redundant vector selection strategy, the goal of a stable dc-link voltage, high power factor, a low THD, and a relatively high efficiency is achieved. The dynamic a high power factor, a low THD, and a relatively high efficiency is achieved. The dynamic characteristics characteristics of the system were tested, and the system was found to have a high dynamic response. of the system were tested, and the system was found to have a high dynamic response. The grid The grid voltage and current quickly adjust to recover sinusoidal waveforms. The superior voltage and current quickly adjust to recover sinusoidal waveforms. The superior advantages of SiC advantages of SiC MOSFET in breakdown voltage, heat conductivity, and high temperature MOSFET in breakdown voltage, heat conductivity, and high temperature compared to Si MOSFET are compared to Si MOSFET are reflected in the high efficiency of the 3L-NPC rectifier built here. reflected in the high efficiency of the 3L-NPC rectifier built here. Acknowledgments: This Acknowledgments: This work work was was supported supported by by the the National National Natural Natural Science Science Foundation Foundation of of China China (Grant (Grant Nos. Nos. 51377004 and 51477144). 51477144). 51377004 and Zhou and Zeliang Shu designed the control algorithm, the controller, and the main Author Contributions: Tao Zhou circuits; Tao Deng Luo,Luo, Xiaoxiao Guo, Guo, and Yajun the prototype and achieved theachieved experiments; circuits; TaoZhou, Zhou, Deng Xiaoxiao and Chen Yajundesigned Chen designed the prototype and the Hongjian Lin Hongjian analyzed Lin the data. experiments; analyzed the data. Conflicts of Interest: The authors declare no conflict of interest. Conflicts of Interest: The authors declare no conflict of interest.
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