A highefficiency realtime digital signal averager ... - Wiley Online Library

Research Article Received: 18 August 2012

Revised: 9 January 2013

Accepted: 18 February 2013

Published online in Wiley Online Library

Rapid Commun. Mass Spectrom. 2013, 27, 1155–1167 (wileyonlinelibrary.com) DOI: 10.1002/rcm.6553

A high-efficiency real-time digital signal averager for time-of-flight mass spectrometry Yinan Wang1, Hui Xu1, Qingjiang Li1, Nan Li1, Zhengxu Huang2, Zhen Zhou2,5*, Husheng Liu1, Zhaolin Sun1, Xin Xu1, Hongqi Yu1, Haijun Liu1, David D.-U. Li3, Xi Wang1, Xiuzhen Dong4 and Wei Gao2* 1

School of Electronic Science and Engineering, National University of Defense Technology, Changsha, Hunan 410073, China School of Environmental and Chemical Engineering, Shanghai University, Shanghai 200444, China 3 School of Engineering and Informatics, University of Sussex, Brighton BN1 9QT, UK 4 Department of Bioengineering, Fourth Military Medical University, Xi’an, Shaanxi 710032, China 5 Hexin Analytical Instrument Co., Ltd., Guangzhou, Guangdong 510535, China 2

RATIONALE: Analog-to-digital converter (ADC)-based acquisition systems are widely applied in time-of-flight mass spectrometers (TOFMS) due to their ability to record the signal intensity of all ions within the same pulse. However, the acquisition system raises the requirement for data throughput, along with increasing the conversion rate and resolution of the ADC. It is therefore of considerable interest to develop a high-performance real-time acquisition system, which can relieve the limitation of data throughput. METHODS: We present in this work a high-efficiency real-time digital signal averager, consisting of a signal conditioner, a data conversion module and a signal processing module. Two optimization strategies are implemented using field programmable gate arrays (FPGAs) to enhance the efficiency of the real-time processing. A pipeline procedure is used to reduce the time consumption of the accumulation strategy. To realize continuous data transfer, a high-efficiency transmission strategy is developed, based on a ping-pong procedure. RESULTS: The digital signal averager features good responsiveness, analog bandwidth and dynamic performance. The optimal effective number of bits reaches 6.7 bits. For a 32 ms record length, the averager can realize 100% efficiency with an extraction frequency below 31.23 kHz by modifying the number of accumulation steps. In unit time, the averager yields superior signal-to-noise ratio (SNR) compared with data accumulation in a computer. CONCLUSIONS: The digital signal averager is combined with a vacuum ultraviolet single-photon ionization time-offlight mass spectrometer (VUV-SPI-TOFMS). The efficiency of the real-time processing is tested by analyzing the volatile organic compounds (VOCs) from ordinary printed materials. In these experiments, 22 kinds of compounds are detected, and the dynamic range exceeds 3 orders of magnitude. Copyright © 2013 John Wiley & Sons, Ltd.

The time-of-flight mass spectrometer (TOFMS) is an instrument in which an ion’s mass-to-charge ratio and other properties can be determined using the flight time measurements.[1] A TOFMS generally consists of an ion source, a mass analyzer, an ion detector, a data acquisition system and an analytical system.[2] Due to its advantages in sensitivity, resolution and time consumption for analysis, the TOFMS is widely applied as a particle discriminator in the fields of atom probing, geological surveying, chemical analysis, vacuum technology and environmental monitoring.[3–6] The high-speed ion detection equipment in a TOFMS consists of a data acquisition system that records the electrical signals, which carry the information regarding molecular

Rapid Commun. Mass Spectrom. 2013, 27, 1155–1167

Copyright © 2013 John Wiley & Sons, Ltd.

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* Correspondence to: Z. Zhou or W. Gao, Institute of Environmental Pollution & Health, Shanghai University, 99 Shangda Road, Shanghai 200444, China. E-mail: [email protected]; [email protected]

weight. A common approach for quantification is ion pulse counting, where a time-to-digital converter (TDC) is adopted to acquire the arrival time of the ions.[7,8] However, TDCs can only record the arrival time, not the envelope curve or the intensity of simultaneous pulses. Thus, TDCs are only quantitative in low concentration conditions, where the ion signal intensity is less than 1 ion per extraction.[9,10] However, by introducing an analog-to-digital converter (ADC) to the TOFMS method, not merely the time of arrival, but also the envelope of the pulse, can be measured.[11,12] The ADC-based data acquisition system has a wider dynamic range than the TDC-based system, allowing it to cope with abundant simultaneous ions.[13] Data acquisition systems, with sampling rates of GSample/s, have been presented in various applications of the TOFMS.[14–17] The required bandwidth for data transfer increases rapidly with the resolution and the sampling rate of the ADC. For instance, if an 8 bit 2 GSample/s ADC is used as the data conversion component, the data throughput will reach at least 2 GByte/s. To relieve the pressure of data throughput,

Y. Wang et al. high-speed interfaces have been introduced, resulting in realistic data transfer per TOF extraction. Li et al.[18] have described a high-speed data acquisition, distribution and storage system. High-throughput interfaces, such as optical fibers and peripheral component interconnect (PCI) express, are adopted to achieve 3 GByte/s transfer bandwidth. However, this technique requires four parallel distribution and storage systems, which makes it difficult and time-consuming to synthesize and play back the original spectral data. Bajo et al.[19] designed a high-speed data-streaming system, where a high data transfer rate (up to 1 GByte/s) is achieved by using the PCI express for real-time data acquisition. This system requires a high-performance dedicated processing platform and large storage capacity. Using another approach, data compression algorithms have been introduced to reduce the quantity of data. Related research mainly deals with high-speed lossless compression for the computer, which, however, cannot reduce the data throughput over the transfer interface.[20–22] Drewnick et al. presented a compression algorithm based on a field programmable gate array (FPGA), which could compress the spectra to unit m/z resolution.[15] This lossy compression algorithm can reduce the quantity of data transferred to the computer memory. Agilent has developed an 8 bit, 2 GSample/s, data acquisition card (AP240), which can realize on-board averaging with the specified firmware and supply a maximum transfer rate of 100 MByte/s by using a PCI interface. In this paper, we present a high efficiency real-time digital signal averager that presents a compromise between performance and complexity. In the digital signal averager, we implement a high-performance signal conditioner, where analog bandwidth, impulse responsiveness and dynamic characteristics are considered, according to the principle of the operation of the TOFMS. The digital signal averager can record a set of repetitive extractions and accumulate the periodic measurement results via the internal memory. With a view to capturing short-time ion signals, which may be present in only a few extractions, efforts are made to improve the efficiency of real-time processing. Therefore, two optimization strategies are implemented, based on FPGA, to enhance the efficiency of data processing, and high efficiency continuous data transfer is achieved. The digital signal averager can perform significant signal-to-noise ratio (SNR) improvement over accumulation in the computer, per unit time. By using a FPGA threshold, the averager can maintain linearity over a

broad dynamic range, especially in the low concentration regimes. Despite this, the PCI (1056 Mbit/s, with 32 bit data width and 33 MHz data rate) and PCI express (2.5 Gbit/s, with 1 lane) can provide higher transfer rates than a universal serial bus (USB) 2.0 (480 Mbit/s). We use the USB 2.0 interface instead of PCI or PCI express, so that the averager can work with an ordinary laptop computer and save cost. The proposed digital signal averager can achieve excellent real-time capability with a low-speed USB 2.0 interface. Thus, the averager features comparable dynamic performance and real-time capability as the AP240. Furthermore, by using a USB interface, the averager is more versatile and has lower cost than the AP240.

HARDWARE PLATFORM General framework As shown in Fig. 1, the digital signal averager is composed of a data acquisition module, a signal processing module, a trigger conditioner, a USB controller and two signal conditioners. In this section, the signal conditioner and the data acquisition module are described in detail. The design of the signal processing module will be introduced in the next section. The brief workflow of the digital signal averager is as follows. First of all, ion pulses and trigger pulses are modulated by the signal conditioner and the trigger conditioner, respectively, to meet the back-end ADC’s requirement. Then, the acquisition module, driven by a high-speed sampling clock, digitizes ion pulses into binary codes. The acquisition results are sent to the signal processing module. The ultimate records are not transferred by the USB controller until accumulation reaches a pre-set value. Finally, a computer is used to reveal and analyze the spectra. Signal conditioner As depicted in Fig. 2, the signal conditioner can be divided into five parts: a programmable step attenuator, an adder circuit, a fully differential driver, an operational amplifier and a digital-to-analog converter (DAC). The conditioner is used for matched receiving, gain controlling and offset adjustment. The output of the ion detector contains some intense signals, which may exceed the maximum range of the ADC, or even damage the device.[24] In view of this, we use

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Figure 1. General schematic of the digital signal averager.

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High-efficiency real-time digital signal averager for TOFMS aperture jitter (tj) exists in the sampling clock due to various factors (e.g., crosstalk, Johnson noise, unmatched impedance and power line variations). The aperture jitter introduces a random deviation between the practical and theoretical sampling time. This means that there is an extra difference between the quantized value and the signal level. A concise analysis follows. Firstly, suppose there is a sinusoidal input signal (S(t)) with frequency f, as given by: SðtÞ ¼ A sinð2pftÞ

Figure 2. Functional diagram of the signal conditioner.

(1)

The maximum error (Ve) occurs when the derivative of S(t) reaches its maximum value, which can be expressed by: a programmable step attenuator to regulate the amplitude of the input pulses and avoid saturating the back-end ADC’s range. A radio-frequency (RF) digital step attenuator, DAT-31R5-PP (Mini-Circuits Inc.), is introduced to provide a 50 ohm matching impedance and an attenuation ranging from 0 dB to 31.5 dB in 0.5 dB steps. The attenuator can be modified through a parallel interface driven by the signal processing module. Since the ion pulses are located at zero bias, only half of the ADC’s dynamic range can be utilized without adjusting the offset. With an 8 bit ADC for example, the theoretical effective number of bits (ENOB) for zero bias signals is no more than 7. For this reason, an adder circuit is used to change the direct current (DC) offset to a suitable level.[25] The MAX5535 (Maxim Inc.), which is controlled by the signal processing module, is used to provide a suitable DC bias. Also, the LM321 (Texas Instruments Inc.) is adopted, in order to enhance the driving capability of the MAX5535. A low distortion differential driver, LMH6555 (Texas Instruments Inc.), is selected to improve the capability of capturing weak signals. It features a fixed gain of 13.5 dB; therefore, the signal conditioner gives an adjustable gain from 18 dB to 13.5 dB in 0.5 dB steps. The low-voltage noise density allows the LMH6555 to operate with fine SNR and spurious free dynamic range (SFDR). Another function of the LMH6555 is to convert the single-ended port into differential, which enhances the common-mode rejection ratio and the even-order harmonic rejection ratio. Data acquisition module


(2)

Consider an ideal ADC, where the step size and quantization error can be ignored. In this case, the SNR can be expressed approximately by[29]: SNR ¼ 20 log

SðtÞMAX ¼ 20 log 2pf tj Ve

(3)

where S(t)MAX is the maximal value of the input signal. Clearly, if the aperture jitter becomes larger, the SNR becomes worse. In order to avoid coding errors in the sampling results, the maximum error caused by aperture jitter should be less than 1/2 the value of the least significant bit (LSB). This is given by: Ve ¼ A2pf tj ≤

LSB A ¼ RADC 2 2

(4)

where RADC represents the resolution of the ADC. Considering this requirement, the maximum aperture jitter can be calculated as: tj ≤

1 pf 2RADC þ1

(5)

In our system, the ADC features 8 bit resolution (RADC = 8), and the bandwidth reaches 500 MHz (f = 500 MHz). Following Eqn. (5), the upper limit of the aperture jitter can be calculated as 1.24 ps. Therefore, the AD9517 (Analog Devices Inc.) is chosen to generate the high-precision sampling clock. The additive aperture jitter is only 225 fs, which satisfies the system’s requirements. The sampling clock is driven using differential low-voltage positive emitter coupled logic (LVPECL) level, which has superior performance in a noisy circuit.

FPGA-BASED SIGNAL PROCESSING General framework The signal processing module consists of a transfer mode converter, a threshold unit, a data cache unit, an accumulation unit, a data storage unit, a USB dispatch unit, a clock management unit and a trigger monitoring unit. The architecture of the signal processing module is shown in Fig. 3. In our design, a Virtex-4 FPGA, XC4VSX35, constitutes the platform of the signal processing module, in which the



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The data acquisition module is a significant element in the digital signal averager and has a vital influence on the system performance and stability.[26] In order to achieve 500 ps time resolution and adequate dynamic range, the ADC08D1000 (Texas Instruments Inc.) is used. It consists of two 1 GSample/s ADCs with 8 bit resolution which can alternately take samples from the two input signals to combine as a single 2 GSample/s ADC. Self-calibration is involved in the integrated complementary metal oxide semiconductor (CMOS) chip, so that the mismatch errors between the two channels can be minimized in time-interleaved mode. Each convertor possesses one 1:2 demultiplexer, which fans out to two 8 bit low-voltage differential signaling (LVDS) buses, to halve the output data rate. The sampling clock performs an important action in the data acquisition module and any high-speed ADC is extremely sensitive to the quality of its sampling clock.[27,28] However,

Ve ¼ A2pf tj

Y. Wang et al.

Figure 3. Architecture of the FPGA-based signal processing module. The red arrows indicate the data flow with the threshold unit open. functions are implemented via the fast reconfigurable elements and cascadable embedded digital signal processing (DSP) slices. The sampling results of the ADC08D1000 include four groups of 8 bit parallel data (DI, DQ, DID and DQD) and a synchronized clock (DCLK). Double data rate (DDR) mode is selected to reduce the rate of DCLK. Thus, the digitized data is presented at the rising and failing edge of the synchronized clock. The data flow for the signal processing is introduced as follows. First of all, the transfer mode converter transforms the DDR differential signals into single-ended signals with a single data rate (SDR). When the trigger monitoring unit detects a valid trigger, the data cache unit is activated to receive the sampling results. If the threshold unit is opened, the sampling results are compared with a user-defined threshold. Only digitized data with a value greater than the threshold is recorded by the data cache unit. If the threshold unit is closed, all the sampling results are recorded by the data cache unit. Then, depending on the record length and the accumulation number, the accumulation unit adds the cached data and saves the temporary results in the data storage unit. Finally, the USB dispatch unit transmits the completed accumulation result from the data storage unit to the USB controller. The XC4VSX35 consists of 15360 slices, 30720 look-up tables and 432 kBytes RAM. About 16% of the look-up tables and 17% of slices are consumed in this averager. In order to enlarge the storage depth, all the RAM resources are used up. For the processing of the first sample in FGPA, this results in an 80 ns delay from caching to being ready for uploading. A sustained data stream can be obtained because of the adoption of the pipeline strategy. Optimization strategy of efficiency

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In order to enhance the efficiency of real-time processing, two optimization strategies are implemented, based on FPGA. The accumulation strategy leads to data compression, so that the massive quantity of data generated by the ADC can be compressed into a sustainable value. Furthermore, the pipeline procedure is used to modify the time consumption of the accumulation. This transmission strategy is used in


order to achieve seamless transfer. By employing the block random access memory (RAM) on FPGA, the ping-pong procedure is used to raise the efficiency of the real-time processing. Consequently, this strategy allows the accumulation and the transmission to be executed simultaneously. The detailed design scheme and performance analysis are presented below. Accumulation strategy Accumulating the spectra in FPGA memory can reduce the requirement of transfer bandwidth between the acquisition system and the PC, due to the resulting data compression. In this paper, the digital signal averager performs with 8 bit resolution, and the 8 bit data width is extended to 24 bits for accumulation. Therefore, the maximal accumulation number reaches 65,535. For one sample, the quantity of data is compressed into 3 Bytes after 65,535 accumulations. However, without accumulation, about 64 kBytes of data needs to be transferred to the PC. As shown in Fig. 4, the accumulation unit consists of an adder and an extra buffer, which cooperate with a block RAM. For one sample, the accumulation procedure, which is composed of two steps (read-add and write-back), consumes two operation cycles. In the first step, as the red lines show in Fig. 4, the accumulation unit reads the current summation of sample N from port B, and adds it to the new sample N in the data cache unit. The renewed summation is stored briefly in the extra buffer. At the same time, the address pointer of port B, RAM_B_Addr, shifts to the next sample space. In the second operation cycle, the new summation is written back to the block RAM through port A. Subsequently, RAM_A_Addr shifts onto the next sample space, as do the rest of the samples, until one circulation from sample 0 to sample M is finished. The accumulation then continues until the finished circulations reach the pre-configured accumulation number. In fact, by using the pipeline method, the renewed summation of sample N-1 is being pushed into the block RAM, as shown by the green lines, while sample N is executing the read-add operation. The pipeline procedure greatly increases the system’s throughput capability. If there are a total of M samples queuing for accumulation, 2M



High-efficiency real-time digital signal averager for TOFMS

Figure 4. Accumulation procedure. The block RAM X represents either of the two RAMs. Each RAM possesses two data ports, where port A is the input data path and port B is the output data path. operation cycles are required using the sequential mode. However, all accumulation can be finished within M + 1 operation cycles with the pipeline method. When M is much greater than 1, this means that the two operation steps for one sample can be realized in approximately one cycle. Transmission strategy As shown in Fig. 5, under the management of the operation controller, two block RAMs alternately take possession of the data path to the USB dispatch unit. Block RAM 1 and the accumulation unit cooperate to perform the accumulation of frame i, meanwhile block RAM 2 holds the USB dispatch unit for the transmission of frame i–1. When both of these operations are completed, the data paths switch over. The adoption of ping-pong strategy allows the accumulation and the transmission to be executed simultaneously. It avoids the long dead times that would be suffered if only one memory

was used, needing to wait for the entire frame to be transferred to the PC before receiving the next. If the transmission of the previous frame is achieved before the accumulation of the current frame, the averager’s dead time is the time of interface switching between the two RAMs. Due to the adoption of FPGA’s internal RAMs, the switching operation can be accomplished within 16 ns, which is much shorter than the record length. However, if the transmission is finished later than the accumulation, new extractions cannot be recorded until the transmission is finished. Thus, an extra waiting time will be introduced although this can be eliminated by adjusting the accumulation number and the record length. Efficiency and SNR improvement analysis The efficiency of the digital signal averager (E) can be defined as the ratio of the number of recorded extractions to the number of total input extractions in unit time. To help




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Figure 5. Transmission procedure. The blue solid lines represent the current data access, while the red dotted lines indicate the alternative data access. We omit the connections between port B of the block RAMs and the accumulation unit, which are described clearly in the accumulation strategy section.

Y. Wang et al. understand the derivation of the efficiency, the accumulation and the transmission are regarded as two processing threads, which can be executed simultaneously. In this discussion, we neglect the switching time between the two RAMs, which is much shorter than the record length. The extra overhead time in transferring one frame from the averager to the computer disk is not included. However, the effect of the extra overhead time will be discussed in the experiments. FTrig and TTrig denote the frequency and period of the extraction trigger, respectively. STrans denotes the sustained rate of data transfer from the digital signal averager to the storage disk, NumAcc is the configured number of accumulations for one frame, LRec is the record length for each trigger, FSamp represents the sampling frequency of the ADC and RADC denotes the resolution of the ADC. WRa denotes the extension ratio of the data width for accumulation. For instance, if the data width of an 8 bit ADC is extended to 24 bits in FPGA, the WRa is 3. To facilitate the data processing in FPGA, WRa does not change with NumAcc. TTrans represents the transfer time of one frame, and TAcc denotes the accumulation time of one frame. As shown in Fig. 6, two regimes are presented, depending on the relationship between TTrans and TAcc. In the first regime, TTrans is less than or equal to TAcc. If the uploading

of one frame is accomplished earlier than the accumulation, there will be a period of idle time for the transmission thread. If TTrans is equal to TAcc, the idle time will disappear. In either case, for regime 1, all the input extractions can be recorded and uploaded. Thus the efficiency of the digital signal averager reaches 100%. In the second regime, TTrans is greater than TAcc. Because the uploading of one frame needs more time than the accumulation, an idle time emerges between the two frames in the accumulation thread. During the idle time, the digital signal averager is unable to record the input extractions. In regime 2, not all the input extractions are recorded and uploaded. It can be deduced that the ratio of the number of recorded extractions to the number of total input extractions is equivalent to the ratio of TAcc to TTrans. Consequently, the efficiency, in regime 2, can be calculated using: E¼

TAcc TTrans

(6)

The accumulating time of one frame (TAcc) is the product of the period of the extraction trigger (TTrig) and the number of accumulations (NumAcc) for one frame:

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Figure 6. Data processing of two regimes. The red extractions are missed by the averager, and the blue ones are recorded. The dashed arrows indicate the changing of operation mode for the block RAMs.




High-efficiency real-time digital signal averager for TOFMS TAcc ¼ NumAcc TTrig

(7)

The transfer time of one frame (TTrans) is the ratio of the data size of one frame to the sustained rate of data transfer (STrans): TTrans ¼

FSamp LRec WRa RADC STrans

(8)

Inserting Eqns. (7) and (8) into (6), the efficiency is given from: E ¼ aNumAcc

(9)

where a is calculated by: a¼

TTrig STrans FSamp LRec WRa RADC

pffiffiffiffi ¼ K SNRU

(11)

Acc

SNRðNumAccÞ


(12)

(13)

MAX

sffiffiffiffiffiffiffiffiffiffiffi 1 ¼ aWRa

(14)

For this averager, the WRa is 3. This means that accumulating in the averager will be more efficient than accumulating in the computer when NumAcc is configured greater than 3.

SYSTEM EVALUATION In this section, comprehensive tests and performance analysis are presented, including the performance of the signal conditioner, the data acquisition module, the processing efficiency, the SNR improvement over accumulation in the computer and the dynamic range with a threshold. For further demonstration of the performance, the averager is used with a vacuum ultraviolet single-photon ionization time-of-flight mass spectrometer (VUV-SPI-TOFMS) provided by Hexin Analytical Instrument Co., Ltd., for on-line analysis of volatile organic compounds (VOCs) from printed materials. Performance of signal conditioner The width of ion pulses varies from a few nanoseconds to tens of nanoseconds, and the amplitude varies from a few millivolts to several volts. To examine these characteristics, targeted experiments have been performed to study parameters, including analog bandwidth, responsiveness and dynamic performance. The frequency spectrum of ion pulses covers a broad bandwidth. If the conditioner cannot satisfy the bandwidth requirement, the width of the ion pulses will be extended and the amplitude will be weakened. In this test, standard sinusoidal signals, varying from 10 kHz to 1 GHz with 1 Vpp amplitude, are generated to provide the input to the signal conditioner. An arbitrary generator, AFG3102 (Tektronix Inc.), was used for the signal frequencies less than 100 MHz, and sinusoidal signals from 100 MHz to 1 GHz were generated using a vector signal generator, SMBV100A (Rohde&Schwarz Inc.). The output of the signal conditioner is captured by a digital phosphor oscilloscope (DPO4104, Tektronix Inc.). As shown in Fig. 7(a), the 3 dB bandwidth of the signal conditioner reaches 1 GHz with different gain configurations, which is sufficient to maintain the integrity of ion pulses. For the 12 dB condition, the swing is 2.97 dB within the



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pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi EPC Acc FTrig SNRU pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ¼ EðNumAccÞ FTrig SNRU

¼

sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi NumAcc WRa

According to Eqn. (13), only when NumAcc is greater than WRa, does accumulating in the averager show improvement over accumulating in the computer. In all other cases, accumulating in the averager gives lower efficiency. When the efficiency of the digital signal averager is 100%, SNRImp reaches its upper limit (SNRImp_MAX), which can be calculated from: SNRImp

Signal accumulation can optimize the SNR performance by pffiffiffiffi a factor K.[30,31] In order to compare the SNR performance resulting from accumulating in the averager with accumulating in the computer, we need to calculate the number of recorded extractions per unit time in both cases. Firstly, accumulating in the computer memory can be regarded as a special case of accumulating in the averager, as given by Eqns. (9) and (10), with NumAcc = 1 and WRa = 1. These values can be used to calculate the efficiency of accumulating in the computer memory (EPC_Acc). E(NumAcc) denotes the efficiency of accumulating in the averager with different values of NumAcc. Thus, for both cases, the achievable SNR in unit time can be given by: SNRPC

SNRImp

SNRðNumAccÞ ¼ ¼ SNRPC Acc

(10)

For this digital signal averager, FSamp, RADC and WRa are constants. STrans depends on the transfer interface and the performance of the back-end computer. For a particular computer and transfer interface, STrans can be regarded as a constant. If TTrig and LRec are fixed, a can be considered as a constant coefficient. According to Eqn. (9), when NumAcc increases to 1/a, the value of E is 100%, i.e., we can increase TAcc by adjusting NumAcc to make it greater than TTrans. Thus increasing NumAcc can lead to regime 1 from regime 2. In practice, NumAcc must be a positive integer. If a is greater than 1, 100% efficiency can be reached with NumAcc = 1. In this work, the product of FSamp, RADC and WRa is greater than STrans. The record length (LRec) is commonly configured close to the period of the trigger (TTrig). Consequently, a is less than 1. The minimum value of NumAcc can be calculated by rounding up 1/a to reach 100% efficiency. In addition, if STrans features a higher rate, the averager can achieve 100% efficiency with a smaller NumAcc. Suppose each extraction features the same SNR (SNRU), and the noise is random and not correlated with the ion signal. Then, the signal-to-noise ratio after K accumulations (SNR(K)) can be given by: SNRðKÞ

Inserting Eqns. (9) and (10) into (12), we can calculate the ratio of SNR(NumAcc) to SNRPC_Acc. This ratio represents the SNR improvement over accumulating in the computer (SNRImp) in unit time:

Y. Wang et al.

Figure 7. Performance of the signal conditioner. (a) Analog bandwidth of the signal conditioner with different gain configurations, including 12 dB, 6 dB, 0 dB, –6 dB, –12 dB and 18 dB. (b) Responsiveness of signal conditioner. The upper signal represents the response to an intense pulse. The amplitude scale is 100 mV/div. The lower one is the response to a weak pulse. The amplitude scale is 10 mV/div. (c) Dynamic performance of the signal conditioner. Two spectra are obtained with the DPO4104, which possesses a fast Fourier transform (FFT) option.

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passband. Fine passband flatness is obtained with 6 dB gain, where the swing is 1.95 dB. From these results, it can be seen that the bandwidth is not restricted by the gain owing to the adoption of a fixed gain amplifier and a programmable step attenuator. In view of the large amplitude variation in the ion pulses, the signal conditioner needs to be highly responsive to both intense and weak pulses. To demonstrate this capability, the AFG3102 is used to generate two kinds of pulses. The intense


pulse has 3.6 V amplitude, 8 ns width, 5 ns leading edge and 5 ns falling edge. The weak pulse has 5 mV amplitude and the same width, leading edge and falling edge as the intense pulse. For the intense and weak pulses, the gain of the signal conditioner is set at 18 dB and 12 dB, respectively. As depicted in Fig. 7(b), the response to the intense signal has an amplitude of 409 mV, a deviation of 9 mV from the theoretical value (400 mV). The pulse width is slightly stretched, to 8.39 ns. The leading edge and the falling edge



High-efficiency real-time digital signal averager for TOFMS are 5.62 ns and 5.98 ns, respectively. The weak signal response shows an 8.32 ns width, 5.17 ns leading edge, 5.24 ns falling edge and 18.8 mV amplitude, deviating from the theoretical value of 20 mV. To verify the dynamic performance of the signal conditioner, the SMBV100A is adopted for generating a 500 MHz sinusoidal signal with 1 Vpp amplitude. The spectra are captured by the DPO4104. Figure 7(c) shows a comparison between the signal conditioner’s input spectrum and the output spectrum. In the upper graph, it is clear that the second and third harmonics are very strong. Since it is affected by the second harmonic at 1 GHz, the SFDR is 41.8 dB and the SNR is 48.1 dB. The output spectrum of the signal conditioner produces 45.6 dB SFDR and 49.4 dB SNR, due to the suppression of even-order harmonics by using the full differential amplifier. Dynamic characteristic of acquisition In the test, standard sinusoidal signals, varying from 100 kHz to 1 GHz, are generated as described above. The amplitude of the sinusoidal signal retains 90% of the full scale range of the digital signal averager. The digital signal averager

operates with a 2 GSample/s sampling rate and 0 dB gain. Finally, the acquisition results are sent to the computer, where the fast Fourier transformation is executed to calculate the dynamic characteristics. As shown in Fig. 8, the digital signal averager maintains a stable SNR under 600 MHz. Within this range, the performance of the ENOB is dominated by SFDR, and the optimal ENOB reaches 6.7 bits. When the frequency continues to increase, the SNR declines. At 500 MHz, the SNR reaches 42.66 dB. At the same time, the aperture jitter of the sampling clock is 2.34 ps, which can be calculated using Equation (3). Since the aperture jitter is greater than the upper limit (1.24 ps) for avoiding error code, the ENOB is only 6.2 bits. This figure shows that the SFDR features a distinct shift at 400 MHz. The shift may be attributed to the variance of frequency response in the passband. When the frequency of the input signal increases, the impact of parasitic capacitances and inductances on the input circuit becomes more distinct. Therefore, at some frequency values, the data acquisition module reveals intense harmonic distortion, which reduces the SFDR. Efficiency and SNR improvement

Figure 8. Dynamic characteristics of the data acquisition. The green, blue and red curves represent the performance of SNR, SFDR and ENOB, respectively.

In order to determine the efficiency, the digital signal averager is configured with a 32 ms record length and 2 GSample/s sampling rate. The AFG3102 is used to provide periodic triggers with FTrig = 31.23 kHz, i.e., TTrig is slightly greater than the record length. WRa is 3 and fixed. RADC is 1 Byte (8 bits). The tests are executed on a computer assembled with Intel dual-core T9400 processors, a DDR2 memory of 4 GBytes and a solid state drive (SSD) of 256 GBytes. The digital signal averager is connected to the computer through a USB 2.0 interface, which performs a sustained data throughput of 15.26 MByte/s. It was found that there is an extra overhead time (TEX) in the transmission of one frame from the averager to the computer disk, which is approximately 386 ms and independent of the configurations of the averager. Figure 9(a) compares the measured efficiency to the theoretical value calculated from Eqns. (9) and (10). From the zoomed picture in Fig. 9(a), it can




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Figure 9. Efficiency and SNR improvement. (a) Efficiency with different numbers of accumulations. (b) SNR improvement as a function of numbers of accumulations. The theoretical values are calculated using Eqns. (16) and (17).

Y. Wang et al. be seen that the measured efficiency is 97.04% with NumAcc = 393. The averager reached 100% efficiency until NumAcc = 405. The variation between the measured and calculated values can be attributed to TEX. Thus, considering the extra overhead time, the correcting efficiency of the averager (E*) can be calculated from: E ¼

NumAcc TTrig FSamp LRec WRa RADC þ TEX STrans

(15)

The process of accumulating in the computer performs with an efficiency of 0.70%, which is less than accumulating in the averager with NumAcc = 3 (0.74%). To verify the SNR improvement over accumulating in the computer, the AFG3102 is used to generate periodic pulses and triggers, in which the pulse has 20 mV amplitude, 8 ns width, 5 ns leading edge and 5 ns falling edge. The trigger rate is 31.23 kHz. The digital signal averager operates with a 2 GSample/s sampling rate, 32 ms record length and 0 dB gain. Figure 9(b) shows that accumulating in the averager can achieve good SNR improvement over accumulating in the computer in unit time using NumAcc greater than 3. Inserting Eqn. (15) into (12) and (13), the correcting SNR improvement (SNR*Imp) can be calculated from: SNRImp

sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi NumAcc ðb þ TEX Þ ¼ WRa b þ TEX

(16)

where b is calculated by: b¼

FSamp LRec RADC STrans

(17)

For NumAcc = 405, the SNR improvement reaches 20.18 dB, which is lower than the theoretical value of 21.55 dB. For NumAcc = 3, the SNR improvement reaches 0.33 dB, which is lower than the theoretical value (0.25 dB). This deviation may be attributed to a correlative component in the noise and some drawbacks in the hardware design. In the test, it was observed that more stable data throughput could be obtained by replacing the hard disk drive (HDD) with the SSD, which improves the stability and reliability of data processing. Furthermore, a PC-based multi-threaded strategy is capable of improving the data throughput and operational efficiency.[16]

the pulses is modified in proportion. For example, the amplitude of pulses in the regime using 10 ions per extraction is 10 times greater than the pulses for 1 ion per extraction. The averager operates with a 2 GSample/s sampling rate, 0 dB gain and 1000 NumAcc. Figure 10 compares the dynamic range with the threshold opened to the dynamic range with the threshold closed. It can be seen that the dynamic range in the low concentration regime is enhanced by using a FPGA threshold. The averager can maintain good linearity (R = 0.9991) with concentrations ranging from 0.001 ions per extraction to 70 ions per extraction by using a threshold. If the threshold is closed, the emulated signal with concentrations below 0.08 ions per extraction is submerged in the background noise after 1000 accumulations in the averager, and it cannot maintain linearity. Furthermore, the averager is saturated for concentrations higher than 70 ions per extraction. Experiments using the VUV-SPI-TOFMS The VOCs volatilized from general printed materials, such as newspapers, books and magazines, may contain harmful chemicals (e.g., methylbenzene, butanone and ethyl acetate), which becomes a potential health risk.[32] Hence, it is necessary to detect the residual VOCs in order to improve printing technology. The digital signal averager is used as an ion signal acquisition system in the VUV-SPI-TOFMS for detection of VOCs. As shown in Fig. 11(a), the VUV-SPI-TOFMS uses a polydimethylsiloxane (PDMS) membrane inlet interface to gather the sample gas. In order to ionize the sample gas, ultraviolet light, with 10.6 eV single-photon energy, is generated and focused using a MgF2 lens. These ions, which are attracted and transported by the electrode, are detected by the TOF mass analyzer. Then the ion signal, enhanced by the preamplifier, and the extraction trigger are captured by the digital signal averager. Finally, to obtain the mass spectrum, the accumulation results are transferred to a laptop computer through a USB 2.0 interface. In order to

Dynamic range with a threshold

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Setting a threshold can enhance the dynamic range of the acquisition system in the low concentration regime, particularly for the weak ion signals.[13] To verify the averager’s dynamic range with a threshold, the AFG3102 was used to produce the emulated signals. Periodic triggers are generated with a frequency of 10 kHz for all the emulated concentrations. We use pulses with a frequency of 10 kHz and 10 mV amplitude to emulate the single ion per extraction regime. When the concentration is less than 1 ion per extraction, pulses are synchronized with the triggers using the proportional frequencies below 10 kHz, i.e., for 0.01 ions per extraction, the pulses are generated with a frequency of 100 Hz. For a concentration of more than 1 ion per extraction, the frequency of the pulses is fixed at 10 kHz. The amplitude of


Figure 10. Dynamic range with a threshold. In this test, the threshold was configured 3 LSB above the mean of the background noise. The relative intensity is normalized with a factor of the intensity value of the single ion per extraction regime.



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Figure 11. Analysis of VOCs from printed materials. (a) Schematic diagram of the VOCs analyzer. In the test, some advertising printed materials were placed in a 3 L airtight container, filled with N2 of high purity, for 2 h. (b) Real-time processing capability with different numbers of accumulations, including NumAcc = 5, NumAcc = 50, NumAcc = 390 and NumAcc = 1000. The y-axis is the summed quantized value of the averager. The SNR of five mass peaks are labeled with purple font. At the top right corner of each graph, it provides a zoomed picture with x-axis reserved from 163 m/z to 173 m/z. (c) Standard curves for methylbenzene and dimethylbenzene. Different sample concentrations are used, including 4.1 ppb, 12.5 ppb, 125 ppb, 500 ppb, 1000 ppb, 2000 ppb and 5000 ppb. The intensity (ion counts) of the samples is calculated using the integration of the peak areas.

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improve SNR performance, digital filtering and correlation processing methods are adopted in the PC software. A lowpass finite impulse response (FIR) filter is used to prevent high-frequency noise.[33] Depending on the frequency spectrum of the ion signals, the cut-off frequency is configured without introducing obvious distortions. Unlike random noise, the noise correlated with ion signals (e.g., periodic noise introduced by the sampling clock and coupling noise from the systematical environmental interference) cannot be decreased by averaging.[34,35] Before each measurement, we switch off the ion signal, and a spectrum with correlated noise is acquired and stored as the reference spectrum. Thus, to suppress the correlated noise, the reference spectrum is subtracted from the measured spectra including ion signals. To compensate for the offset error introduced by the TOFMS, we adjusted the baseline of the spectrum in the PC software. To demonstrate the real-time processing capability, the digital signal averager is configured with a 2 GSample/s sampling rate, 32 ms record length and 0 dB gain. The final spectra are acquired with varied numbers of accumulations, including NumAcc = 5, NumAcc = 50, NumAcc = 390 and NumAcc = 1000. The extraction trigger generator is set to produce a total of 300,000 triggers for each measurement, with a frequency of 30 kHz. As shown in Fig. 11(b), mass peaks are identified by referring to the literature concerning VOCs from printed materials.[36–39] Twenty-two kinds of compounds are detected, including acetaldehyde (44 m/z), acraldehyde (56 m/z), acetone (43 and 58 m/z), methyl acrylate (58 m/z), ethyl acetate (70 m/z), butanone (72 m/z), dichloromethane (82 m/z), methylbenzene (92 m/z), aminobenzene (92 m/z), cyclohexanone (82 and 98 m/z), 4-methyl-2-pentanone (100 m/z), isopropanol (106 m/z), dimethylbenzene (106 m/z), ethylbenzene (106 m/z), chlorobenzene (112 m/z), propyl benzene (120 m/z), trimethylbenzene (120 m/z), nitrobenzene (124 m/z), tetramethylbenzene (134 m/z), diethylbenzene (134 m/z), undecane (153 m/z) and tetrachloroethylene (168 m/z). In Fig. 11(b), it can be seen that the VUV-SPI-TOFMS features different real-time processing efficiency with diverse NumAcc. The efficiency of the averager can be calculated from Eqn. (15). For NumAcc = 5, the efficiency is quite low (1.29%). Most of the extractions are missed, so the intensity of the peak is low. For NumAcc = 50, the efficiency increases to 12.85%. Therefore, the intensity of the spectrum is about ten times higher than the intensity with NumAcc = 5. However, many extractions still cannot be recorded. From Eqn. (15), 100% efficiency can be achieved with NumAcc, which is greater than or equal to 390. Thus for NumAcc = 390 and NumAcc = 1000, the averager reaches 100% efficiency. All the extractions are recorded and uploaded to the computer and the intensity achieves its highest level. It can be seen that the optimal efficiency of real-time processing can be obtained by modifying the configuration of the digital signal averager. We calculate the SNR of five mass peaks (43 m/z, 58 m/z, 82 m/z, 120 m/z and 168 m/z) in the different spectra. According to the derivation of the SNR improvement in unit time, better SNR performance is achieved by increasing NumAcc. Thus, compared to NumAcc = 5, the theoretical SNR improvement of NumAcc = 50, NumAcc = 390 and NumAcc = 1000 are 10 dB, 18.92 dB and 18.92 dB, respectively. As shown in Fig. 11(b), the SNR improvement of one peak between every two spectra is in agreement with


the theoretical value. Due to the correlative component in the noise and drawbacks in the hardware, there are still deviations between the measured and theoretical values. To verify the dynamic range of the VUV-SPI-TOFMS using this digital signal averager, the standard gases methylbenzene (5 ppm) and dimethylbenzene (5 ppm) are adopted as samples. In the experiment, high-purity N2 (99.999%) is used as the carrier gas, with a pressure of 0.1 MPa and a flow rate of 1000 mL/min. The concentration of the samples is modulated by changing the flow rate of the standard gas and the carrier gas using mass flow controllers. The digital signal averager operates with NumAcc = 1000, and the trigger generator generates 30,000 triggers for each measurement, with a frequency of 30 kHz. As shown in Fig. 11(c), the VUV-SPI-TOFMS gives excellent linearity over a dynamic range of 3 orders of magnitude. For methylbenzene and dimethylbenzene, the correlation coefficients are 0.9979 and 0.9958, respectively.

CONCLUSIONS A schematic description and experimental realization of a high-efficiency real-time digital signal average is presented. The averager features good responsiveness, wide dynamic range and real-time processing capability. Optimization strategies are adopted for improving the efficiency of the averager. The efficiency and SNR improvement over accumulating in the PC are quantified and measured with emulated signals. By using a FPGA threshold, the linearity of the averager can be improved in the low concentration regimes. For further demonstration of the performance, the digital signal averager is used with a VUV-SPI-TOFMS for analysis of VOCs from printed materials, demonstrating its highly efficient real-time processing and wide dynamic range. In future work, the FPGA-based block RAMs will be replaced by high-capacity on-board DDR2 memory, which can extend the record length and the number of accumulations. In addition the designs for hardware and noise suppression (e.g., careful grounding, shielding and heat dissipation) will be optimized for superior performance.

Acknowledgements This work was supported in part by the Joint Fund Project of National Science Foundation of China - Guangdong Province (No. U12011232). We would like to thank Qiang Liu, Zebin Mai, Guobin Tan and V. I. Kozlovskiy for their helpful discussions and assistance in the test preparation and Shiyu Zhao for his constructive comments on the English writing of this paper.

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