A Highly Efficient Quatro 10T SRAM CELL with Soft Error ... - CiteSeerX

International Journal of Emerging Technology and Advanced Engineering Website: www.ijetae.com (ISSN 2250-2459, ISO 9001:2008 Certified Journal, Volume 4, Issue 3, March 2014)

A Highly Efficient Quatro 10T SRAM CELL with Soft Error Robustness and High Signal to Noise Margin. Ahsan Ul Haq Manzoor1, Tarana A Chandel2, Suhail Beg3 1,3

M.Tech(VLSI) , Integral University Lucknow Jr.Associate Professor, Integral University Lucknow

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Abstract—A ten transistor (10T) SRAM cell with enhanced immunity to soft error induced due to Single Event Upset (SEU) is proposed. The cell is capable of providing higher Signal to Noise Margin (SNM) for 1V supply scenarios in low voltage high speed SRAMs than a soft error tolerant 12T DICE SRAM cell. In comparison to an industry standard 6T SRAM cell, the proposed cell offers increased noise margin, with a negligible compromise on the leakage power. The cell also enables drastic reduction in Soft Error Rate (SER) than the 6T cell, implemented in 90-nm CMOS technology. The proposed cell provides redundancy of the data state stored in a cell without using the error prone inverter logic that displays tendency to provide a short circuit path during its transition from one state to another. SPICE based simulation carried out and has been documented to cross validate the proposed cell’s merits.

Fig 1: particle induced SET

Both memory and logic circuits are prone to soft errors. Compared to logic circuits, memories are more vulnerable to soft error due to their high packaging density and the relative lack of transient masking mechanisms [4]. A particle strike directly affects a memory cell and often the neighboring cells by changing the stored values in these cells. The changed values remain stored until the cells are rewritten. Among memory static random access memory (SRAM) is more prone to soft errors due to larger sensitive volume per bit and lower node capacitance [5]. Early SRAMs were more robust against the soft errors because of their higher operating Voltages and larger junction capacitances. With technology scaling, designers have deliberately minimized the SRAM junction area to reduce capacitance, leakage, and cell area while aggressively reducing the operating voltage to minimize power consumption. But as the scaling approaches nanometer regime the soft error rate (SER) in SRAMs is increasing [2], [6]. So to reduce this SRAM SER error correction codes (ECC) or soft error hardened memory cells have been employed. Hardened memory cells are more widely used because ECC has limited multiple bit error correction capability. The most widely used hardened memory cell is the ten transistor (10t) dual interlocked cell(DICE)[7](see fig 3). Another process compatible differential 10t SRAM cell was reported with less SER [8] ,but this system has less read current due to an extra NMOS. One more area efficient 6t SRAM cell has less SER [9] (see fig 2).

Keywords— Single event effects, soft error, sram,10t SRAM, signal to noise margin ,cell leakage.

I. INTRODUCTION Radiation-induced transients in ICs are primarily caused by energetic neutrons and alpha particles, which come from cosmic rays and chip packaging materials, respectively [2]. These particles generate a dense track of electron-hole pairs as they pass through a semiconductor device, causing a voltage transient at the node that collects the charge (see Fig.1) [3]. This phenomenon is referred to as a single event transient (SET) [1]. Due to their high charge collection efficiency, the reverse-biased p-n junctions in an IC are the most susceptible parts to SETs. If a sufficient amount of charge is collected by the junction, the SET results in a fault by flipping the logic state (‗1‘ to ‗0‘ or vice versa) at the associated node. When such a fault is latched into a memory cell or a flip-flop, a single event upset (SEU) occurs. Since an SEU does not permanently damage the device, it is referred to as a ―soft error‖. It can lead to a system instability or malfunction.

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International Journal of Emerging Technology and Advanced Engineering Website: www.ijetae.com (ISSN 2250-2459, ISO 9001:2008 Certified Journal, Volume 4, Issue 3, March 2014) If the stored bit is logic ―1‖, the logic states of the four nodes are complementary to the logic values of the state ―0‖. Two of these nodes A & B are connected through access transistors, N5 and N6, to the bit lines (BL and BLB), whereas all of the four nodes are fed by their respective NMOS and a PMOS transistor with the gate drives of these driver PMOS and NMOS transistors of a node, controlled by two different nodes. The gate drives of two adjacent nodes, such as, A and B control only NMOS transistors (N2 & N3 by A, N1 &N4 by B) and the other set of adjacent nodes C and D control only the PMOS transistors of the proposed 10T cell. As a result, if Single Event Transient (SET) reverses a node voltage, that node voltage is restored by the either the PMOS or NMOS transistor driving that node and driven by another node. If an alpha or equivalent high energy particle strikes any of the four nodes during the retention or hold state, i.e. when the cell is disconnected from the wordline and bitline access circuitry, thus causing a SET to strike a node and turning on the PMOS or NMO S transistor driven by that node, the turned on transistor is opposed by an unaffected ‗ON‘ NMOS or PMOS transistor, driving that node, to pull up or down its drain voltage respectively. So, negative feedback kick-starts preventing any accidental flipping of the cell. This is totally opposite of the logic realised in a standard 6T cell (Fig.2 excluding Cc), where a positive feedback action is undertaken due to the configuration adopted, when an SET changes a node voltage, which actually helps to flip the cell. For a scenario where an SET simultaneously affects multiple nodes, the proposed 10T cell may also flip. The probability of such a failure depends on the location, magnitude, and duration of the transients. The worst case happens when two nodes of the same potential (nodes A and D or nodes B and C) are affected. Therefore, in order to reduce the possibility of such multiple nodes upsets, care is taken to keep such nodes as physically apart as possible.

In this paper we present a Quatro 10t soft error robust SRAM cell with a little bit of compromise on leakage current but having drastic improvement in signal to noise margin. This cell is referred as Quatro 10t cell because it has four operating nodes. This cell is tested under 90 nm technology.

Fig 2 : CMOS 6T SRAM cell

Fig 3: 12t dice SRAM cell

III. OPERATION OF QUAD NODE 10T SRAM CELL Fig 4: Proposed soft error robust Quatro-10T cell.

A. Read Operation For the read operation as the word line (WL) signal is pulled to logic high turning on the access transistors N5 and N6, the pull-down transistor N1 or N3 discharges BL or BLB depending on the voltage value at node A. The logic-0 degradation is similar to that of a 6T cell for the same driver-to-access (N1/N5) ratio. However, a larger read disturbance at logic-0 node is required to flip the10T cell. This is because, unlike the 6T cell, the accessed node i.e. A & B do not directly drive any PMOS transistor.

II. PROPOSED 10T SRAM CELL The proposed 10T is shown in Fig. 4. Instead of two nodes as in 6T SRAM cell, the 10T cell has four nodes and is thus also referred to as Quattro or quad-node 10T SRAM. The fig.4 depicts the four nodes as A, B, C & D. If we assume that the proposed 10T SRAM cell is storing a bit whose value is logic ‗0‘ at any time , the corresponding logic states at that instant at nodes A, B, C, and D are ‗0‘, ‗1‘, ‗1‘, and ‗0‘, respectively, thus providing a redundancy in terms of the state of the cell. 604

International Journal of Emerging Technology and Advanced Engineering Website: www.ijetae.com (ISSN 2250-2459, ISO 9001:2008 Certified Journal, Volume 4, Issue 3, March 2014) Fig. 6 compares the SNM of the Quatro-10T and standard 6T cells by measuring the side of the largest square inside the close loops of the plotted VTC waveforms of the Quatro-10T and standard 6T cells. The VTCs have been obtained by inserting equal and opposite DC noises at the two storage nodes that hold ‗0‘ and ‗1‘ for 10T and FOR 6T two nodes, such as, Node A and B have been considered The resulting SNM of Quatro-10T cell is much larger than that of the 6T cell for all supply voltages irrespective of the number of increased numbers of transistors that are being driven by nodes like A and B in 10T cell as compared to 6T cells. This makes the Quatro cell very attractive for low-voltage operations. In addition, the Quatro-10T cell consumes 26% less leakage current than the 12T DICE cell and 53% higher leakage current than the 6T cell when simulated at 1V (see Fig.7).

Fig 5( a) Quatro-10T cell with DC noise inserted at storage nodes and ( b) voltage transfer characteristics during read access.

Fig.5 (b) shows the Voltage Transfer characteristics (VTC) of the 10T cell, when equal and opposite DC voltage sources characterizing noise signals and emulating the effect of a radioactive particle striking any one of the nodes at nodes A and B during the read cycle of the memory array. As most of the SRAMs use differential type sense amplifiers, it is desired that for a stable read operation, voltages present on the bitlines should not discharge substantially as this may lead to flipping of the stored value or even worse reduction in the difference between the bitlines themselves. Therefore for a reliable read operation of the 10T cell, where the SNM depends on the W/L ratio of (N1 and N5) or (N3 and N6), the ratio has been optimized to be in the range of 1.5 to 1.7. Substituting the dc currents (noise signals) through N1 and N5, the degradation of logic-0 voltage at node A can be expressed as

Fig 7: Comparison of leakage current at different supply voltages in the simulation.

However, a trade-off between the leakage current and SNM can be made.. Thus, the Quatro-10T cell can save 19% cell leakage without compromising the read SNM.

Where VDSATn is the drain-to-source voltage that causes the carrier velocity saturation, VTHn is the threshold voltage of the NMOS, and the cell ratio is defined as CR is (WN1/LN1)/(WN5/LN5). The value of CR should be typically 1.5-1.7 for a good read SNM.

B.

Write Operation For writing a different logic value into a Quatro-10T cell than the value stored at that instant, both bitline BL and the bitline bar BLB are used. For writing 0, BL and BLB are pre-charged to ‗0‘ and ‗1‘ respectively, and the WL is activated.. Node A discharges through Bitline BL capacitance to pull down the potential at node A, V A , below the threshold voltage VTHn of N3 to turn it off . For such an action to be smooth, N5 has to be stronger than P1. To find the most appropriate sizing of P1 & N5, DC currents through P1 and N5 are equated to determine the voltage at node A as

Fig.6 Comparison of signal to noise margin.

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International Journal of Emerging Technology and Advanced Engineering Website: www.ijetae.com (ISSN 2250-2459, ISO 9001:2008 Certified Journal, Volume 4, Issue 3, March 2014) Mobility‘s, respectively, and PR1 is referred to as pull-up ratio-1 defined as (WP1/LP1)/ (WN5/LN5). Since the NMOS has higher carrier mobility, the pull-up ratio can be kept as 1 to enable pulling down VA. As VA is pulled below to turn off N3, BLB pulls up VB through N6 towards VDD-VTHn . The resulting overdrive of N4 has to be strong enough to fight against P4 so that VD can be pulled down to flip the cell. Equating the DC currents through P4 (saturation) and N4 (linear), the voltage at node D, VD can be expressed by doubling the VTHn parameter value in equation given above for VA and using PR2, referred to as pull-up ratio-2 and defined as (WP4/LP4)/ (WN4/LN4) instead of PR1. For complete writing into the cell, VD has to be pulled below VDD-[VTHp] so that P2 and P3 can be turned on. A PR2 of 0.75 or smaller can reliably do this job as shown in Fig. 8. Since the Quatro-10T cell is symmetric, all of its constituent transistors can thus be easily sized by choosing the CR, PR1 and PR2.

Fig 10: simulation showing flipping of cell for an injected current mimicking a 0 to 1 SET at node A.

Illustrates such a recovery for a 1 to 0 SET at node A. On the other hand, nodes C and D are able to recover from 0 to 1 SETs; however, a sufficiently large 0 to 1 SET at node A or B has the potential to flip the cell. If and a large 0 to 1 SET occurs at node A, N2 can turn on P1 and P4 by lowering while N3 can turn off N4 by lowering . Consequently, the cell flips as shown in Fig. 10. However, the critical charge for such a case is very large meaning a very high energy neutron is required to cause the upset. Since the ground level neutron flux exponentially decreases with increasing energy, upset probability is low. Furthermore, the 0 to 1 SET is less likely to occur at the drain of the ‗OFF‘ PMOS since it requires a higher energy neutron than a 1 to 0 SET does due to the n-well-to-psubstrate junction collecting a sizable portion of the deposited charge. However, the storage nodes (A and B) of the Quatro-10T cell can be made more robust against 0 to 1 SET by appropriately sizing some of the transistors.

IV. SOFT ERROR ROBUSTNESS OF QUATRO 10T SRAM CELL The soft error robustness of the Quatro-10T cell is verified in SPICE by injecting an exponential current at nodes A, B, C, and D to mimic a particle-induced SET. Results show that all nodes are capable of recovering from 1 to 0 SET. Fig. 8

V. CALCULATION OF SNM AND CELL LEAKAGE A. Signal to noise margin: The concept of signal to noise margin (SNM) for an SRAM cell is shown the figure 11. The SNM is defined as the minimum noise voltage present at each of the cell storage nodes necessary to flip the state of the cell. A basic understanding of the SNM is obtained by drawing and mirroring the inverter characteristics and then finding the maximum square between them.[10].

Fig.8: simulation waveform of storage nodes, word line, and it line in a write cycle.

Fig 9: recovery of cell for an injected current mimicking a 1 to 0 SET at node A.

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International Journal of Emerging Technology and Advanced Engineering Website: www.ijetae.com (ISSN 2250-2459, ISO 9001:2008 Certified Journal, Volume 4, Issue 3, March 2014)

Fig 11: butterfly curve for finding SRAM SNM.

Fig 13: standby leakage components in a mosfet.

Signal to noise margin of 6T and 10T cell is shown in fig 6.

After summing up all the leakages the various leakages are given by

B. Cell leakage current [11]: There are three main types of leakage currents present in a mos cell, they are as follows 1. Gate leakage current: Gate leakage current is further of three types. Gate to source leakage, gate to drain leakage, gate to body leakage 2. Sub threshold leakage current 3. Junction current

I sub= I sub N6+ I sub N4+ I sub N1+ I sub P3+ I sub P2

Among these these three leakages subtreshold leakage is the most important one and the other two are almost negligible.[11].

Total leakage current of 10T and 6T SRAM CELL is shown in fig 7.

I junc=I junc N6+ I junc N4+ I junc N1+ I junc N5+ I junc p2+ I junc p3. Igate= IgdN6+ IgdN4+ IgsN3+ IgdN3+ IgdN1+ IgsN2+ IgdN2+ IgdN5+ IsdN5+ IgdP1+ IgsP1+ IgdP3+ IgsP4+ IgdP4+ IgsP2. I leakage total= I sub + I junc + I gate. I leakage almost equal to I sub (fig 13).

VI. CONCLUSION We have presented a 10T SRAM cell that reduces soft errors by 98%. Also our cell has very high SNM which saves leakage power while offering better data stability compared to 6T cell. REFERENCES [1]

[2] [3] Fig 12: various leakage currents

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