A Knowledge-Based System-Level Construction Methodology Peter Oehler, Klaus Waldschmidt Professur fuer Technische Informatik Johann Wolfgang Goethe-Universitaet D-60054 Frankfurt am Main, Robert-Mayer-Strasse 11-15 E-mail:
[email protected], FAX: +49 69/798-22351
ABSTRACT
The synthesis of mixed analog/digital systems is a relatively complex task because of the heterogeneity of these systems. This paper describes how major principles of expert systems for construction tasks can be used to deal with the design space of mixed analog/digital systems at the system level: 1) conception-hierarchies can represent the system level in an elegant way, which views the partitioning problem as a well-de ned task; 2) constraint nets support the distribution of limited design resources. Both together with design methodologies for the subblocks and strategies allow the construction of such systems. This is sucient to make important design decisions at system level, like the determination of sample frequencies and bit widths, for example.
1 INTRODUCTION
Mixed analog/digital systems are typical members of the class of heterogeneous systems. Such systems of high complexity are normally designed using a hierarchy with several levels of abstraction. During the design process, alternatives exist on di erent levels relative to various possible realizations (topologies). A knowledge-based expert system for construction tasks such as PLAKON (Gunter et al., 1991) is well-suited for heterogeneous systems, because it o ers well structured representation forms which can handle the solution (design) space in an ecient way: Conception-hierarchies are used for the representation of static knowledge about construction objects. There are two main relationships mixed in conception-hierarchies: Is-A relations describe possible specializations and Has-Parts relations describe possible compositions of construction objects. Concepts are meta-objects, which span the
This work is supported by DFG under WA 357/9.
solution space of construction objects. An instance of a concept initially spans the entire solution space open to that concept. During the construction process an instance is subsequently specialized and re ned. Dependencies between the parameters of construction objects have to be represented in a general form. This can be expressed with conceptual constraints which, like concepts, are metaobjects. Constraint nets are built dynamically in parallel with the generation of instances. Constraint propagation is done for consistency checks and for reduction of parameter ranges or even determination of parameter values. Instances of concepts and constraint nets build the dynamic knowledge base on which the construction process works. It consists of the repeated execution of one of four possible construction steps: split objects, which means to instantiate subobjects (top-down, using Has-Parts relations); integrate objects (bottom-up, using Has-Parts relations); specialize objects (using Is-A relations); parameterize objects, which means to reduce attribute ranges or even determine attributes of objects. The nal construction consists of a number of instances which satisfy the relations of the conceptionhierarchy and all constraints, and where no more specializations are possible and all attributes of the instances are determined. The concept of the construction tool KANDIS, which follows this methodology, is described in Oehler et al. (1995). The current paper concentrates on the representation of mixed analog/digital systems with conception-hierarchies and constraint nets at the system level. Conception-hierarchies at the system level
o er the possibility to handle di erent kinds of subblocks. Each subblock can use di erent construction or synthesis methods for estimation purposes. KANDIS can deal with systems which consist of subblocks described by functions, such as lters, mathematical operators and A/D and D/A converters, and subblocks described by algorithms, like the process statement o ered in VHDL (IEEE, 1994). The input speci cation for KANDIS is a VHDLhybrid description. VHDL-hybrid is a modeling style of VHDL which allows the user to describe mixed analog/digital systems on a high level of abstraction. In a rst step, the input description is compiled into KIR, a graph-based intermediate format (Grimm and Waldschmidt, 1996). KIR has three sections with di erent semantics: netlist, data- ow graph and discrete-time signal- ow graph. In the second step, the netlist section at top level of KIR is translated into instances of concepts which rebuild the system level on conceptionhierarchies. This is the starting point for the construction process with PLAKON. This methodology is comparable with the hierarchical design methodology proposed in Gielen et al. (1993) and Gielen and Franca (1996). The hierarchies are: system or (sub)chip level, functional block level, circuit level and device level. None of the realized tools known from the literature which follow this methodology work at the system level. They are located at the functional block level (mainly data converters) and the circuit level (mainly operational ampli ers). Our approach considers the system level and the functional block level. It should be noted that the description of mixed analog/digital systems with conception-hierarchies and constraint nets is not just a model but a design tool at system level because of the underlying construction possibilities (control of the construction process, constraint propagation). Further, our approach o ers more exibility during the design process than the design methodology proposed by Gielen et al. (1993): First, it is more exible in the vertical design direction, because the construction doesn't have to be done in a strong top-down manner; Second, it is more exible in the horizontal design direction, because the use of constraint nets handles the distribution of resource limitations more exibly. Figure 1 shows the design ow. Conception-hierarchies for the representation of electronic systems at system level are described in section 2. A general converter concept is presented which takes care of the generation of the correct converter types between the di erent system-level blocks. Constraint nets at system level are shown in section 3. The nature of the design parameters is very di erent: area, power consumption, delays, bit widths, data rates, clock and sampling frequencies, signal levels and frequencies, signal noise ratios. During the construction process the di erent subblocks request design resources and continually reduce the ranges of their design parameters. The di erent constraint nets at sys-
tem level handle this between the subblocks, where con icts because of inconsistency can occur. Section 4 shows how high-level synthesis methods for the parameter estimation of the digital parts can be integrated into our construction methodology. Section 5 describes the minimal set of strategies which are needed for con ict solving.
2 REPRESENTATION OF ELECTRONIC SYSTEMS WITHIN CONCEPTION-HIERARCHIES
Figure 2 shows how mixed analog/digital systems can be represented within conception-hierarchies at the system level: A system consists of blocks at different hierarchical levels and signals which express the structural relationships between the blocks (In- and Out-Signals, are only used at top level, because at lower levels the structural relationships are implicitly known as part of the static knowledge). The concept System is a specialized block which consists only of blocks at the top level. There are also concepts of delays which hold an attribute Tdelay (delay time) between the inputs and outputs of the corresponding block. Most attributes of objects have ranges [min max] which describe the possible solutions. Has-Parts [min-nr max-nr] expresses that this composition consists of minimum min-nr and maximum max-nr instances. Fclk represents the maximumclock frequency of that block and Fs is the sampling frequency. FsigMax describe the maximum signal frequency and Snr is the signal-noise ratio of a signal (only at the system outputs). If a signal lies between blocks of di erent block-types (A - analog, SC - with switched capacitors, D - digital) or the related digital blocks work with di erent clock or sampling frequencies, the construction tool automatically generates a corresponding converter. Such a converter can be an analog low pass lter, an A/D or a D/A converter, a decimator or an interpolator, a parallel to serial (P/S) or serial to parallel (S/P) converter, or a cascade of some of them. Figure 3 shows that part of the conception-hierarchy Converter which is need for the conversion from the analog domain to either the SC or digital domain (or the digital by way of the SC domain). An arrow at the arc of a Has-Parts relation visualizes in which sequential order the blocks are cascaded. A converter between the analog and the digital domain (A-D-Converter) consists of an antialiasing lter, possibly a sample-and-hold circuit, the actual A/D converter ( ash converter, successive approximation, modulation, etc.) and possibly a decimator followed by a P/S converter, for example. The other parts of the conception-hierarchy Converter are similar. There are several choices how an user can describe his intended system: No converters in the VHDL description, but the
attributes Block-Type are speci ed for every block to express the initial partitioning. Therefore, the specialization of each signal to the correct signaltype and the generation of the matching converter is done automatically (if necessary). For example, in gure 4a Signal 1 can be only an A-D-Signal and must have an A-D-Converter. The user describes converters explicitly in his VHDL description. The compiler then generates one instance for each converter. The corresponding signal-types are therefore known and the block-types of the corresponding blocks can be determined automatically. For example, in gure 4b Signal 2 can be only an A-D-Signal and Block 3 (Block 4) must have the block-type A (D). No precondition by the user. The determination of the partitioning (position of the converters) is the task of the construction process. Mixed usage of all three styles above. The necessity of a converter between two digital blocks depends on the corresponding clock and sampling frequencies. Conceptual constraints which use constraint classes of the type EXIST check the inequality of these frequencies and generate necessary converter types automatically.
3 CONSTRAINT NETS AT THE SYSTEM LEVEL
PLAKON o ers constraint nets for the representation and evaluation of dependencies between construction objects or their attributes. Conceptual constraints express relations on concepts of the conception-hierarchy and their attributes. Not only instances are generated during the construction process but also the corresponding constraint nets. Conceptual constraints which handle resource limitations at the system level are shown in gure 5 as dotted lines. The attributes of the whole system are at the top left corner. Attributes of one block and of one signal are illustrated in the middle and the bottom of the gure, respectively. The di erent kinds of conceptual constraints are described in more detail in the following subsections.
3.1 CONSTRAINTS FOR AREA AND POWER CONSUMPTION
The constraints for area and power consumption are related to the Has-Parts relations of the concept block. The area (power consumption) of one block equals the sum of the area (power consumption) of its subblocks. Because the basic principle of numerical constraints is always similar, the realization of the sum-constraint is shown in more detail in gure 6. The maximumarea of one subblock will decrease if the maximum area of the whole system minus the sum extended over the minimum area of all other subblocks is smaller than the old value. The minimum area is computed in the
opposite way. Figure 6 visualizes only the computation of the attribute Area of Block 1. A small example introducing numbers: Let the maximum system area be 1mm2 . At the beginning of a construction, all subblocks have the minimum area of 0mm2 , because they are unknown. A rst subblock is now constructed which needs a minimum area of 50m2 . After the constraint propagation of the sumconstraint all other subblocks will have a maximum area of 1mm2 ? 50m2 = 0:95mm2 which restricts their further construction. Constraints work in both directions which means that a parameter is always input and output of a constraint. In the example above, the area of one subblock can both be reduced by other subblocks' areas and can in uence these attributes.
3.2 TIMING CONSTRAINTS
The user has the possibility to describe user-delays (range [min max]) at the system level from any input to any output by using attributes in his VHDL description. An algorithm searches possible pairs of paths which have the same starting and ending point for every user-delay, as is shown in gure 7a. During the construction process a timing-constraint ( gure 7b) is automatically generated which enforces the minimum and maximum user-delay. A rst version uses a very simple time model, considering only dead times such as the settling time of operational ampli ers and delays in the digital domain. The transient time of lters (analog or digital) shall be included in the time model in the next version.
3.3 CONSTRAINTS FOR FREQUENCIES
Our underlying hardware model assumes that the system has a single master clock, and all derivated slower clocks are generated by simple counters. Several constraints between frequencies exist (see gure 5): The master clock frequency Fclk(System) is an integer multiple of each clock frequency of a block Fclk(Block). The clock frequency of a block Fclk(Block) equals the sampling frequency Fs of that block for a bit parallel realization or Fs multiplied by the bit width of the corresponding signals for a bit serial realization, respectively. Nyquist Criterion: The sampling frequency Fs of a block has to be at minimum twice as the maximum signal frequency Fsig-max of a corresponding signal. The data rate at a signal stays constant, independent of a bit parallel or a bit serial realization.
3.4 CONSTRAINTS ON SIGNAL PATHS
Because an instance of a signal is both connected to an output of one block and an input of the corresponding block (see gure 2), it is automatically realized that the attributes (bit width, Fsig-Max, etc.) of both input and output are always identical. It
should be noted that signals which have an interpolator/decimator block have two di erent bit widths at input and output, respectively. Signal levels and maximum signal frequencies are changed by blocks. For example, the signal level at the output of an ampli er is the input signal level multiplied by the ampli er gain. This can be modeled by directed constraints, that means only from the inputs to the outputs, to simplify the computations. The in uence of feedbacks has to be considered also. A simple approach models all inaccuracies in circuit realizations, such as noise, parameter sensitivities or quantization errors, as stochastic noise signals. These noise signals occur at di erent points in the system. If the (frequency dependent) modi cation of these noise signals via the signal paths to the system outputs are computed, it is possible to calculate the signal-to-noise ratios at the system outputs. This model allows the comparison of di erent system realizations in relation to accuracy. All constraints on signal paths shall be realized with directed constraints. The implementation of these constraints is not yet complete.
4 THE INTERACTION WITH SUBBLOCK CONSTRUCTION/SYNTHESIS METHODS
KANDIS uses a knowledge-based method for the construction of modules described by functions (using the same method as at the system level). Conceptionhierarchies for these modules can be found in Oehler et al. (1995). Digital subsystems need another design method. KANDIS uses high-level synthesis methods (like scheduling) to get estimations for the modules described by algorithms. Therefore, the integration of these methods into the construction process on conception-hierarchies is an important necessity. Subblocks described by algorithms have a computing function which: 1. makes the attributes area, power, clock frequency, bit width for each input and output and delays between each input and output available as constraints; 2. starts the high-level synthesis methods on this subblock; 3. puts the generated estimations back into the attribute slots.
5 STRATEGIES FOR CONFLICT SOLVING
The minimal set of con ict-solving strategies is described in this section. If a computing function at an attribute returns a range of values which is outside of its actual range, a con ict has to be generated. The relationships in gure 5 show, for the di erent kinds of
attributes, the possible candidates for con ict-solving. If the computed range of a delay is outside of its actual range, for example, the other delays on the corresponding signal paths ( gure 7b) are possible candidates for con ict solving. The construction process has to backtrack to the construction step \Parameterize Tdelay".
6 CONCLUSION
This paper has presented a construction methodology at the system level to deal with mixed analog/digital systems. This construction methodology uses basic principles of knowledge-based expert systems for construction tasks: conception-hierarchies and constraint nets. Because it is possible to nd common modeling concepts for di erent design parameters, the problem of the heterogenity of mixed analog/digital systems can be overcome. The implementation of our tool KANDIS is still in progress. A rst prototype of KANDIS works without constraints on signal paths.
7 REFERENCES
IEEE, 1994, "Standard VHDL Language Reference Manual (IEEE Std 1076-1993)". R. Cunis, A. Gunter, and H. Strecker, 1991, "Das PLAKON-Buch", Informatik-Fachberichte, Nr. 266, Springer-Verlag, Berlin, Heidelberg, New York. G. Gielen, K. Swings, and W. Sansen, 1993, "Open analog synthesis based on declarative models", Analog Circuit Design, pp. 421{445, Kluwer Academic Publishers. G. Gielen and J. Franca, 1996, "CAD Tools for Data Converter Design: An Overview", IEEE Transactions on Circuits and Systems - II: Analog and Digital Signal Processing, Vol. 43, No. 2, pp. 77{89.
C. Grimm and K. Waldschmidt, 1996, "KIR - a Graph-Based Model for Description of Mixed Analog/Digital Systems", Euro-DAC, Geneva. P. Oehler, C. Grimm, and K. Waldschmidt, 1995, "Begri shierarchien zur wissensbasierten Konstruktion von Filtern, mathematischen Operatoren und Wandlern (in German)", 7. E.I.S.-Workshop, Technische Universitat Chemnitz. P. Oehler, C. Grimm, and K. Waldschmidt, 1995, "KANDIS - a Tool for Construction of Mixed Analog/Digital Systems", Euro-DAC, Brighton, UK.
8 FIGURES VHDL-hybrid
Conception hierarchies
Partitioning into analog & digital blocks
KIR-Graph
Conceptual Constraints Computing functions & estimation methods for filters, math. operators, A/D & D/A converters
Instances at system level
High-Level Synthesis as estimation method for algorithmic blocks
selected structures (correct construction)
Figure 1: Design ow with KANDIS
Is-A
Has
Has-Parts [0 k]
System
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ar
s-P
rts [
-Pa
Ha
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als
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m Fro
-
lay
De
]
la
De
Signal
Ha
s-C
on
A
ve
Is-
Attributes
rte
r[
01
]
Is-A
Converter
... Has-
Ha
Con
Is-A
A-DSignal
al
gn
-Si
o y-T
Bit width Signal Level Fsig-Max Snr
ASignal
al
gn
-Si
n]
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Is -A
Attributes Block-Type = {A SC D} Area Power Fclk Fs Realization = {parallel serial}
...
ign
ig
Tdelay
Delay
-S
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t-S
Is-A
Is-A
Block
Attributes
0 j]
Delay-List [1 n*m]
r [1]
0]
r[
rte
ve
on
s-C
verte
A-DConverter
A-SCConverter
Figure 2: Conception-hierarchies at the system level
...
[0 1] [0 1 ] [0 1]
[0
Is-A
Is-
Analog Low Pass Filter
Has-Parts [0 1]
A
Converter
1] 2] [0
Sample & Hold
ts
Par
A-SCConverter
sHa
A/D Conversion
arts Has-P SC-D[0 1] D ecima Converter tor [0 1]
D/A Conversion
ts ar -P 1] s a 0 H [ A-DConverter
Interpolator/ Decimator
[0 1] Decimator
[0 1
]
Is-
A
Parallel/ Serial Converter
Is-
A
n-m Bit Converter
Serial/ Parallel Converter
Figure 3: Conception-hierarchy data converter (part A/D conversion)
Attributes
Attributes Block-Type = D
Block 2
Block 3
Block 4
[1
]
]
t-S Ou
Signal 1
als ign In
In
] [1
] [1
-S
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als
als ign
als ign
-S
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[1
Block-Type = A
Block 1
Signal 2
r[
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A-DConverter 1 a.)
b.)
Figure 4: Details of possible constructions: a) block-types are terminated, b) usage of an explicit A/D converter
System Area Power Fclk = m * Fclk(Block)
ΣA r Σ Po ea wer
Block Block-Type Area Power Fclk = n * Fs Fs
Outputs (Set)
Nyquist Criterio
n
Inputs (Set)
Tdelays (Set) Signal Paths
Input/Output: Bit Width Data Rate = Fclk * k Signal Level From Input(Block) to Output(Block) Fsig-Max
}
Parallel Realization: n = 1, k = Bit Width Serial Realization: n = Bit Width, k = 1
m : positive integer, > 0
Figure 5: Constraint nets at the system level
Area(System) [min max]
max
-
min
[min max] Area(Block 1)
[min max] Area(Block 2)
Σ Σ ... ... ...
[min max] Area(Block n)
Figure 6: Sum-constraint detail: Computation of range area of Block 1
td1 td2
td3 td1 user-delay
a.)
td3
[min max]
[min max]
td2 [min max]
user-delay [min max]
b.)
Figure 7: Timing-constraint: Example of a pair of paths: a.) Block diagram detail, b.) Resulting timing relation
