A Low-Power Highly Sensitive Capacitive Accelerometer IC Using ...

IEEE SENSORS JOURNAL, VOL. 15, NO. 11, NOVEMBER 2015

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A Low-Power Highly Sensitive Capacitive Accelerometer IC Using Auto-Zero Time-Multiplexed Differential Technique Yan Mei Wang, Pak Kwong Chan, Senior Member, IEEE, Holden King Ho Li, and Soon-Eng Ong

Abstract— This paper presents a low-power highly sensitive switched-capacitor (SC) readout integrated circuit (IC) for a capacitive accelerometer. Fabricated using bulk micromachining technique, the mechanical sensor with a cantilever structure achieves a high sensitivity and low noise feature. An autozero time-multiplexed differential capacitance-to-voltage converter (AZTMD-CVC) is proposed in the SC readout interface. The CVC is based on a simple single-ended topology to yield a time-multiplexed differential output. As such, dc offset, 1/ f noise, thermal drift, and component mismatch errors are significantly reduced in form of common mode errors through the time-multiplexed differential operation. In addition, the thermal noise of the AZTMD-CVC is analyzed and optimized with power so as to achieve good noise-power efficiency. The application specified IC chip is fabricated using 0.35-µm CMOS technology and draws a total current of 240 µA at a ±2.5 V supply. The accelerometer system’s sensitivity √ is 1.95 V/g. The measured system noise floor is only 1.16 µg/ Hz at 250 Hz and the √ output noise-power product figure of merit (FOM) is 0.28 (µg/ Hz) × mA. Index Terms— Capacitive accelerometer, switched-capacitor capacitance-to-voltage converter, bulk micro-machining, micro-electromechanical systems (MEMS).

Comparing the two main micromachining processes for MEMS accelerometers, bulk micromachined accelerometers [2]–[4] have higher sensitivity as well as lower mechanical thermal noise performance than surface micromachined accelerometers [5]–[8] because of the inherently large seismic or proof mass in bulk micromachined devices. The sensor device developed in this work is a bulk micromachined capacitive sensing element based on a cantilever suspension structure. The out-of-plane sensing scheme results in a high capacitive sensitivity. However, higher parasitic capacitance of the bulk micromachined sensing devices is unavoidable. It contributes to noise issue by increasing the noise gain factor associated with the interface electronics. To overcome this drawback, the design agenda will incorporate a low-power low-noise circuit architecture, low-noise amplifier design, and noise-power optimization. In this way, the interface circuit will be able to tolerate large parasitic capacitances while providing low noise performance metric in conjunction with low-power implementation.

I. I NTRODUCTION

II. R EVIEW OF C APACITIVE S ENSING T ECHNIQUES

APACITIVE micro-accelerometers have the advantages of low drift, low temperature dependence and low power consumption. Such MEMS accelerometer continues to become more popular in automotive and consumer electronics. Precision applications, such as inertial grade navigation, platform stabilization, inertial measurement units (IMUs) and microgravity measurement systems [1], require μg-level based micro-accelerometers. Some of these MEMS accelerometers are powered by batteries and usually incorporate a large number of sensing interface circuitries. Hence, power awareness is a key design priority for electronic readout systems.

In CMOS readout circuits, the dc offset and 1/f noise of charge amplifiers are the major error sources that limit the system resolution in sensor applications, especially at low-frequency bandwidths (dc to 100’s Hz). Chopper stabilization (CHS) [9], switched-capacitor auto-zero (SC-AZ) [10], [11] and correlated double sampling (CDS) [12], [13] are well-established capacitive sensing techniques that can effectively reduce these errors. Compared to the SC scheme, CHS has a lower baseband noise level since it does not suffer from KT/C noise or the thermal noise folding effect. However, as shown in Fig. 1 [16], the CHS technique is sensitive to the parasitic capacitances appearing between the sensing nodes and the ground. A bulk micromachined sensor device typically has parasitic capacitance values at least three to five times larger than its sensing capacitance. This will greatly attenuate the sensor signal, thereby degrading the resolution. Besides, for applications with sensor capacitor values having few tens pF or above, the amplitude of the charging/discharging spikes resulting from the charge injection and clock feed-through effect can be as large as several tens mV. In the CHS scheme, any spikes caused by these non-idealities appearing at the sensitive inputs of the op-amp will be amplified and demodulated at the output [14], [15]. The big AC spikes and

C

Manuscript received April 8, 2015; revised June 10, 2015; accepted June 10, 2015. Date of publication June 25, 2015; date of current version August 26, 2015. The associate editor coordinating the review of this paper and approving it for publication was Dr. Amitava Chatterjee. Y. M. Wang and P. K. Chan are with the School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore 639798 (e-mail: [email protected]; [email protected]). H. K. H. Li is with the School of Mechanical and Aerospace Engineering, Nanyang Technological University, Singapore 639798 (e-mail: [email protected]). S. E. Ong is with Temasek Laboratories, Nanyang Technological University, Singapore 639798 (e-mail: [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/JSEN.2015.2448600

1530-437X © 2015 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.

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Fig. 1.

Fig. 2.

Typical implementation of CHS sensing interface.

Differential interface with ICMFB for half bridge capacitive sensor.

large RC time constant will contribute to a large residual offset and chopper ripple in the demodulation process. Besides, the noise optimization method used in [16] is only suitable for a small sensing element environment. It is common to see that CHS sensing interfaces [16]–[19] being used mainly in small sensing elements, such as surface micromachined or post-CMOS surface micromachined sensor devices. When interfacing with large MEMS sensor devices, the SC-AZ/CDS method is preferred because it is well suited for fast charging and discharging of capacitances while offering simpler circuit topologies. The SC sensing interface also provides the virtual ground at the sensing nodes so that the sensing signal is made insensitive to the parasitic capacitances. To cancel the dc offset, 1/f noise and the switch errors in a SC circuit, one of the more effective ways is to use a fully differential circuitry with the SC-CDS technique. Differential interface topology has the merit of first-order common-mode noise or errors rejection, and has a higher SNR (double output voltage swing) and better power-supply rejection ratio. When a fully differential amplifier is used to interface with only a halfbridge capacitive device having a single common electrode, the typical implementation is to apply the sensing voltage to the common electrode, while the other two electrodes are tied to the amplifier summing nodes. As depicted in Fig. 2 [12], this scheme [12] suffers from an amplifier input common mode level shift problem. To address this problem,

Fig. 3. Differential sensing interface using two pair of half bridge sensor device.

Fig. 4. Offset-canceled (OCC-CVC).

cascade

capacitance-to-voltage

converter

an additional input common mode feedback (ICMFB) circuit is used. Fig. 3 shows the alternative scheme [20] that uses two pairs of half-bridge sensor devices to come up with a fully differential sensing interface with a fully differential amplifier. The tradeoff for both solutions comes at the expense of circuit complexity. They also approximately double the circuit’s area and power consumption compared to the single-ended counterpart. Moreover, the higher complexity of these SC topologies will increase the switch sampling noise. Although the alternative pseudo differential scheme uses two single-ended readouts to eliminate the common mode feedback design, the overheads arising from the two singleended circuits, in terms of their power consumption and circuit area, remain at the same level. Regarding the foundation SC-AZ capacitance-to-voltage converter [21], it has the simplest architecture, and hence lowers SC noise. Unfortunately, it suffers from the non-idealities of dc offset, 1/f noise and switch error. To address these problems, the offset-cancelled cascaded capacitance-to-voltage converter (OCC-CVC) [10], as shown in Fig. 4, is used. The reset clock P1 is turned off earlier than P2 . This action permits the dc offset, flicker noise and charge injection error coming from the first stage to be sampled on C3 . Due to the inverting operation of the second stage with an identically designed op-amp, the sampled error will be largely suppressed at the output by the second op-amp

WANG et al.: LOW-POWER HIGHLY SENSITIVE CAPACITIVE ACCELEROMETER IC

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TABLE I A CCELEROMETER S ENSOR S PECIFICATIONS

Fig. 5. Cross-sectional diagram of the bulk micromachined accelerometer sensor device.

with a similar circuit topology. Despite the simplicity of the circuit, it still relies on two op-amps whilst not compromising on power consumption. In this SC front-end sensing interface, an Auto-Zero Time-Multiplexed Differential Capacitance-to-Voltage Converter (AZTMD-CVC) circuitry is proposed. This circuit architecture provides differential output using a simple singleended CVC design structure. The time-multiplexed differential output improves the S/N ratio and reduces the low frequency errors, including dc offset, 1/f noise and the switch errors comprising charge injection and clock feed through, without sacrificing power consumption and circuit complexity. This scheme also avoids the stringent requirements for component matching and eliminates the common-mode problem in conventional fully differential interface circuitry. Finally, the low-noise design of the front-end charge sensing amplifier along with noise-power optimization in the AZTMD-CVC in the context of the large sensing and parasitic capacitance environment is presented as the solution. Following the Introduction, Section II describes the capacitive sensing structure and the fabrication process associated with bulk micromachined sensor devices. Section III presents the accelerometer IC system block diagram and the basic building blocks, such as the AZTMD-CVC and its powernoise optimization design, the SC differential-to-single-ended amplifier, and the supply-insensitive temperature-compensated oscillator. Section IV discusses the measurement results, and is followed by the concluding remarks in Section V.

In this structure, the external acceleration perpendicular to the plane of the proof mass causes the proof mass to move in the z-direction, resulting in capacitance changes between the proof mass and the two fixed conductive electrodes. The variable capacitors C1S and C2S represent the differential sensing capacitances while C1 P and C2 P are the parasitic capacitances comprised of bonding capacitances as well as stray capacitances resulting from the oxide insulator between two conducting electrodes. Since the bulk micromachining process creates micromechanical structures by selectively etching an entire silicon wafer, the vertical dimensions of the structures that are created can easily be made to match the typical wafer thickness of 500–700 μm. The thick proof mass with an out-of-plane movement scheme and the reduced gap distance significantly increases the capacitance sensitivity of the sensor device. For a low-noise high-resolution sensor system design, the sensor should have a high level of sensing sensitivity so that it alleviates the gain requirement of the electronic readout circuit [12], [20], [22]. A large movable proof mass size also reduces the mechanical thermal noise caused by the Brownian motion of the mass, which is an important factor that limit the system’s noise performance. The accelerometer sensor specifications are given in Table I. IV. A RCHITECTURE OF THE R EADOUT I NTERFACE

III. B ULK M ICROMACHINED ACCELEROMETER S ENSOR The micro-mechanical accelerometer device shown in Fig. 5 is based on a single beam cantilever suspension structure fabricated using a bulk micromachining process. The center wafer is made as a middle moving electrode while the upper and lower wafers are dry-released as the external fixed electrodes. These three wafers are fusion bonded together with an optimal gas damping and bandwidth control, which at the same time allows the sensing element to be encapsulated and hermetically sealed. Silicon dioxide is buried as the dielectric to isolate these three electrodes. Sensor bonding pads are made through a multi-step metallization process. The sensor device is wire-bonded to a standard DIP package and is mounted with the readout integrated circuit (IC) on a PC board for system integration.

Fig. 6 shows the simplified block diagram of the accelerometer ASIC together with the capacitive sensor device. Due to the imperfection in manufacturing process, this capacitive sensor has unbalanced parasitic capacitances. To compensate for the difference between the parasitic capacitances C1 P and C2 P , an offset capacitor, Co f f set , with programmable feature for balancing the differential capacitive sensors, is implemented. It can be configured so that it can be attached either in the top-middle or middle-bottom position in the respective sensing capacitor. The front-end interface is designed using the proposed auto-zero time-multiplexed differential capacitance-to-voltage converter (AZTMD-CVC), which is able to sense and convert changes in sensor capacitance to a differential output voltage without having to use a fully differential circuit

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Fig. 6.

Simplified block diagram of the capacitive accelerometer IC.

TABLE II P ERFORMANCE C OMPARISON OF THE P ROPOSED A CCELEROMETER IC W ITH R EPORTED W ORKS

architecture. The differential output is coupled to a programmable differential-to-single-ended SC gain stage [23]. This is then followed by the signal-conditioning block which comprises an external passive first-order low-pass filter and an on-chip low-offset low-noise op-amp buffer. The external passive RC network provides a smoothing function on the quasi-analog output from the SC gain stage and defines the bandwidth of the accelerometer IC. The op-amp buffer is realized using the precision amplifier topology [24]. As such, the systematic offset is minimized with the cascaded differential amplifier architecture whilst the random offset is minimized with common centroid in centroid layout strategy

on the large-sized critical transistor pairs. The third gain stage ensures high gain to minimize the gain error. Finally, low offset, low noise and high CMRR performance metrics are obtained. Furthermore, a low-power supply-insensitive temperature-compensated relaxation oscillator incorporated with control clock logic will generate the control clocks for the SC system. This is further described in subsequent sections. A. Operation Principle of the AZTMD-CVC Fig. 7 depicts the schematic of the Auto-Zero Time-Multiplexed Differential Capacitance-to-Voltage Converter (AZTMD-CVC) together with its time-multiplexed


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obtained as: 2V R E F + CS Q (n) + Vo f f − sw1 (1) CF 2C F 2V R E F + CS Q (n + 1/2) + Vo f f − sw1 (2) Vo2 (n + 1/2) = CF 2C F where V R E F + = −V R E F − , C S is the ac incremental capacitance subject to acceleration. Qsw1 (n) and Qsw1 (n + 1/2) are the channel charge errors injected by switch SW1 when it is turned off at the end of the reset phase. Due to the swapping action across the voltage references, V R E F + and V R E F − , during T2 on-period, the generated output Vo2 is opposite in magnitude with respect to Vo1. As long as the time-multiplexing rate is much larger than the sensor’s signal frequency, the latency contributed by the switching duration of the time-multiplex clock can be kept to minimum. Therefore, the reverse cycle of the converted electrical signal in the time-multiplexed based cross-coupling switching network will be very close to the magnitude of the positive cycle generated by the single-ended CVC in the earlier time-multiplexing action. In this way, a time-multiplexed differential signal is established between Vo1 and Vo2 . This arrangement allows a simple single-ended CVC to perform the conversion of a capacitive senor signal to a time-multiplexed output voltage signal in a differential format. In addition, this sensing scheme allows low frequency error components such as 1/f noise, dc offset, switch errors contributed by charge injection and clock feed-through and thermal drift to be treated as common mode errors at the time-multiplexed differential output of the TMD-CVC. They will be cancelled by the following differential-to-single-ended gain stage. Unlike the classical fully differential structure, the matching requirement for the feedback capacitor, C F , the reset switch, SW1 , and the symmetry requirement of op-amp implementation will be eliminated because the differential signal is generated by the same set of circuit components. This reduces circuit error without encountering the common-mode feedback circuit in the time-multiplexed differential circuit design. For a capacitive sensor with large sensing and parasitic capacitances, the charging and discharging action in the CVC will cause large spikes because the voltages on the capacitors cannot change instantly. In order to minimize the impact of these spikes, two special S/H sub clocks, T1s and T2s , are generated with the guard band, which rise up later and fall down earlier than the corresponding charge transfer clocks T1 and T2 . This arrangement ensures that the corresponding output signal being sampled to the associated holding capacitor is isolated first prior to the arrival of big spikes for the stated switching transitions. Vo1 (n) = −

Fig. 7.

Schematic diagram of the AZTMD-CVC with its control clocks.

control clock signals. The non-ideal voltage source Vo f f in series with the positive input of the op-amp OA1 represents the flicker noise and dc offset error of the op-amp. This structure deals with a multi-rate SC design. The reset clock 1 , which is equal to the master clock’s frequency, is designed to be twice the frequency of the multiplexed clock, 1 /2, which comprises the charge transfer clocks T1 , T2 and the respective reset period for the time-multiplexed differential channel. The functioning steps of the AZTMD-CVC are summarized as follows: (a) When 1 turns on, both the sensing capacitors and the op-amp are reset. (b) 1 turns off and T1 turns on. The reference voltage will charge up the sensing capacitors and the output of OA1 will charge the feedback capacitor in response to the charge transfer. (c) After a certain intentional delay, T1S will turn on and the output voltage Vo1 will be sampled and stored on Ch1 . (d) This is then followed by the turn-on of 1 again to reset the sensing elements and the op-amp prior to the second charge transfer phase. (e) 1 turns off and T2 turns on. The reference voltage will be interchanged to generate a time-multiplexed differential sensing charge signal across C F . (f) T2S will turn on and the output voltage Vo2 will be sampled and stored on Ch2 . (g) The process is repeated again. It is noted that by using sub-clocks T1S and T2S for delay-sampling and look-ahead holding actions in the sample-and-hold (S/H) process, the large glitches appearing at the clock edges will be suppressed during the charging and discharging of the large time constant environment. This will be confirmed by the simulations in Section V. By charge conservation theory between the reset phase and charge transfer phases, the output voltages of Vo1 and Vo2 are

B. Differential-to-Single-Ended Programmable SC Gain Amplifier The passive S/H outputs of AZTMD-CVC will be coupled to a SC amplifier for scaling the sensing signal. Fig. 8 depicts the schematic of the SC-CDS differential-to-singleended programmable gain stage with its control clocks. A 5-bit programmable capacitor array (PCA) is implemented in parallel with the feedback capacitors C2 and C2 . This

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Fig. 9.

Schematic of the push-pull current mirror core OTA.

acceleration (CNEA). The relationship is defined as follows: (5) T N E A = B N E A2 + C N E A2

Fig. 8. Schematic of the differential-to-single-ended programmable SC-CDS gain stage with its control clocks with respect to reset clock 1 .

permits the adjustment of the second voltage gain stage so that it can compensate the gain variation from the sensor device. Since the signal coupling is based on passive capacitive components, charge sharing effect will occur between capacitor Ch1 (shown in Fig. 4) and C1 . The same goes for Ch2 (shown in Fig. 4) and C1 . Taking into account the charge redistribution, the effective input voltages across capacitor C1 and C1 become ∗ = Vo1

Ch1 Ch2 ∗ Vo1, Vo2 = Vo2 . Ch1 + C1 Ch2 + C1

(3)

Therefore, the output signal after the programmable gain stage is ∗ C1 ∗ Vo1 − Vo2 C2 + C PC A C1 Ch1 2V R E F + C S =− · · C2 + C PC A Ch1 + C1 CF

Vout =

(4)

It is noted that capacitor C1 is made 6 times smaller than the S/H capacitor Ch1 to minimize signal attenuation due to charge sharing effect between the capacitors. C. Electronic Noise Analysis and Optimization The overall system noise performance metric is characterized by the total noise equivalent acceleration (TNEA) which is determined by the sensor’s Brownian noise equivalent acceleration (BNEA) and the circuit noise equivalent

In this design, the bulk micromachined sensor device √ achieves a low Brownian noise level of less than 1 μg/ Hz, making CNEA the limiting factor of the total system noise level. For trade-off design, there always exists a compromise between noise and power consumption in an electronic system. Lower circuit noise typically requires higher power consumption and vice versa. Therefore, it is imperative to examine the key parameters pertaining to the output noise PSD of the SC CVC with respect to the power consumption. Since both the accelerometer sensing capacitance and the integration capacitor used in the interface circuit are large, the KT/C noise is negligible with respect to the amplifier noise which comprises 1/f noise and wide band thermal noise. As interpreted in Section A, the amplifier offset and the 1/f flicker noise can be treated as common-mode errors. They can be cancelled at the time-multiplexed differential voltage output, leaving the wideband thermal noise as the dominant noise factor in the interface circuit. Hence, thermal noisepower optimization becomes the major design strategy for a low-noise front-end electronic interface. Fig. 9 depicts the push-pull current mirror based operational transconductance amplifier (OTA) topology [25] in this AZTMD-CVC. According to the current ratio setting in the current mirror transistors, the total current It ot drawn by the core OTA is 5 times the respective drain current ID , biasing the transistors MP7 and MP8 in the differential pair. For low-noise design consideration, the OTA is designed in a way that the aspect ratio of the differential input pair transistors MP7 and MP8 is significantly larger (600 μm/1 μm) than that of the current mirror transistors MN3 (30 μm/50 μm) and MP1 (10 μm/15 μm). The cascode transistors (MP3 -MP4 , MP6 , MN1 -MN2 , MN5 -MN6 ) do not contribute any significant amount of output noise, because of large source degeneration.


Fig. 10.

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Noise signal processing in the TMD-CVC interface. Fig. 11.

The same goes for the tail current source transistor MP5 which has very small transconductance value. Hence, the OTA input-referred noise PSD mainly comes from the input pair and the active current mirror loads. It is derived as follows: 16K T 7 gmn3 3 gmp1 16K T (1 + · + · )≈ (6) Snop = 3gmp7 4 gmp7 4 gmp7 3gmp7 where gmp7 gmp1 , gmp7 gmp3 , gmn3 , gmp1 , gmp7 are the respective transconductance of the transistors, K is the Boltzman’s constant, and T is the temperature in Kelvin. Fig. 10 illustrates the thermal noise model in the SC interface circuit. It is assumed that the parasitic capacitances associated with the sensor device are balanced, such that C1 P = C2 P + Co f f set = C P . During the reset phase 1 and the charge sensing phase T1 or T2 , the broadband thermal noise entering the system is directly amplified and low-pass filtered by the SC interface with respective continuous-time circuit transfer function of H (s). Between the transition of these two working phases, the noise source is sampled at the end of the reset phase and later transferred to the output as a sampled-data signal during the charge transfer phase. Based on the SC noise analysis method in [26], the noise PSD Sno (ω) at the output of the charge sensing amplifier is given as follows: Sno (ω) =

Snop · (1 + α)2 2 2(1 + ) 2[1 + ω2 1+α ] ωu 2 1 z− 2 ωT π fu ) · Snop · −α · + · sin c2 ( ωT (1 + α) f s 2 j 2 sin( 2 ) (7) Snop

ω2 ωu2

+

where (1 + α) is the noise gain factor, α = (C1S + C2S + 2CP )/CF > 1, ωu = 2π f u = gmp7 /Cload is the unity gain bandwidth of the op-amp, Cload is the load capacitor. The output noise Sno (ω) of the charge sensing amplifier is then sampled by capacitors Ch1 and Ch2 during the on-periods T1s and T2s . This process results in two sampled noise components Sno1 and Sno2 accordingly. Since all the samples of the output noise signal are sampled from the same noise

AZTMD-CVC output noise PSD under different supply currents.

source Sno by the capacitors Ch1 and Ch2 at the same sampling rate, the PSD of Sno1 and Sno2 are of the same value and are uncorrelated with each other. Hence, the low frequency noise PSD of Sno1 and Sno2 are obtained as follows: Sno1 = Sno2

π fu π fu π fu + Snop · (1 + α) · + Snop · α · 2 fs 2 fs fs π fu 3 = Snop · (1 + α) · (8) 2 fs As a result, the overall output noise Snot ot al arising from the time-multiplexed differential output (Vo1 −Vo2 ) can be obtained as follows: π fu Snot ot al = Sno1 +Sno2 = 2Sno1 = Snop · (2 + 3α) · fs 16K T π fu ≈ · (2 + 3α) · (9) 3gmp7 fs = Snop ·

From (9), it can be concluded that the overall output noise is a function of the transconductance gmp7 , the noise gain factor α and the undersampling ratio (π f μ )/ f s . Besides, without sacrificing power consumption, the SNR of the proposed TMD-CVC is increased when compared to the single-ended counterpart. This is because the output signal amplitude is doubled in the differential operation. In the bulk micromachined sensor device, the level of the parasitic capacitance C P typically is at least five to ten times that of the sensing capacitor C1S . The high parasitic capacitance eventually increases the noise gain α, leading to a high level of output noise. It is apparent that power and noise are the major parameters in conflict, especially in the context of the high parasitic capacitance environment that degrades the noise performance of readout circuits. To address this problem, a trade-off design strategy between noise and power consumption is adopted. Fig. 11 shows the simulation and theoretical results of the output noise PSD Snot ot al in (9) adopting different OTA input pair transistor aspect ratios at different I D biasing currents, with the relationship that the supply current It ot = 5I D . It is noted that the unity gain frequency ωu is kept constant by

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maintaining a constant ratio between gmp7 and Cload . It can be seen from the figure that, despite some small differences, the theoretical results correlate well with the simulation results. Referring to the design using W/L = 600 μm/1 μm, each segmented area is formed by the multiplication of the output noise PSD and the supply current. This is called the noisepower product (NPP), and it is used as a FOM for assessing the performance metric of capacitive accelerometer readout IC designs [28], [29]: the smaller the NPP, the better a system’s noise-power efficiency. It can be interpreted from Fig. 11 that the NPP increases nonlinearly as the bias current rises. By comparing these two output noise curves, the design with larger aspect ratios indicates a better NPP, which yields a lower noise level with effective power utilization. Hence, the relationship between NPP and the bias current, as well as the aspect ratios of the input pair transistors, provide low-noise, low-power optimization. The analysis of the NPP is as follows. Based on the SC thermal noise analysis result of the interface circuit given in (9), the NPP can be expressed as N P P = Snot ot al · It ot ≈ = A·

16K T π fu · (2 + 3α) · · It ot 3gmp7 fs

ID gmp7

(10)

where It ot = 5I D is the total current drawn by the AZTMD-CVC OTA, and A is a constant coefficient equal to [80KT(2 + 3α) · π f u ]/3 f s . According to [25] and [27], the relative transconductance in all the transistor inversion regions is defined as gmp7 κ 2 ≈ · (11) √ ID VT 1 + 1 + 4 · I C where κ is the subthreshold gate coupling coefficient, VT is the thermal voltage, the inversion coefficient I C = I D /I S as indicated in Fig. 11 is the ratio of the transistor drain current ID over the moderate inversion characteristic current I S . Substituting (11) into (10), we obtain √ VT 1 + 1 + 4I C · (12) NPP = A · κ 2 where IC is given as IC =

ID κ ID = IS 2μCox VT2 (W /L)

(13)

From (12), the NPP is minimized when the inversion coefficient IC of the input pair transistors is minimized. In brief, the input pair transistors should be biased with a small bias current I D and a large W/L ratio to obtain a small NPP (the relative transconductance gmp7 /I D is maximized in the subthreshold region). However, the minimum bias current is constrained by the low output noise requirement, while the W/L ratio is limited by the area constraint and the slew rate requirement. When 4I C < 1, using the power series expansion, (12) can be rewritten as follows: NPP ≈ A ·

VT · (1 + I C) κ

(14)

Fig. 12.

Schematic of the current source generator (startup not shown).

The NPP can be made approximately linear with IC. Indeed, when the input pair transistors are biased into weak inversion region where the IC is much smaller than 1, slightly increasing the bias current will significantly reduce output noise without substantially affecting the NPP due to the linear and deeper slope. This can be seen from the two segments from point A to point C using W/L = 600 μm/1 μm. For the segment AB, the output noise is reduced by 30% while the NPP remains almost unchanged. For the segment BC, the output noise is reduced by 60% and the NPP increases by approximately 20%. When the bias current is increased beyond that, the level of output noise will reduce at a much slower rate, in contrast to the rapid increase of NPP. This gives the illustration that point C is at the optimal bias current level when I D = 15 μA or It ot = 75 μA for this noise-power optimization design because it yields a low level of output noise while power consumption is not excessively increased (the NPP is not sacrificed). This design optimization is based on the input pair transistors working in the subthreshold region, implying large aspect ratios for the input pair transistors under a certain bias current level. This noise-power optimization strategy is different from the CHS scheme [16], where the input capacitance of the amplifier is made comparable with the sensing and parasitic capacitances in the surface micromachined sensor device. It turns out that CHS noise optimization in bulk micromachined sensors becomes difficult because of the need to substantially increase the parasitic capacitance of input transistors to match the capacitances coming from the large sensor. Instead of that approach, the parasitic capacitances of input transistors in this proposed noise-power optimization work in SC-AZ CVC do not have any significant effects. In fact, large input transistors which operate in subthreshold regions to take advantages of power efficiency are favored. This justifies why the SC-AZ scheme is suitable for large bulk micromachined sensors. D. Low-Power Vdd -Tracking Temperature-Compensated Relaxation Oscillator In order to provide a fully integrated clock oscillator low sensitivity to temperature and supply variation, a Vdd -tracking temperature-compensated current comparator for one-shottimer based relaxation oscillator is proposed. The relaxation


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Fig. 13. One-shot-timer based on Vdd -tracking temperature-compensated current comparator.

Fig. 15.

Fig. 14. Exemplary simulated output glitches for different output signals under 0g input in Fig. 7 using the sub-clocks T1S and T2S for glitches suppression via the delay-sampling and look-ahead hold process.

oscillator consists of a startup circuit, two one-shot timer [30] circuits in a ring arrangement and a current source generator to produce constant currents with a negative temperature coefficient (T.C.) for biasing the respective one-shot timer. For the current source generator in Fig. 12, MP9 is biased into the weak inversion region with a large W/L ratio and its source-to-gate voltage over the poly resistor R3 defines the bias current for this circuit as follows: VSG9(T ) Ire f = (15) R3 (T ) Fig. 13 shows the schematic of the one-shot timer circuit which comprises a NOR gate based SR latch, a Vdd -tracking temperature-compensated current comparator and a buffer inverter. Transistors MP0 and MN0 control the respective charging and discharging actions of the capacitor C. When CLK is low, transistor MP0 is on and will quickly charge capacitor CL to the supply voltage Vdd . When CLK is high, transistor MN0 will turn on and capacitor CL will discharge almost linearly through the current source.

Integrated system prototype

The current comparator compares the current Iin with the reference current Ire f and causes the transition of output voltage level at Vo . Specifically, when the node voltage VC L is charged to a point higher than Vdd − Vre f , Iin will be smaller than Ire f . Eventually, it will force the transistors MN10 and MN11 to go off and exhibit a high resistance, thereby increasing the output voltage Vo . When VC L is discharged to a potential which is lower than Vdd − Vre f , Iin becomes larger than Ire f . It causes the transistors MN10 and MN11 to enter into the triode region. This results in a low potential level at the output node. The comparison output Vo will be sharpened by the buffer inverter in which the output generates the reset signal for the SR latch. As discussed above, the capacitor C L is quickly charged to supply voltage Vdd first. It is then constantly discharged to a potential level of Vdd − Vre f . The oscillation frequency is mainly determined by the discharging time Tdis of the capacitor C L . It is given as follows: Q 2C L {Vdd − [Vdd − VSG10(T ) − Iin (T )R0 (T )]} = I Ire f (T ) 2C L [VSG10(T ) + Iin (T )R0 (T )] = Ire f (T ) 2C L VSG10(T ) 2C L Iin R0 (T ) + (16) = Ire f (T ) Ire f (T )

Tdis =

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Fig. 16. Output voltage of the micro-accelerometer system against acceleration.

Fig. 17. Dynamic response of the accelerometer readout (channel 2 on bottom trace) under electrostatic force of actuation by a 100 Hz sinusoidal input (channel 1 on top trace) at a reference input of the sensor.

Fig. 19.

Fig. 20.

Measured in-run bias instability.

Measured clock signal in one sample.

reference current generated by the self-biased current source generator. As can be observed from (16), the discharging time is independent of the supply voltage Vdd since the former does not affect the charge difference Q. Among these temperature-dependent terms, the temperature coefficients of VSG10(T ) and VSG9(T ) can cancel each other. The same goes for those of Iin (T ) and Ire f (T ). As such, the expression for discharging time can be rewritten as Tdis =

Fig. 18.

Measured output noise at 0 g.

where VSG10(T ) and VSG9(T ) are the respective source-togate voltage of transistors MP10 and MP9 , Iin (T ) is the current flowing through the N-well resistor R0 (T ), and Ire f (T ) is the

2C L R3 (T )VSG10 2C L Iin R0 (T ) + VSG9 Ire f

(17)

Only two temperature-dependent terms, R0 (T ) and R3 (T ), remain in (17). The poly resistor R3 (T ) has a linear negative temperature coefficient which counteracts the coefficient of the N-well resistor R0 (T ). By proper choosing the values for the N-well resistor R0 (T ) and the poly resistor R3 (T ), the combined T.C. will tend to zero. Finally, a temperatureindependent oscillation frequency is achieved. The clock signal that is generated will pass through a control clock generator logic composed of a frequency divider, delay blocks and two sets of non-overlapping clock generator blocks. This combination generates the 20 kHz reset phase clock


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Fig. 21. Measured 5 samples’ clock frequency against: (a) temperature variation and (b) supply variation. (a) Frequency variation with temperature. (b) Frequency variation with supply voltage.

for the first stage and two sets of 10 kHz non-overlapping charge transfer clocks for AZTMD-CVC and the differentialto-single-ended gain stage respectively. V. R ESULTS AND D ISCUSSIONS The ASIC interface IC has been designed and fabricated using the AMS 0.35-μm CMOS 3.3/5V process. Fig. 14 shows the simulation results of the charging/discharging glitches using the delay-sampling and look-ahead hold process discussed in Section IIIA. The sensor device is modeled as having sensing capacitance of 20pF in parallel with 100pF parasitic capacitance at each side in Fig. 7. As can be seen from the simulation results, the amplitude of the glitches can reach as high as 75 mV before the S/H action. With the sub-clocks T1S and T2S enabling the delay-sampling and look-ahead hold process, the time-constant induced spikes in Vo1 and Vo2 are largely removed. The remaining errors are the dc offset and the switch error induced spikes which come from the switching operation of each S/H switch. The average result is close to zero in the differential signal Vdiff , leaving the final residual dc offset of about 1μV. This has demonstrated the effectiveness of the timing scheme in the special S/H. Fig. 15 shows the integrated system prototype which includes the packaged accelerometer sensor device, the readout IC and other peripheral electronic components dedicated to trimming functions. The packaged sensor is mounted onto the PC board with the interface IC. The system sensitivity test is performed under a 1 g gravitational field with the PC board mounted onto a precise tilting table which can rotate 180° to change the acceleration on the sensor from −1 g to 1 g with a resolution of 0.002°. Fig. 16 shows the output response of the micro-accelerometer system under −1 g to 1 g external acceleration. The system shows a sensitivity of 1.95 V/g with a nonlinearity error of 0.4%. Fig. 17 shows the measured output response (channel 2 on bottom trace) of accelerometer readout when an ac signal of 100 Hz (channel 1 on top trace) is applied to one reference with electrostatic force of actuation of the mechanic sensor while the other reference

is set to ground. It can be seen the dynamic sinusoidal response is reasonable good and clean. The measured output noise at 0 g is shown in Fig. 18. The system achieves a low noise level of −100 dBm/Hz, which corresponds to an √ equivalent noise acceleration of 1.16 μg/ Hz. The total current consumption including the clock generator is 240 μA at a ±2.5-V supply. The bias stability test is taken under 0g acceleration over a timespan of around 3 hours. The Allan variance analysis, plotted in Fig. 19, indicates a bias stability of 7.5 μg. Fig. 20 shows the clock signal from one sample. The Vdd -tracking current comparator-based relaxation oscillator provides a 172 kHz fundamental clock for the interface circuit. The power consumption of this oscillator circuit is only 20 μW. Fig. 21 shows the measured clock frequency against temperature and supply variation, respectively. With 5 samples, the clock signal has a mean variation of 0.23% when the supply ranges from ±1.6 V to ±2.5 V, and a mean T.C. of around 0.018%/°C when the clock frequency ranges from −40 to 90 °C. Table II depicts the performance of the IC and the comparison with other reported prior-art works. The results indicate that the proposed accelerometer IC achieves the best FOM in terms of output noise-power product. This outcome demonstrates the effectiveness of the simple timemultiplexed single-ended CVC architecture, low-noise OTA design and the noise-power optimization method. VI. C ONCLUSION A new auto-zero time-multiplexed differential capacitanceto-voltage converter is presented. It is integrated with the signal-processing block and other house-keeping circuitries, such as the oscillator and the clock generator, in the ASIC design. It has been fabricated using AMS 0.35-μm CMOS process. A bulk micromachined accelerometer sensor device is interfaced with the ASIC. The ASIC interface offers differential output on the basis of a singleended topology. It provides the technical merits of low cost, low power consumption, simple circuit architecture, a reduced component pair matching requirement, and improved

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S/N ratio. The design has also adopted low-noise OTA and the noise-power optimization of the CVC. As a result, the accelerometer IC achieves high sensitivity, low noise and low current consumption. R EFERENCES [1] N. Yazdi, F. Ayazi, and K. Najafi, “Micromachined inertial sensors,” Proc. IEEE, vol. 86, no. 8, pp. 1640–1659, Aug. 1998. [2] T. Smith, O. Nys, M. Chevroulet, Y. DeCoulon, and M. Degrauwe, “A 15 b electromechanical sigma-delta converter for acceleration measurements,” in IEEE ISSCC Dig. Tech. Papers, San Francisco, CA, USA, Feb. 1994, pp. 160–161. [3] H. Kulah, J. Chae, N. Yazdi, and K. Najafi, “A multi-step electromechanical converter for micro-g capacitive accelerometers,” in IEEE ISSCC Dig. Tech. Papers, San Francisco, CA, USA, Feb. 2003, pp. 202–488. [4] J. Chae, H. Kulah, and K. Najafi, “An in-plane high-sensitivity, lownoise micro-g silicon accelerometer with CMOS readout circuitry,” J. Microelectromech. Syst., vol. 13, no. 4, pp. 628–635, Aug. 2004. [5] B. E. Boser and R. T. Howe, “Surface micromachined accelerometers,” IEEE J. Solid-State Circuits, vol. 31, no. 3, pp. 366–375, Mar. 1996. [6] X. Jiang, F. Wang, M. Kraft, and B. E. Boser, “An integrated √surface micromachined capacitive lateral accelerometer with 2 μG/ Hz resolution,” in Proc. Solid-State Sens., Actuator Microsyst. Workshop, Hilton Head Island, SC, USA, 2002, pp. 202–205. [7] A. A. Seshia et al., “A vacuum packaged surface micromachined resonant accelerometer,” J. Microelectromech. Syst., vol. 11, no. 6, pp. 784–793, Dec. 2002. [8] H. Luo, G. Zhang, L. R. Carley, and G. K. Fedder, “A post-CMOS micromachined lateral accelerometer,” J. Microelectromech. Syst., vol. 11, no. 3, pp. 188–195, Jun. 2002. [9] J. Bernstein, R. Miller, W. Kelley, and P. Ward, “Low-noise MEMS vibration sensor for geophysical applications,” J. Microelectromech. Syst., vol. 8, no. 4, pp. 433–438, Dec. 1999. [10] L. Zimmermann et al., “Airbag application: A microsystem including a silicon capacitive accelerometer, CMOS switched capacitor electronics and true self-test capability,” Sens. Actuators A, Phys., vol. 46, nos. 1–3, pp. 190–195, Jan./Feb. 1995. [11] M. Yucetas, J. Salomaa, A. Kalanti, L. Aaltonen, and K. Halonen, “A closed-loop SC interface for a ±1.4 g accelerometer with 0.33% √ nonlinearity and 2 μg/ Hz input noise density,” in IEEE ISSCC Dig. Tech. Papers, San Francisco, CA, USA, Feb. 2010, pp. 320–321. [12] M. Lemkin and B. E. Boser, “A three-axis micromachined accelerometer with a CMOS position-sense interface and digital offset-trim electronics,” IEEE J. Solid-State Circuits, vol. 34, no. 4, pp. 456–468, Apr. 1999. [13] B. R. Schiffer, A. Burstein, and W. J. Kaiser, “An active charge cancellation system for switched-capacitor sensor interface circuits,” IEEE J. Solid-State Circuits, vol. 33, no. 12, pp. 2134–2138, Dec. 1998. [14] C. C. Enz and G. C. Temes, “Circuit techniques for reducing the effects of op-amp imperfections: Autozeroing, correlated double sampling, and chopper stabilization,” Proc. IEEE, vol. 84, no. 11, pp. 1584–1614, Nov. 1996. [15] P. K. Chan and J. Cui, “Design of chopper-stabilized amplifiers with reduced offset for sensor applications,” IEEE Sensors J., vol. 8, no. 12, pp. 1968–1980, Dec. 2008. [16] J. Wu, G. K. Fedder, and L. R. Carley, “A low-noise low-offset √ capacitive sensing amplifier for a 50-μg/ Hz monolithic CMOS MEMS accelerometer,” IEEE J. Solid-State Circuits, vol. 39, no. 5, pp. 722–730, May 2004. [17] D. Zhao, M. F. Zaman, and F. Ayazi, “A chopper-stabilized lateralBJT-input interface in 0.6 μm CMOS for capacitive accelerometers,” in IEEE ISSCC Dig. Tech. Papers, San Francisco, CA, USA, Feb. 2008, pp. 584–637. [18] D. Y. Fang, “Low-noise and low-power interface circuits design for integrated CMOS-MEMS inertial sensors,” Ph.D. dissertation, Dept. Elect. Comput. Eng., Univ. Florida, Gainesville, FL, USA, 2006. [19] Y. Hu and M. Sawan, “CMOS front-end amplifier dedicated to monitor very low amplitude signal from implantable sensors,” in Proc. 43rd IEEE Midwest Symp. Circuits Syst. (MWSCAS), vol. 1. Aug. 2000, pp. 298–301. [20] F. Zhu and J. W. Spronck, “A capacitive tactile sensor for shear and normal force measurements,” Sens. Actuators A, Phys., vol. 31, nos. 1–3, pp. 115–120, Mar. 1992.

[21] K. Chun and K. D. Wise, “A high-performance silicon tactile imager based on a capacitive cell,” IEEE Trans. Electron Devices, vol. 32, no. 7, pp. 1196–1201, Jul. 1985. [22] B. V. Amini, S. Pourkamali, M. Zaman, and F. Ayazi, “A new input switching scheme for a capacitive micro-g accelerometer,” in IEEE Symp. VLSI Circuits Dig. Tech. Papers, Jun. 2004, pp. 310–313. [23] K. Martin, L. Ozcolak, Y. S. Lee, and G. C. Temes, “A differential switched-capacitor amplifier,” IEEE J. Solid-State Circuits, vol. 22, no. 1, pp. 104–106, Feb. 1987. [24] X. L. Zhang and P. K. Chan, “An untrimmed CMOS amplifier with high CMRR and low offset for sensor applications,” in Proc. IEEE Asia Pacific Conf. Circuits Syst. (APCCAS), Nov./Dec. 2008, pp. 802–805. [25] R. R. Harrison and C. Charles, “A low-power low-noise CMOS amplifier for neural recording applications,” IEEE J. Solid-State Circuits, vol. 38, no. 6, pp. 958–965, Jun. 2003. [26] C.-A. Gobet and A. Knob, “Noise analysis of switched capacitor networks,” IEEE Trans. Circuits Syst., vol. 30, no. 1, pp. 37–43, Jan. 1983. [27] Y. Tsividis, Operation and Modeling of the MOS Transistor, 2nd ed. Boston, MA, USA: McGraw-Hill, 1998. [28] W. F. Lee and P. K. Chan, “A capacitive-based accelerometer IC using injection-nulling switch technique,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 55, no. 4, pp. 980–989, May 2008. [29] X. Zhang and P. K. Chan, “A low-power switched-capacitor capacitive transducer with high resolution,” IEEE Trans. Instrum. Meas., vol. 57, no. 7, pp. 1492–1499, Jul. 2008. [30] R. Woudsma and J. M. Noteboom, “The modular design of clock-generator circuits in a CMOS building-block system,” IEEE J. Solid-State Circuits, vol. 20, no. 3, pp. 770–774, Jun. 1985. [31] B. V. Amini, R. Abdolvand, and F. Ayazi, “A 4.5-mW closed-loop micro-gravity CMOS SOI accelerometer,” IEEE J. Solid-State Circuits, vol. 41, no. 12, pp. 2983–2991, Dec. 2006. [32] H. Qu, D. Fang, and H. Xie, “A monolithic CMOS-MEMS 3-axis accelerometer with a low-noise, low-power dual-chopper amplifier,” IEEE Sensors J., vol. 8, no. 9, pp. 1511–1518, Sep. 2008. [33] P. Lajevardi, V. P. Petkov, and B. Murmann, “A interface for MEMS accelerometers using electrostatic spring constant modulation for cancellation of bondwire capacitance drift,” IEEE J. Solid-State Circuits, vol. 48, no. 1, pp. 265–275, Jan. 2013.

Yan Mei Wang received the B.Eng. (Hons.) degree in microelectronics from Southwest Jiao Tong University, China, in 2010, and the Ph.D. degree in analog and mixed signal IC design from Nanyang Technological University, Singapore, in 2015. Her research area is analog and mixed signal interface circuits design for low-power high-resolution sensor readout systems.

Pak Kwong Chan was born in Hong Kong. He received the B.Sc. (Hons.) degree from the University of Essex, U.K., in 1987, the M.Sc. degree from the University of Manchester, Institute of Science and Technology, U.K., in 1988, and the Ph.D. degree from the University of Plymouth, U.K., in 1992. From 1989 to 1992, he was a Research Assistant with University of Plymouth, working in the area of MOS continuous-time filters. In 1993, he joined the Institute of Microelectronics, Singapore as a member of the Technical Staff, where he designed highperformance analog/mixed-signal circuits for integrated systems and CMOS sensor interfaces for industrial applications. In 1996, he was a Staff Engineer with Motorola, Singapore, where he developed the magnetic write channel for Motorola first generation hard-disk preamplifier. He joined Nanyang Technological University, Singapore in 1997, where he is currently an Associate Professor with the School of Electrical and Electronic Engineering. Besides, he served as an IC Design Consultant to local and multi-national companies and conducted numerous IC design short courses. He served as a Guest Editor for 2011 and 2012 Special Issues in Journal of Circuits, Systems and Computers. His current research interests include sensor circuits and systems, mixed-mode circuits and systems, PVT-insensitive circuits and systems, precision analog circuits, ultra low-voltage low-power circuits, and power management IC for integrated sensors and system-on-chip.


Holden King Ho Li received the B.Eng. degree from the National University of Singapore, in 1997, and the M.S. and Ph.D. degrees from Stanford University, CA, USA, in 2002 and 2005, respectively, all in mechanical engineering. From 1997 to 2013, he was with the DSO National Laboratories, Singapore, where his focus is on the electronics testing instrumentation and development of MEMS sensors. In 2013, he joined the School of Mechanical and Aerospace Engineering, Nanyang Technological University, Singapore, where he currently focus on micro and nanofabrication methods and MEMS reliability study. Besides, Holden is actively working in the area of integration of microelectronics with MEMS and system level design.

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Soon-Eng Ong received the B.Eng. degree in mechanical engineering and the Ph.D. degree in diamond-like carbon film for BioMEMS from Nanyang Technological University (NTU), Singapore. He is currently a Senior Research Scientist with Temasek Laboratories, NTU. He has been involved in a technology buildup of the laboratory’s microfabrication capability, and in the design and development of microsensors and systems. He has also co-developed a 3D encapsulated MEMS microfabrication process with GlobalFoundries, and is running projects based on this process.