A Low-Power Low-Noise Dual-Chopper Amplifier for ... - IEEE Xplore

IEEE SENSORS JOURNAL, VOL. 11, NO. 4, APRIL 2011

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A Low-Power Low-Noise Dual-Chopper Amplifier for Capacitive CMOS-MEMS Accelerometers Hongzhi Sun, Student Member, IEEE, Deyou Fang, Kemiao Jia, Student Member, IEEE, Fares Maarouf, Member, IEEE, Hongwei Qu, Member, IEEE, and Huikai Xie, Senior Member, IEEE

Abstract—This paper reports a novel dual-chopper amplifier (DCA) and its application to monolithic complementary metal–oxide semiconductor–microelectromechanical systems accelerometers. The DCA design minimizes the power consumption and noise by chopping the sensing signals at two clocks. The first clock is a high frequency for removing the flicker noise while the second clock is a significantly lower frequency to keep the unit gain bandwidth low. A monolithic three-axis accelerometer integrated with the DCA on the same chip has been successfully fabricated using a post-CMOS micromachining process. The measured noise floors are 40 g/ Hz in the - and -axis and 130 g/ Hz in the -axis, and the power consumption is about 1 mW per axis. Index Terms—Accelerometer, capacitive sensing, chopper stabilization, complementary metal–oxide semiconductor–microelectromechanical systems (CMOS-MEMS), dual-chopper amplifier (DCA), microelectromechanical systems (MEMS), monolithic integration.

I. INTRODUCTION N RECENT YEARS, monolithically integrated microelectromechanical-systems (MEMS) inertial sensors have attracted extensive attention from academia and industry due to their advantages of small packaging size, high signal-to-noise ratio (SNR), and low cost. They have been widely applied in automotive, navigation, video games, cell phones, and many other consumer electronics products [1]–[15]. Capacitive sensing is the preferred sensing mechanism for MEMS inertial sensors due to its high accuracy, low-temperature dependence, and good compatibility with complementary metal–oxide semiconductor (CMOS) technology. Integrated MEMS inertial sensors can be fabricated using either surface micromachining [2], [3], [6]–[10] or bulk micromachining [11]–[15] of which the bulk CMOS-MEMS technology can achieve higher resolution than its surface micromachining counterpart even with

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Manuscript received May 03, 2010; revised June 17, 2010; accepted July 16, 2010. Date of publication September 23, 2010; date of current version February 09, 2011. This work was supported in part by the NASA/UCF-UF Space Research Initiative, in part by the University of Florida Research Foundation, and in part by the Industrial Technology Research Institute (ITRI) of Taiwan. The associate editor coordinating the review of this paper and approving it for publication was Prof. Gerald Gerlach. H. Sun and H. Xie are with the Department of Electrical and Computer Engineering, University of Florida, Gainesville, FL 32611 USA (e-mail: hzsun@ufl. edu). D. Fang and K. Jia are with Freescale Semiconductor, Tempe, AZ 85284 USA. F. Maarouf is with Qualcomm, San Diego, CA 92121 USA. H. Qu is with the Department of Electrical and Computer Engineering of Oakland University, Rochester, MI 48309 USA. Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/JSEN.2010.2064296

the same footprint. Meanwhile, bulk CMOS-MEMS structures do not have the stress problems that limit the proof mass size and sensing capacitance in thin-film CMOS-MEMS structures. Therefore, the combination of bulk machining and capacitive sensing is a good choice to realize low-cost, moderate-to-high performance, single-chip CMOS-MEMS accelerometers. The sensing capacitance of surface-micromachined accelerometers is typically in the range of 100 fF [1], [10]. Bulk CMOS micromachining, on the other hand, can significantly increase the sensing capacitance by increasing the structure size as well as using bulk silicon as part of sensing capacitors [15], but the capacitance is typically kept in the range of 0.5–2 pF to minimize the chip size. The minimum detectable signal (MDS) is usually determined by the noise floor of the interface circuits. Thus, designing low-noise interface circuits is crucial to the overall performance of the devices. Several circuit architectures have been reported for interfacing with MEMS accelerometers, including switched-capacitor (SC) circuit [7]–[9], [11]–[13], [19], continuous-time current sensing (CTC) [16]–[18], and continuous-time voltage sensing (CTV) [2], [10], [18], [22], [23]. The analysis in [10] proves that the open-loop CTV has the best noise performance theoretically. The chopper-stabilized amplifier reported in [10] yields a noise floor of 50 g/ Hz, which is close to the theoretical limit of the thermal noise of the thin-film accelerometer. However, its power consumption is as high as 30 mW, which is too much for those portable devices with a stringent power budget. There is a tradeoff between the noise level and the power consumption, which poses a serious challenge for trying to obtain low noise and low power consumption at the same time. Bakker et al. reported a nested-chopper architecture that uses two chopper frequencies with one chopping to reduce 1/f noise and the other for removing offset [21]. Using a similar architecture, Fang et al. reported a dual-chopper amplifier (DCA) with one chopping to reduce 1/f noise and the other for minimizing the overall power consumption [22]. With that DCA, a CMOS-MEMS accelerometer with a 50- g/ Hz noise floor at only 1-mW power consumption was demonstrated [22]; the relatively large temperature dependence of that DCA design was later reduced by 55% by optimizing the input transistors [23]. But there were no DCA design details given in either [22] or [23]. In this paper, the DCA that can simultaneously achieve low noise, low power, and low-temperature variation is discussed in detail. The circuitry is integrated with a three-axis CMOSMEMS accelerometer and the performance of the system is characterized.

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Fig. 2. SEM of the three-axis accelerometer.

Fig. 1. Cross-sectional view of the post-CMOS process flow: (a) Backside etch. (b) Backside photoresist coating and front-side anisotropic SiO etch. (c) M4 etch. (d) Deep Si etch and undercut to form a structure with isolation. (e) Anisotropic SiO etch and DRIE etch for comb fingers and mechanical springs. (f) Photoresist ashing for final release.

TABLE I DIMENSIONS OF SENSING ELEMENTS TEST

II. CMOS-MEMS ACCELEROMETER An - accelerometer and a -axis accelerometer are integrated with the interface circuits on a single CMOS chip. The TSMC 4-metal 0.35- m CMOS process is used, and the CMOS foundry service is provided by MOSIS. Of the four metal layers, metal3 and metal4 work as the etch masks for forming the mechanical microstructures, and metal1 and metal2 are used for electrical wiring. The device is fabricated with a post-CMOS micromachining process [15], [24], [25]. The process flow is illustrated in Fig. 1. The backside etch [Fig. 1(a)] defines the thickness of the microstructure, and a thick photoresist layer is coated on the back side as a thermal path in the following steps [Fig. 1(b)]. After anisotropic SiO etching [Fig. 1(b)], wet aluminum etching [Fig. 1(c)], and a deep silicon etching followed by isotropic etching [Fig. 1(d)], the electrical isolation structures are formed. Then, another anisotropic SiO etching plus a deep Si etching defines the springs, comb fingers, and other mechanical structures [Fig. 1(e)]. Finally, the photoresist is removed by using oxygen plasma ashing to release the structures [Fig. 1(f)]. Interested readers can refer to [25] for more details. Fig. 2 shows a die photo and some scanning electron micrographs (SEMs) of a fabricated three-axis accelerometer. The three-axis accelerometer is realized with two proof masses, of which the inplane sensing is based on variable-gap comb fingers and the out-of-plane sensing is achieved with the torsional springs and side-wall capacitances formed by the metal layers in comb fingers. The details of the device are summarized in Table I. Readers who are interested in the sensor design can refer to [15]. Note that the three-axis accelerometer in [15] has only a single proof mass while the three-axis accelerometer reported

here has an - proof mass and a separate proof mass. This proof mass arrangement reduces the cross-axis coupling. III. DCA ARCHITECTURE 1) Noise Analysis: Fig. 3 shows the equivalent model of the capacitive sensing front-end circuit. For the sake of analysis simplicity, only half of the common-source differential pair is schemed, and the input PMOS transistor is shown as , a MOS-bipolar pseudoresistor, a small-signal model. is connected to the gate of the input transistor to provide the proper dc bias while maintaining large ac impedance [20]. The electrical signal at the gate of the input transistor is governed by the following equation: (1)

SUN et al.: LOW-POWER LOW-NOISE DCA FOR CAPACITIVE CMOS-MEMS ACCELEROMETERS

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is the drain-to-source current of of the input transistor, and the input transistor. It can be observed from (2) that a higher ratio of the input transistors means a lower noise level. The length can take the minimum value, but the width cannot be arbitrarily large because the acceleration signal in (1) will be attenuated since the gate capacitance increases when the gate width increases. Therefore, there is an optimal width to obtain the maximum signal-to-noise ratio (SNR), which can be derived by letting (3) Fig. 3. Circuits model of the capacitive-sensing front end.

where is the sensing capacitance, is the parasitic capacitance from wiring, is the gate-to-source capacitance, and is the gate-to-drain capacitance of the input MOS transisis the amplitude of the modulation signal that is aptors, and plied to the sensing capacitors. A gain factor of is put in front of in (1), with the Miller effects taken into consideration. Fig. 3 shows various noise sources appearing in the front end and represent the flicker of the interface circuits. noise and the thermal noise from the input metal–oxides semiis the shot conductor field-effect transistor (MOSFET). is the residue noise noise of the pseudoresistor for dc bias, injected to the sense node from the reference voltage sources for the modulation signals and the corresponding switches, is the noise from the resistive load of the front-end amplifier, in series with the next amplifier stage lumps the and noise from the following stages. In a properly designed ampliand are both negligible since these noises are fier, reduced by a factor of the gain of the first stage when referred to can work as eithe input node. The MOS-bipolar device ther a subthreshold PMOS or a diode-connected pnp transistor, depending on the polarity of . is a shot noise and is negligible compared with other noise sources since the dc leakage current is small during operation. The residue noises from the voltage references and the corresponding switches for generating the modulation signals may be injected into the sensing node. However, for full-bridge sensing capacitors, the residue and , which are two input noises are injected equally to nodes of a fully differential amplifier, so that they cancel each other out. Wu et al. reported a detailed noise analysis [10]. Generally, at low frequency, the flicker noise dominates, while the thermal noise takes it over in high frequency (usually above hundreds of kilohertz) and limits the noise floor eventually. In this design, the modulation frequency is chosen higher than the corner frequency, so only the thermal noise needs to be considered and can be written as (2) where is the Boltzmann constant, is the absolute temperais the carrier mobility of the input transistors, is ture, and are the width and length the gate capacitance density,

Plugging (2) into (3), we can obtain the optimal transistor width which satisfies the following equation: (4) , and are the gate-to-source, gate-to-drain where capacitance of the input transistors, and the parasitic capacitance is the of the metal stray for interconnection, respectively; gain of the amplifier stage; and is 1/3 for ideal long-channel transistors and needs fine tuning during simulation. More details about the derivation can be found in [10]. 2) Tradeoffs Between Noise and Power: The governing equation of a simple open-loop amplifier is given by

(5) represents the product of the dc gain and the bandwhere is the dc gain of the amplifier, width of the amplifier, is its open-loop bandwidth, is the transconductance of the is the load capacitance, and input transistors, and are the carrier mobility, the gate capacitance density, and the size of the input transistor, respectively. The dc bias current is then derived from (5) (6) This is the minimum bias current to meet the gain—bandwidth requirement. So the power consumption of an amplifier can be written as

(7) where is a constant representing the ratio of the total current to the current given in (6), which is the current in a single branch of the differential pair. Open-loop amplifiers and telescopic am2, while folded-cascode ampliplifiers, for instance, have 2, since the current drawn in the current mirrors fiers have needs to be taken into consideration. Despite the variation of of different architectures, is a good assumption

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Fig. 4. Architectures comparison among (a) the single-chopper single stage, (b) the single-chopper dual stage, and (c) the dual-chopper dual-stage amplifiers.

in practical design, since the input differential pair usually conrepresents the power supply and sumes most of the power. is the dc gain of the amplifier. is a constant defined to lump all constants appearing in (7). In real designs, the value of depends on the architecture of the amplifier, and it will make the following analysis very tedious. For the sake of easier understanding, is assumed identical for open-loop and closed-loop amplifiers in the following analysis. It has been mentioned in the previous section that the modulation frequency is above the corner frequency of the thermal and flicker noise, which is normally hundreds of kilohertz, to get rid of the flicker noise. So the operation frequency of the interface stage is much higher than the baseband frequency of the acceleration signal. The single-stage amplifier working at a single high modulation frequency is shown in Fig. 4(a), whose power is rewritten as (8) The equation is rewritten directly from (7) with a proper subscription. Typically, is designed to be close to . Thus, the power consumption of the amplifier is directly proportional . to the square of Since the power of an amplifier is proportional to the quadratic value of its gain, it is beneficial to split a high overall gain to two stages, as shown in Fig. 4(b). Assuming the gains and , respectively, the power of this of the two stages are single-chopper dual-stage architecture is given by

) and the power in this case is stages (i.e., compared to the single-stage archireduced by a factor of tecture. The required overall gain of MEMS accelerometers is usually larger than 100, so the two-stage architecture has a significant advantage in terms of power over the single-stage amplifier for interfacing with MEMS accelerometers. The amplifier working at high frequency has a low noise floor due to the flicker noise reduction. In a well-designed two-stage amplifier, the noise from the first stage dominates. Thus, it may be unnecessary to have the second stage still working at the same high frequency. That is the basic idea of the dual-chopper amplifier (DCA), in which the overall gain is split into two stages and, at the same time, the two stages operate at different modulation frequencies (i.e., two chopping clocks [22]). As shown in Fig. 4(c), the first stage operates at the high chopping frequency and a moderate gain while the second stage operates at the low chopping frequency with a larger gain. Thus, the power of the DCA is written as

(11) and are the gains of the two stages, and where are the width and the length of the input transistors of the second is the load capacitance of the second stage. In this stage, and is chosen at 1 DCA design, the high modulation frequency MHz, higher than the noise corner frequency to minimize the flicker noise. A further increase on the modulation frequency may not have a significant merit of noise reduction, but it has the cost of more power consumption. The low modulation freto avoid aliasing. In this DCA quency is much lower than design, is chosen to be 20 kHz. means a high gain According to (2), (5), and (9), high bandwidth of the first stage and, thus, leads to low input noise, but the cost is significantly high power consumption. So there is a tradeoff between the noise and power. The criterion of optimization is to obtain the minimum value of the product of the total power and total input-referred noise by choosing a proper . It can be derived as (12) By substituting (2), (5), and (11) into (12), the optimized gain of the first stage for the two-stage dual-chopper architecture is (13)

(9) where the two stages are assumed to have the same load and transistor size. Comparing the power consumption of these two architectures by considering the same overall gain, that is, , we have

where is the overall gain. This result is based on the assumption that the noise from the second stage is comparable to that from the first stage when referred to the input node, which is usually the case. The power of the DCA after optimization of the high-frequency gain is then

(10) The two-stage amplifier achieves its minimum power consumption when the overall gain is equally split into the two

(14)


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Fig. 5. DCA system architecture and operation. (a) System architecture. (b) Clock signals in DCA. (c) Operation in the frequency domain.

So the power consumption of the DCA is further reduced by a factor of , compared with the two-stage architecture working at a single high frequency. It is a significant reduction . considering For the CMOS-MEMS accelerometer reported in this paper, based on (13), after taking some practical factors into consid1 MHz, 20 kHz, eration and setting , and 5, the optimized is about 10. high-frequency gain 3) System Design: The architecture and the operational principle of the DCA are shown in Fig. 5. The sensed signal is amplified by two amplification stages and chopped by two fundaand to demodulate the signal back to the mental clocks baseband. The clock frequencies are and , respectively, . A similar nest-chopper architecture has been reand ported in [21] to reduce noise and dc offset. The modulation signals applied on the sensing capacitors are generated by chopping comes from the two dc references, and the switching signal XOR operation of two clocks and , as shown in Fig. 5(b). The employed CMOS-MEMS processing gives the possibility of making two electrically isolated pairs of sensing capacitors for the fully differential amplifier so that the noise from the modulation signal is injected into the two input nodes equally and cancels each other out. There are no switches between the sensing capacitors and the input transistors of the front-end amplifier. This arrangement makes the kT/C noise from switches and the residual spikes during switching, which is an important noise source as mentioned in [21] to the common mode, so they do not play a significant role in this fully differential amplifier. is an open-loop amplifier with a gain of The first stage about 10. The open-loop architecture is believed to have better noise performance because it suffers less from noise folding compared with transimpedance amplifiers and capacitive feedis an ac coupling circuitry back amplifiers [10]. Following and buffers that remove the dc offset from . The capacitor and the MOS-bipolar device work as a high-pass filter whose is 4 pF, which cutoff frequency is set at 2 kHz. The value of

is realized to an on-chip poly-insulator-poly capacitor. Then, the for the first time to move the signal signal is demodulated by - low-pass filter follows with a cutoff freto the band. A quency of 200 kHz, which filters the high-frequency harmonics and high-frequency noises to reduce the noise folding in the next demodulation. Then, the signal is amplified by the second am, which is a capacitive-feedback amplifier plification stage based on an OTA. Two MOS-bipolar pseudoresistors, similar to the ones discussed in Section III-1, are in series to provide high feedback , this impedance. Compared with the open-loop amplifier can provide larger signal swing with closed-loop amplifier good linearity and increase the dynamic range of the system. is low, relatively high gain Since the operating frequency of without adding too much power consumpcan be allowed in and , have the same tion. The offset tuning signals , and they are used to remove the offset due to frequency as the sensing capacitance mismatch. The signal amplified by is then demodulated by , and the buffered output is fed into an off-chip low-pass filter to obtain the baseband signal. Fig. 5(c) shows the operation in the frequency domain. The acceleration signal is modulated to the high modulation freso that the signal moves away from the large flicker quency noise frequency range. Flicker noise dominates the signal’s baseband. After high-frequency chopping, the flicker noise is , and then filtered by the moved to odd harmonics of filter. The signal after is chopped with to demodulate the signal back to the baseband. Of course, there is some power during this procedure. Finally, loss at higher harmonics of the off-chip low-pass filter removes all out-of-band signals and obtains the acceleration signal at the baseband. 4) Temperature Dependence: Another important consideration is the dependence of the performance on temperature variation. The output signal is written as (15)

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Fig. 6. Schematic of A with the PMOS load.

So the temperature coefficient can be expressed as (16) Fig. 7. Schematic of OTA of the second amplifier stage.

There are mainly three sources of the temperature dependence: the amplitude variation of the modulation signal applied to the sensing capacitors and the gain variations of the two amplification stages. The modulation signal is generated by chopping two dc reference voltages, so ideally the reference should be temperature insensitive. It is not a problem if the dc reference comes from a regulated power supply, but in that case, the output signal will be sensitive to the fluctuation of the power line. In this design, a band-gap voltage reference is applied to generate the temperature-independent reference voltage. The second stage is based on capacitive feedback, so the effect of temperature is negligible. Since the first stage of the DCA is an open-loop amplifier is the major source of the without feedback to clamp the gain, temperature dependence. The first version of the DCA reported in [22] is affected a lot by temperature variation. The solution of the problem will be discussed in Section IV. IV. CIRCUITS DESIGN 1) Amplifier Design: The schematic of the first stage is and are cascaded with the input transisshown in Fig. 6. and draw the dc current from tors to have good linearity. the load branch to increase the impedance of the diode-connected load transistors to ensure proper gain. In the early version, the load resistors are realized with two diode-connected NMOS transistors, and the gain of this stage is (17) where and are the transconductances of and and are their static currents, and are their carrier moand is a constant related to tranbility, sistor sizes. If and are of different types, their

carrier mobility mismatch will lead to a significant temperature , which is the case of the first version of the dependence of DCA design [22]. and have been changed from In this DCA design, NMOS to PMOS, as shown in Fig. 6. In this case, the input and load transistors are of the same type, so the temperature dependences of the input and load transistors will cancel each other in (17) less sensitive to temperature variation. out, making The second amplifier stage is a closed-loop capacitive-feedback amplifier based on an operational transconductance amplifier (OTA), whose schematic is plotted in Fig. 7. It is implemented with a fully differential folded-cascode architecture and working in the triode rewhich has two transistors gion to control the common-mode voltage level of the output signal. The input differential pair uses long-channel large-width PMOS transistors to reduce the flicker-noise corner frequency to around 20 kHz. The open-loop gain is designed to be 80 dB with the unity-gain frequency at 20 MHz in order to maintain a good virtual ground at the input node. - Filter: The low-pass - filter is schematically 2) shown in Fig. 8. Source degeneration is applied to the input transistors for better linearity. Two diode-connected transistors with very long channel length work as the load resistors to provide properly high resistance to achieve a cutoff frequency of 200 kHz. That cutoff frequency is low enough to attenuate the high-frequency noise after the first modulation and to keep the phase lagging introduced by this stage acceptable. The capacitor required in this application is 6 pF, which can be realized by on-chip polycapacitors. 3) Design Robustness Consideration: Another practical issue is the robustness of the interface circuits design. During the designing process, the corner analysis in Spectre is run to


Fig. 8. Schematic of the low-pass

G -C filter.

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Fig. 9. Output versus 100-Hz acceleration.

ensure the performance at extreme conditions. Considering the fabrication process variations and the temperature dependence of the first open-loop amplifier stage, external control signals are used to optimize the performance. As mentioned in Section III (3), the offset introduced by the sensing capacitance mismatch is cancelled by an external ac signal. The common-mode voltages of the two amplifiers are provided externally for maximal dynamic range. It will also be worthy in future work to use a capacitance array as the feedback capacitance to make the gain tunable, in order to compensate the gain variation and obtain a stable scale factor. V. EXPERIMENTAL RESULTS The interface circuitry has been fabricated together with a CMOS-MEMS three-axis accelerometer using TSMC 0.35- m 2P4M technology, followed by a post-CMOS micromachining processing. A die photograph has been shown in Fig. 2. The circuitry is not visible because it is covered by a whole piece of Metal3 layer to avoid any circuit detriment during micromachining processing. The acceleration measurements are made on a LDS V-408 shaker that can generate single-tone sinusoidal acceleration. An SR 560 low-noise amplifier with high input impedance and a tunable filter is used to pick up the output signal, minimize the loading effect of other testing equipment, and provide proper low-pass filtering. The cutoff frequency is 10 kHz. A PCB Piezotronics 356A16 reference accelerometer, whose sensitivity is 100 mV/g, is mounted on the shaker to monitor the acceleration. Fig. 9 plots the dynamic responses of the three axes to 100-Hz sinusoidal accelerations. The measured , and axes are 144, 139, and 23.3 mV/g, sensitivity of respectively, as shown in Fig. 9. The linear ranges of the lateral axes are both 11.5 g, and that of the axis is as high as 29 g due to its smaller sensitivity. The spectra of the output signal of the axis and axis in response to 100-Hz acceleration are shown in Fig. 10. The spectrum of the axis is not shown because it looks similar to that of the -axis. The noise floors of the , and axis are 40, 40, and 130 g/ Hz, respectively.

Fig. 10. Spectra of the response to 100-Hz acceleration. (a)

x axis. (b) z axis.

The cross talks between the three axes are measured by monitoring the outputs of the other two axes when the device is excited in a certain axis. The results are shown in Table II.

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TABLE II CROSS TALK AMONG AXES

the power consumption is 12 mW per axis [13]. Colibrys achieves 18 g/ Hz at 2 mW, but the package size is 14.2 mm 14.2 mm [27]. The 40- g/ Hz resolution at only 1-mW power consumption and a 3 mm 3-mm die size (CMOS circuitry included) makes this work a very good balance between the noise, power, and size. VI. CONCLUSION

TABLE III SUMMARY OF ACCELEROMETER CHARACTERISTICS

A novel DCA that realizes low power consumption and low noise level simultaneously has been demonstrated in this paper. The DCA has been integrated with three-axis CMOS-MEMS accelerometers. The combination of single-crystal silicon processing and the DCA ensures an on-chip accelerometer system with 1-mW/axis power consumption and the noise floors of 40, 40, and 130 g/ Hz for all three axes. The temperature coefficient of sensitivity is reduced by the improvement of the first amplifier stage and the application of band-gap voltage reference. The concept of the DCA can be applied to the design of other MEMS sensors, such as micro-gyroscopes and strain sensors. REFERENCES [1] N. Yazdi, F. Ayazi, and K. Najafi, “Micromachined inertial sensors,” Proc. IEEE, vol. 86, no. 8, pp. 1640–1659, Aug. 1998. [2] J. A. Geen, S. J. Sherman, J. F. Chang, and S. R. Lewis, “Single-chip surface micromachined integrated gyroscope with 50 /h Allan deviation,” IEEE J. Solid-State Circuits, vol. 37, no. 12, pp. 1860–1866, Dec. 2002. [3] Analog Devices, “ADXL103/ADXL203 Single/dual axis accelerometer datasheet” Cambridge, MA, 2004. [4] ST Microelectronics, “LIS244AL 2-axis- 2 g ultracompact linear accelerometer datashee,” Switzerland, 2009. [5] MXA2050A Dual Axis Accelerometer Datasheet. North Andover, MA: MEMSIC, 2007. [6] W. Yun, R. T. Howe, and P. R. Gray, “Surface micromachined, digitally force-balanced accelerometer with integrated CMOS detection circuitry,” in Proc. 5th IEEE Tech. Dig. Solid-State Sensor and Actuator Workshop, 1992, pp. 126–131. [7] C. Lu, M. Lemkin, and B. E. Boser, “A monolithic surface micromachined accelerometer with digital output,” in Proc. IEEE Solid-State Circuits Conf. Dig. Tech. Papers, 1995, pp. 160–161. [8] M. Lemkin and B. E. Boser, “A three-axis micromachined accelerometer with a CMOS position-sense interface and digital offset-trim electronics,” IEEE J. Solid-State Circuits, vol. 34, no. 4, pp. 456–468, Apr. 1999. [9] X. Jiang, F. Wang, M. Kraft, and B. E. Boser, “An integrated surface micromachined capacitive lateral accelerometer with 2 g/ Hz resolution,” in Proc. Solid-State Sensor, Actuator and Microsystems Workshop, Hilton Head Island, SC, 2002, pp. 202–205. [10] J. Wu, G. K. Fedder, and L. R. Carley, “A low-noise low-offset capacitive sensing amplifier for a 50 g/ Hz monolithic CMOS MEMS accelerometer,” IEEE J. Solid-State Circuits, vol. 39, no. 5, pp. 722–730, May 2004. [11] N. Yazdi and K. Najafi, “An interface IC for a capacitive silicon g accelerometer,” in Proc. IEEE Solid-State Circuits Conf., Dig. Tech. Papers, 1999, pp. 132–133. [12] H. Kulah, J. Chae, N. Yazdi, and K. Najafi, “A multi-step electromechanical 16 converter for micro-g capacitive accelerometers,” in Proc. IEEE Solid-State Circuits Conf. Dig. Tech. Papers, 2003, pp. 202–488. [13] J. Chae, H. Kulah, and K. Najafi, “A monolithic three-axis micro-g micromachined silicon capacitive accelerometer,” J. Microelectromech. Syst., vol. 14, no. 2, pp. 235–242, 2005. [14] H. Takao, H. Fukumoto, and M. Ishida, “A CMOS integrated threeaxis accelerometer fabricated with commercial submicrometer CMOS technology and bulk-micromachining,” IEEE Trans. Electron Devices, vol. 48, no. 9, pp. 1961–1968, Sep. 2001. [15] H. Qu, D. Fang, and H. Xie, “A monolithic CMOS-MEMS 3-axis accelerometer with a low-noise, low-power dual-chopper amplifier,” IEEE Sensors J., vol. 8, no. 9, pp. 1511–1518, Sep. 2008.

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Fig. 11. Comparisons of the noise and power consumption of this paper with other accelerometers.

The axis accelerometer is based on imbalanced torsional force in the axis, so it is sensitive to the acceleration in the axis, especially when the spring constant is lower than the designed value due to processing imperfections. It can be further reduced by better process control. The characteristics of the three-axis accelerometer are summarized in Table III. Fig. 11 compares the noise and power consumption of this paper with the previous work [10], [13] and some commercially available accelerometers [3]–[5], [26], [27]. Chae et al. reported 4- g/ Hz resolution, but the device size is 7 mm 9 mm and


[16] J. Salvia, P. Lajevardi, M. Hemkat, and B. Mrumann, “A 56M

CMOS TIA for MEMS applications,” in Proc. IEEE Custom Integrated Circuits Conf., 2009, pp. 199–202. [17] A. Sharma, M. F. Zaman, and F. Ayazi, “A 104-dB dynamic range transimpedance-based CMOS ASIC for tuning fork microgyroscopes,” IEEE J. Solid-State Circuits, vol. 42, no. 8, pp. 1790–1802, Aug. 2007. [18] G. K. Fedder, “Simulation of microelectromechanical systems,” Ph.D. dissertation, Elect. Eng. Comput. Sci. Dept., Univ. California at Berkeley, Berkeley, CA, 1994. [19] H. Kulah, A. Salian, N. Yazdi, and K. Najafi, “A 5 V closed-loop second order sigma–delta micro-g micro accelerometer,” in Proc. Solid-State Sensors and Actuators Workshop, Hilton Head Island, SC, 2002, pp. 219–222. [20] R. R. Harrison and C. Charles, “A low-power low-noise CMOS amplifier for neural recording applications,” IEEE J. Solid-State Circuits, vol. 38, no. 6, pp. 958–965, Jun. 2003. [21] A. Bakker, K. Thiele, and J. H. Huijsing, “A CMOS nested-chopper instrumentation amplifier with 100-nV offset,” IEEE J. Solid-State Circuits, vol. 35, no. 12, pp. 1877–1883, Dec. 2000. [22] D. Fang, H. Qu, and H. Xie, “A 1 mW dual-chopper amplifier for a 50 g/Hz monolithic CMOS-MEMS capacitive accelerometer,” in Proc. Symp. VLSI Circuits. Dig. Tech. Papers, 2006, pp. 59–60. [23] H. Sun, F. Maarouf, D. Fang, K. Jia, and H. Xie, “An improved lowpower low-noise dual-chopper amplifier for capacitive CMOS-MEMS accelerometers,” in Proc. 3rd IEEE Int. Conf. Nano/Micro Engineered and Molecular Systems, 2008, pp. 1075–1080. [24] H. Qu, D. Fang, and H. Xie, “A single-crystal silicon 3-axis CMOSMEMS accelerometer,” in Proc. IEEE Sensors, 2004, pp. 661–664. [25] H. Qu and H. Xie, “Process development for CMOS-MEMS sensors with robust electrically isolated bulk silicon microstructures,” J. Microelectromech. Syst., vol. 16, no. 5, pp. 1152–1161, Oct. 2007. [26] Kionix Inc., “KXP94 2 g tri-axis accelerometer specifications,” Ithaca, NY, 2007. [27] Colibrys Ltd., “MS8000.D datasheet,” Switzerland.

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Kemiao Jia (S’07) was born in Shenyang, Liaoning Province, China, in 1982. He received the B.S. and M.S. degrees in electrical engineering from Zhejiang University, Hangzhou, China, in 2002 and 2005, respectively, and the Ph.D. degree in electrical engineering from the University of Florida, Gainesville. His research interests include the development and application of optical and inertial microeletromechanical-systems devices. Currently, he is a MEMS Design Engineer with Freescale Semiconductors, Tempe, AZ. He has authored and coauthored multiple U.S. and Chinese patents.

Fares Maarouf (M’09) received the M.S. degree in electrical and computer engineering from the University of Florida, Gainesville, in 2007, and the B.E. degree in electrical engineering from American University of Beirut, Beirut, Lebanon, in 2005. He is a Senior Engineer in mixed-signal integratedcircuit design at Qualcomm, San Diego, CA. Mr. Maarouf received the Dean’s Honor List Award several times. He also won the Achievement Award at the University of Florida.

Hongzhi Sun (S’07) received the B.S. degree in materials science and engineering from Zhejiang University, Hangzhou, China, in 2005 and the M.S. degree in electrical engineering from the University of Florida, Gainesville, in 2008, where he is currently pursuing the Ph.D. degree in electrical engineering. His research interest is the interface design for complementary metal–oxide-semiconductor–microelectromechanical-system inertial sensors. Mr. Sun is a member of Eta Kappa Nu.

Hongwei Qu (M’06) received the B.S. and M.S. degrees in electrical engineering from Tianjin University, Tianjin, China, in 1988 and 1993, respectively, and the Ph.D. degree in electrical engineering from the University of Florida, Gainesville, in 2006. He also received the M.S. degree in applied physics from Florida International University, Miami, FL, in 2002, with thesis research on ferroelectric thin films. Currently, he is an Assistant Professor in the Department of Electrical and Computer Engineering, Oakland University, Rochester, MI. From 1993 to 2000, he was a faculty member at the Electrical Engineering Department, Tianjin University, where he was involved in research on a variety of solid-state sensors. His research involves microelectromechanical-systems (MEMS) technology and devices, with a focus on complementary metal–oxide-semiconductor–MEMS integration, inertial sensors, as well as electrothermal and electrostatic actuators. He also has expertise in other MEMS devices, such as optical and radio-frequency MEMS. He has a particular interest in biomedical applications of MEMS. He has been published in more than 40 publications.

Deyou Fang received the B.E. degree in automation control from the University of Electronic Science and Technology of China, Chengdu, China, in 1993, and the M.S. and Ph.D. degrees in electrical and computer engineering from the University of Florida, Gainesville, in 2003 and 2006, respectively. From 1993 to 1996, he worked on the design and development of power station control systems. From 1996 to 2001, he was with the Central R&D Department at Huawei Technologies Co. Ltd., Shenzhen, China, where he was involved in the design and implementation of communication equipment, including telecommunication switches, Global System for Mobile Communications, and code-division multiple-access wireless systems. Since 2006, he has been a Member of the Technical Staff with Freescale Semiconductor, Tempe, AZ, where he has been working on analog/mixed-signal integrated circuits and systems design for automotive microelectromechanical-systems accelerometers and gyroscopes.

Huikai Xie (SM’07) received the M.S. degree in electrooptics from Tufts University, Medford, MA, in 1998, and the Ph.D. degree in electrical and computer engineering from Carnegie Mellon University, Pittsburgh, PA, in 2002. He is an Associate Professor in the Department of Electrical and Computer Engineering, University of Florida, Gainesville. From 1992 to 1996, he was a faculty member at the Institute of Microelectronics at Tsinghua University, Beijing, China. He has published many technical papers and has had seven U.S. patents granted and 15 U.S. patents pending. His current research interests include microelectromechanical systems (MEMS)/nanoelectromechanical systems, integrated inertial sensors, sensor interface circuits, microactuators, integrated power passives, carbon nanotube-complementary metal–oxide-semiconductor integration, optical MEMS, biophotonics, infrared (IR) sensors, and IR spectroscopy.

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