A Low Power Pipeline ADC with Digital Correction Logic

2017 2nd International Conference for Convergence in Technology (I2CT) Siddhant College of Engineering, Pune , India. Apr 7-9, 2017

A Low Power Pipeline ADC with Digital Correction Logic S. I. Bakhtar

Dr. S. S. Dalu

Assistant Professor Department of Electronics & Telecommunication Engg, PRMCEAM, Amravati (Maharashtra), India [email protected]

Assistant Professor Department of Electronics & Telecommunication Engg, Government Polytechnic, Yavatmal (Maharashtra), India [email protected]

Abstract - Analog to digital converters are very important blocks which are currently used in many applications to improve digital systems, with respect to analog systems. The Pipeline ADC has become very popular because of its lower power consumption and reasonably fast conversion rate as compared to other ADC architectures. The pipeline ADC accomplishes this by a major reduction in the amount of circuitry required in the conversion process. Low power dissipation is very important factor in every ADC design. To reduce power consumption, switching op-amps can be introduced in several pipeline stages. These switching op-amps should be provided with short turn-on time for low power consumption in pipeline ADC. The errors which are caused by offsets in the comparator can be cancelled out by using a digital error correction logic.

Fig. 1. General Pipeline ADC

multiplying DACs, implemented in most cases as switched capacitor (SC) circuits including an operational amplifier. The analog input signal is sampled and hold by the S/H block. For each successive stage, the input signal is converted to digital part by an ADC which is then applied to the DAC. Finally, the DAC output which can be Vref+, VCM (Common mode voltage) or Vref- is subtracted from the input and the result is then amplified. The digital part of the ADC takes the outputs from stages and allows them with a particular delay. Then the decisions are taken by simply adding together in a 1.5 bit/stage fashion to give an 8 bit output word. The analog blocks should be implemented in such a manner so that it will increase the power supply rejection ratio and decrease the effect of noise and harmonics. The plot of residue transfer function is shown in Fig. 2.

Index Terms: Pipeline ADC, low power, pipeline, op-amps

I. INTRODUCTION Analog to digital converters are one of the most essential elements in mixed signal circuits. Pipelined ADCs are most popularly used for converting medium to high resolution with fast conversion rate. Pipelined ADCs are used in various applications such as wired or wireless systems, flat panel displays, cable head-ends and in various HDTVs. Among various ADC architectures, although SAR [1] and Flash [2] ADCs exhibit good power efficiency, pipeline architecture provides good sampling rate when compared with SAR architecture and low input capacitance when compared with Flash architecture. Hence, ideas to reduce power consumption of op-amps can be used such as sharing of op-amp, and current reuse of op-amp [10]. II. PIPELINE ADC ARCHITECTURE Fig. 1 shows general pipeline ADC. A pipeline stage consist of sample and hold circuit, analog-to-digital converter (ADC) and digital-to-analog converter (DAC). The performance of ADC is determined by the properties of the quantization process performing comparators, which are usually implemented using dynamic topologies. The performance of a pipeline ADC as a whole is limited by the

Fig. 2. 1.5 bits per stage residue plot.

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III. DIGITAL CORRECTION LOGIC Each stage provides a 2 bit digital word which is sent to the digital correction block. The digital correction block contains a simple shift register and digital correction logic circuits. The 1 bit redundancy in each stage is usually referred to as the 0.5 bit redundancy, thus the term 1.5 bits/stage. This redundancy compensates for component non idealities. When the initial sample is clocked through all stages then the first digital output is available from the digital correction block. During this latency period samples are continually taken. Individual stage outputs are stored in the shift register. Thus a complete 8 bit digital output is available on each successive clock cycle, after the initial latency period. The output of the shift register is sent to the digital correction logic. In pipeline ADC, digital redundancy is utilized to compensate sub ADC errors. As a result, twice as many bits are generated than required for the output. A digital correction logic is required to produce the correct output. The concept of the correction logic is represented in Fig. 3. The outputs of the previous stages are stored in the register until stage N has its output available. The collected output bits are then added using a 1bit overlap methodology as shown in Fig. 3.

Fig. 4. Mathematics of digital correction.

The errors can be cancelled out by using a digital error correction logic which are caused by offsets in the comparator. The percentage of comparator errors which can be cancelled out depends upon bits in each stage design. However for 1.5 bit per stage architecture comparator offsets can be handled up to ¼ VFS (Full Scale Voltage). There is probability of errors when the next stage in the ADC cannot convert an out-of-range signal. The output bits are not useful without considering digital correction. Digital correction contains two parts: circuit delay and error correction. Since the delays which are inherent in a pipeline architecture so the most significant bits are provided with a few clock cycles before the least significant bits, hence in order to align the bits in time, a circuit delay is required. The circuit delay can be designed by clocked D-latches because every successive stage is inversely clocked hence there is no necessity to use Flip-flops.

A simple example for the binary addition is calculated as shown in Fig. 4. Z = D

(1)

Y= B  C

(2)

X =A+B•C

(3)

IV. SIMULINK RESULTS In order to achieve the design objectives, extensive circuit analysis and simulations need to be performed to guide the sizing of transistors in each of the ADC components. In this section, simulation of various ADC components is done in MATLAB/Simulink environment, which speeds up simulation results. A key feature of MATLAB/Simulink is the ability to describe circuit blocks in discrete time operation, where circuit responses to inputs are only calculated at clock edges therefore increasing the speed of the simulation. Other relevant features of Simulink include the creation of hierarchical block diagrams, an extensive collection of functions and data functions, and flexible simulation time step control. None of one bit ADC have ideal performance. Non idealities associated with the Sub-ADC’s, Sub-DAC’s and gain stages corresponds to error in overall pipeline ADC performance. Hence one has to find means to tolerate/correct errors. Important sources of errors are:

To perform the mathematical operation shown in Fig. 4, it is broken down and implemented using logic gates. The operation in equation is performed by a simple XOR. The CARRY-BIT logic performs the AND/OR operation in equation 1- 3.

1. Sub ADC errors comparator offset. 2. Gain stage offset. 3. Gain stage gain error. 4. Sub DAC error.

Fig. 3. Concept of digital correction.

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A. Pipeline Stage Model (1.5 Bit Per Stage) The advantage of the 1.5-bit per stage architecture is that it has a redundancy of half bit in each stage in correction process and it is advantageous in the comparators without the residue voltage exceeding the full-scale range.

(c)

Fig. 6. Output of 1.5 bits per stage (bps) Pipeline ADC model (a) Dout

(b) Residue 1

(c) Residue 2

(d) Residue 3

Another advantage realized by relaxing the comparator offset requirements is that the comparator can be optimized for speed. Here the comparator threshold levels are placed strategically and the gain is set to G = 2.Thus effective number of bits is,

Fig. 5. 1.5 bits per stage (bps) Pipeline ADC model (2 Comparators per stage).

Beff = log2G = 1

-------- (4)

and the 1.5 bits per stage corresponds to the number of bits as, B = log2 ( 2+ 1 ) = 1.589 ------- (5) This results in redundancy of 1.5 bits. All the three stages are set with the comparator offset values and the overall transfer curve (Dout) has the characteristics of no missing codes but there exists some DNL (differential nonlinearity) error.

(a)

B. Pipeline ADC (2 bits per stage) Case 1: Second stage gain < Number of bits from first stage. Fig. 7 and 8 represent the simulink model and the corresponding output of the Case1 where second stage gain is less than number of bits from first stage. Output mainly consists of ADC characteristics and ADC error. (b)

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In this module of 2 bits per stage the gain for residue to be processed by second stage is less than 2B1. Here gain for the second stage is G2 = 1. The gain processed by the first stage as shown in Fig. 8a is 4 and the corresponding error plot is as shown in Fig. 8b. Case 2: Gain of First stage < Number of bits Fig. 9 and 10 represent the simulink model and the corresponding output of the Case 2 where first stage gain is less than number of bits from first stage. Output mainly consists of ADC Dout, Residue 1 and Residue 2.

Fig. 7. Pipeline ADC 2 bits per stage model.

Fig. 9. Pipeline ADC 2 bits per stage Digital Correction.

(a)

(b)

(a)

Fig. 8. O/P of Pipeline ADC 2 bits per stage (a) ADC Characteristics (b) ADC Error.

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Fig. 12. The corrected output is more accurate compared to the normal because of the saturation block.

(b)

Fig.11. Pipeline ADC Gain Correction model.

(c) Fig. 10. Output of Pipeline ADC 2 bits per stage Digital Correction. (a) ADC Dout. (b) Residue 1 (c) Residue 2.

In this module of two bits per stage pipeline ADC, the number of bits from the first pipeline stage is greater than the gain which is used to correct the output for the processing of the later stages i.e. G1= 2 < 2B1 = (2^2) = 4. As seen from Residue 1 output it exists within the input range of next stage, thus resulting in non integer effective resolution but in this case as G1 = 2 therefore only one bit resolution exists from first stage. Thus, inspite of comparator offset there exists no overall error in the final output.

(a)

C. Pipeline ADC Gain Correction Model This simulation is done for correcting the gain as shown in Fig. 12. The normal output Dout is obtained from two signals, namely, the input signal and the signal obtained after the product block. Because of this the output may consists of some errors. The corrected output has two input signals, namely the input signal and the second stage obtained after the sum block. The residue signal is saturated by saturation block and this saturation block limits the error signal output to ± Verror/2 where Verror is the full scale voltage range. The normal and the corrected output are as shown in

(b) Fig. 12. Output of Pipeline ADC Gain Correction model. (a) Corrected Output (b) Residue.

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[13] M. Vadipour, C. Chen, A. Yazdi, M. Nariman, T. Li, P. Kilcoyne, and H. Darabi, ―A 2.1 mW/3.2 mW delay-compensated GSM/WCDMA sigma-delta analog-digital converter,‖ in Symp. VLSI Circuits Dig. Tech. Papers, 2008, pp. 180–181. [14] L. Bos, G. Vandersteen, J. Ryckaert, P. Rombouts, Y. Rolain, and G. van der Plas, ―A multirate 3.4-to-6.8 mW 85-to-66 dB DR GSM/Bluetooth/ UMTS cascade DT in 90 nm digital CMOS,‖ in ISSCC Dig. Tech. Papers, Feb. 2009, pp. 176–177. [15] P. Crombez, G. Van der Plas, M. Steyaert, and J. Craninckx, ―A 500 kHz-10 MHz multimode power-performance scalable 83-to-67 dB DR CT in 90 nm digital CMOS with flexible analog core circuitry,‖ in Symp. VLSI Circuits Dig. Tech. Papers, 2009, pp. 70–71. [16] Siddhartha Devarajan, Larry Singer, Dan Kelly, Steven Decker, Abhishek Kamath & Paul Wilkins, ―16 Bit,125MS/s, 385mW,78.7dB SNR CMOS Pipeline ADC‖, IEEE Journal Of Solid-State Circuits, Vol. 44, No. 12, December 2009. [17] Ahmed M. A. Ali, Member, IEEE, Andrew (Andy) Morgan, Christopher Dillon, Greg Patterson, Scott Puckett, Paritosh Bhoraskar, Member, IEEE, HuseyinDinc, Mike Hensley, Russell Stop, Scott Bardsley, David Lattimore, Jeff Bray, Carroll Speir, and Robert Sneed, ―A 16-bit 250-MS/s IF Sampling Pipelined ADC With Background Calibration‖, IEEE Journal of Solid-State Circuits, Vol. 45, No. 12, December 2010. [18] Sunghyuk Lee, Student Member, IEEE, Anantha P. Chandrakasan, Fellow, IEEE, and Hae-Seung Lee, Fellow, IEEE,” A 12 b 5-to-50 MS/s 0.5to1 V Voltage ScalableZero-Crossing Based Pipelined ADC‖, IEEE Journal Of Solid-State Circuits, Vol. 47, No. 7, July 2012. [19] Mohammad Taherzadeh-Sani & Anas A. Hamoui, ―A Reconfigurable and Power-Scalable 10–12 Bit0.4–44 MS/s Pipelined ADC With 0.35–0.5 pJ/Stepin 1.2 V 90 nm Digital CMOS‖, IEEE Transactions On Circuits And Systems - I: Regular Papers, Vol. 60, No. 1, January 2013. [20] Bing-Nan Fang and Jieh-Tsorng Wu, Senior Member, IEEE,” A 10Bit 300-MS/s Pipelined ADC with Digital Calibration and Digital Bias Generation‖, IEEE Journal of Solid-State Circuits, Vol. 48, No. 3, March 2013. [21] Chien-Jian Tseng, Student Member, IEEE, Chieh-Fan Lai,AndHsinShu Chen, Member, IEEE, ―A 6-Bit 1 Gs/S Pipeline ADC Using IncompleteSettlingwith Background Sampling-Point Calibration‖ IEEE Transactions On Circuits And Systems—I: Regular Papers, Vol. 61, No. 10, October 2014

V. CONCLUSION Compared to state-of-the-art power-efficient reconfigurable pipelined ADCs, this ADC provides a large bandwidthresolution reconfigurability space, while maintaining a highly competitive figure of merit. To achieve such lowpower performance, this ADC utilized: 1) wide-swing lowpower pseudo-cascode-compensated opamps; 2) switchedcapacitor dynamic comparators with low input capacitance (input-loading effect); and 3) a low-power digital correction technique. ACKNOWLEDGMENT The authors would like to thank members of Applied Electronics Research Lab, Sant Gadge Baba Amravati University, Amravati for access to their research lab platform. The authors would also like to thank Dr. M. S. Ali, Principal, Prof Ram Meghe College of Engineering & Management, Badnera for helpful discussions.

REFERENCES [1]

G. Geelen, E. Paulus, D. Simanjuntak, H. Pastoor, and R. Verlinden,

―A 90 nm CMOS 1.2 V 10 b power and speed programmable pipelined ADC with 0.5 pJ/conversion-step,‖ in ISSCC Dig. Tech. Papers, Feb. 2006, pp. 214–215. [2] B. Xia, A. Valdes-Garcia, and E. Sanchez-Sinencio, ―A 10-bit 44 Ms/s 20 mW configurable time-interleaved pipeline ADC for an 802.11 b/bluetooth dual-mode receiver,‖ IEEE J. Solid-State Circuits, vol. 41, no. 3, pp. 530–539, Mar. 2006. [3] Y.-J. Kim, H.-C. Choi, S.-W. Yoo, S.-H. Lee, D.-Y. Chung, K.-H. Moon, H.-J. Park, and J.-W. Kim, ―Are-configurable 0.5 V to 1.2 V, 10 MS/s to 100 MS/s, low-power 10 b 0.13 um CMOS pipeline ADC,‖ in Proc. Custom Integr. Circuits Conference (CICC), San Jose, CA, 2007, pp. 185–188. [4] I. Ahmed and D. A. Johns, ―A high bandwidth power scalable subsampling 10-bit pipelined ADC with embedded sample and hold,‖ IEEE J. Solid-State Circuits, vol. 43, no. 7, pp. 1638–1647, Jul. 2008. [5] I. Ahmed and D. A. Johns, ―A 50-MS/s (35 mW) to 1-kS/s (15 W) power scalable 10-bit pipelined ADC using rapid power-on opamps and minimal bias current variation,‖ IEEE J. Solid-State Circuits, vol. 40, no. 12, pp. 2446–2455, Dec. 2005. [6] T. N. Andersen, B. Hernes, A. Briskemyr, F. Telsto, J. Bjornsen, T. E. Bonnerud, and O. Moldsvor, ―A cost-efficient high-speed 12-bit pipeline ADC in 0.18-um digital CMOS,‖ IEEE J. Solid-State Circuits, vol. 40, no. 7, pp. 1506–1513, Jul. 2005. [7] W. Audoglio, E. Zuffetti, G. Cesura, and R. Castello, ―A 6–10 bits reconfigurable 20 MS/s digitally enhanced pipelined ADC for multistandard wireless terminals,‖ in Proc. Eur. Solid-State Circuits Conf., 2006, pp. 496–499. [8] M. Anderson, K. Norling, A. Dreyfert, and J. Yuan, ―A reconfigurable pipelined ADC in 0.18 um CMOS,‖ in Symp. VLSI Circuits Dig. Tech. Papers, 2005, pp. 326–329. [9] K. Gulati and H.-S. Lee, ―A low-power reconfigurable analog-todigital converter,‖ IEEE J. Solid-State Circuits, vol. 36, no. 12, pp. 1900–1911, Dec. 2001. [10] T. Christen, T. Burger, and Q. Huang, ―A 0.13 mm CMOS EDGE/ UMTS/WLAN tri-mode ADC with dB THD,‖ in ISSCC Dig. Tech. Papers, Feb. 2007, pp. 240–241. [11] S. Ouzounov, R. van Veldhoven, C. Bastiaansen, K. Vongehr, R. van Wegberg, G. Geelen, L. Breems, and A. van Roermund, ―A 1.2 V 121- Mode CT modulator for wireless receivers in 90 nm CMOS,‖ in ISSCC Dig. Tech. Papers, Feb. 2007, pp. 242–243. [12] Y. Fujimoto, Y. Kanazawa, P. Lore, and M. Miyamoto, ―An 80/100 MS/s 76.3/70.1 dB SNDR ADC for digital TV receivers,‖ in ISSCC Dig. Tech. Papers, Feb. 2006, pp. 76–77.

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