Backtrack is the process of removing a signal assignment which is found to cause a ... Multiple backtrace is a technique used to reduce the number of backtracks ...
A Method of High-quality Transition Fault ATPG for Scan Circuits
(Haupt)-Seminar: Algorithms for Design-Automation - Mastering Nanoelectronic Systems Summer Semester 2007
Author: Zhe Wang Advisor: Dipl.-Inf. Stefan Holst
July 3rd, 2007
Table of Contents 1
2
3
Introduction................................................................................................................. 1 1.1
Models for delay fault......................................................................................... 2
1.2
Test for transition fault........................................................................................ 3
1.3
Scan circuits and broad-side testing.................................................................... 3
Preliminaries ............................................................................................................... 5 2.1
Time expansion circuit for restricted broad-side testing..................................... 5
2.2
SDQL – a metric for delay fault test quality....................................................... 6
2.3
Basics of combinational ATPG .......................................................................... 8
2.3.1
D-algorithm................................................................................................. 9
2.3.2
PODEM..................................................................................................... 11
2.3.3
FAN........................................................................................................... 12
2.3.4
SOCRATES .............................................................................................. 13
Proposed ATPG Algorithms ..................................................................................... 14 3.1
Algorithm selection........................................................................................... 14
3.2
Propagation-first algorithm............................................................................... 15
3.3
Activation-first algorithm ................................................................................. 16
3.4
Overall ATPG procedure .................................................................................. 17
4
Result and discussion................................................................................................ 17
5
Summary ................................................................................................................... 19
References......................................................................................................................... 19
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1 Introduction Today’s VLSI circuits have become extremely large and fast. To achieve better performance, higher operating rates with smaller clock period and transistors with smaller geometry size have used in the design and fabrication process of VLSI circuits, respectively. These trends can put manufactured circuits into a growing risk of timingrelated failures [Hama06]. For example, defects like resistive opens and bridges, crosstalk, and process variation may cause additional delays in circuits [Chen00, Mitr04]. If the combinational delay of a manufactured circuit exceeds the specified time period, the circuit is considered to have a delay fault [Krst98]. To deal with this risk, testing for delay fault is getting more important. Particularly, detecting errors caused by small delay faults is of major concern. The effect of a small delay fault in a circuit is illustrated in Fig. 1. A, B, C and D are paths in the circuit. Consider Fig. 1 (b) as a conventional design with a lower clock rate and (c) as a modern design with a higher clock rate. Suppose a delay with size 1.5ns caused by some defect may propagate along A, B, C or D. We see that the chance for the delay to cause an error behavior in circuit (b) is small, since the fault is only observable when propagated along path C, a longest path with greatest combinational delay. This is not the case for circuit (c), whose paths are of smaller delay (thus higher clock rate can be achieved). The same delay fault has a much bigger chance to cause an error in a circuit like (c), since it will be observed when propagated through path B, C, or D. Things are even worse, if we let the fault propagate along path A in our test for circuit (b), leaving it undetected. The problem is that small delay faults are causing more problems in today’s manufactured circuits, and they can only be detected by properly designed test patterns which propagate a fault along long paths. Therefore, generating high-quality tests capable of detecting small delay faults is an important task of today’s delay testing.
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Fig. 1 Effect of small delay fault. (a) A fault and possible propagation paths in a combinational circuit. (b) Situation for a slower circuit. (c) Situation for a faster circuit. This report is organized as follows: In the rest part of this section, models of delay fault, especially the transition fault model, and test application methods of transition fault test using scan circuits are introduced. Section 2 explains the basis of the proposed ATPG method, including a time expansion circuit to be used for ATPG, the statistical delay quality model to evaluate delay test quality, and the concepts of combinational ATPG algorithms. The proposed ATPG algorithms for transition fault are explained in section 3. In section 4, experimental results of the proposed ATPG method and discussions on the method are presented. Section 5 summarizes this report.
1.1 Models for delay fault To generate a test pattern for a delay fault, the fault has to be modeled first. There are two major models for delay faults. The path delay fault model [Smith85] focuses on the aggregate delay effect of gates and signal lines along a path in the circuit under test (CUT). Thus if it takes a signal to propagate along a path longer than a specified time period, e.g. system clock period, the path is considered to have a delay fault. This model is a global delay fault model since it takes an entire path into account. The main drawback of the model is the huge number of possible faults in a circuit. If the circuit contains n signal lines, the number of possible faulty paths can be n2 or exponential to n [Jaya03], which makes testing practically impossible in a big circuit. Tests based on path delay fault model therefore target mainly at critical paths only. However, this model is still not quite easy to use because of the difficulty to identify and analyze critical paths [Kaji06]. The transition fault model [Waic87], on the other hand, is a local fault model similar to the stuck-at fault model. A transition fault on signal line l makes the signal change on l slow, which may cause a signal transition on l unable to reach a flip-flop or an output pin within the desired time. For every line in a circuit, there are two possible faults: slow-torise (STR) and slow-to-fall (STF). An example of a STR fault on output line c of an AND gate is given in Fig. 2. As we can see, the fault causes the signal on c to take a longer time (2 ns in this example) to change from 0 to 1 than normal. The major advantage of this model is that the number of possible faults grows linearly with circuit size. In a
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circuit with n lines, there are 2n possible transition faults altogether. Moreover, the similarity to stuck-at fault model indicates that it may be possible to obtain test patterns for transition fault model by extending an automatic test pattern generation (ATPG) program for stuck-at faults. One of the disadvantages of transition fault model is that the size of a delay is not considered. Because the detectable delay size is dependent on the length of the path on which the fault is propagated, and the path is sensitized by a generated test pattern, a transition fault ATPG program can not guarantee to detect an arbitrarily small delay [Kaji06]. Transition fault model is widely used in industry. In this report, we will concentrate on test generation for transition fault.
Fig. 2 Transition fault (STR).
1.2 Test for transition fault In order to detect a transition fault, a two-pattern test is generally needed. In this report, a test pattern is also referred to as a test vector. The first pattern (V1) initializes the fault site (target signal line) to an initial value, which is 0 in the case of a STR fault, so that a desired transition to 1 at the fault site may happen later. The tasks of the second pattern (V2) are: (1) Activate the fault by creating a signal transition at the fault site, which is 1 in the case of a STR fault; (2) Propagate the fault effect, i.e. signal transition, to an observable output. After applying the two patterns, in the case of a STR fault, we can detect the fault by observing a stuck-at-0 fault at the output, provided that our observation was made in time.
1.3 Scan circuits and broad-side testing To apply test patterns and observe circuit responses in a large sequential circuit, the technique of scan design is widely used in industry. Scan design reduces a sequential circuit into combinational circuits and provides us with controllability and observability for flip-flops in each combinational circuit. This is done by adding a test mode into the circuit during the design phase, making flop-flops in the circuit form big shift registers, and adding hardware such as multiplexers and pins for test control and test data input and output. A conventional scan circuit is shown in Fig. 3. A test pattern is (partly) scanned bit by bit into scan flip-flops (SFFs), and the combinational circuit’s response is scanned out in the same way. Moreover, SFFs can hold only one test pattern at the same time in a conventional scan circuit.
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Fig. 3 Conventional scan circuit. When applying a two-pattern test for transition fault in a conventional scan circuit, it is impossible to shift the second pattern (V2) into SFFs bit by bit, because every shift operation changes the values inside the SFFs, which feedback the combinational circuit directly. If we shift more than once, the state of the circuit initialized by the first pattern (V1) will be ruined. Therefore, either we shift in only one bit, or we do not shift in anything at all, but let the circuit’s response to V1 be our V2. The former method is called skewed-load testing [Savir92] and the latter is called broad-side testing [Savir94]. It should be noticed that in both methods, it is important to capture the circuit’s response to V2 in order to observe a small delay fault. Obviously, the earliest time to make our observations should be one system clock period after applying V2. Therefore to capture circuit’s response to V2 at the system speed, which is referred to as at-speed testing [Bush00], is essential for transition fault test using scan circuits. In a skewed-load testing, after scanning in PPI bits and setting PI bits of V1, the circuit is initialized. An additional scan clock is applied while the circuit is still in the scan mode, producing (PPI bits of) V2 as a one-bit shifted version of PPI bits of V1. After scanning in PPI bits and setting PI bits of V2, the circuit is set to normal mode and is clocked once so that the outputs can be observed in either primary output (PO) or scan flip-flops. One drawback of this method lies in the difficulty to manipulate test control signal and to apply different clock signals within an interval corresponding at-speed [Jaya03, Kaji06]. In a broad-side testing, V1 is scanned in as usual, but V2 is obtained from the combinational circuit’s response to V1. That is, after scanning in PPI bits of V1 and setting its PI bits, by applying one system clock (launch), the PPO bits of V2 are captured in SFFs. Before clocking the circuit again, PI bits of V2 can be set. Then, by applying one system clock again (capture), the outputs can be observed either at PO or in SFFs. This procedure is illustrated in Fig. 4. Because of its simplicity, the broad-side-testing method is widely used for transition fault test.
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Fig. 4 Timing graph for broad-side testing.
2 Preliminaries 2.1 Time expansion circuit for restricted broad-side testing Although in our previous discussion about broad-side testing the primary inputs can be fully controlled when applying a two-pattern test, and the circuit’s response can be observed at primary outputs, controlling the values of PI and observing the values of PO at-speed are not easy in reality. This is because automatic test equipments (ATEs) that support at-speed PI and PO operations are expensive [Jaya03]. Moreover, in [Jaya03] it is shown that when the number of PI or PO, or the sum of PI and PO, is small, namely less than 200 pins for PI or PO respectively, or less than 300 pins in total, the test coverage improved by having at-speed controllability at PI and observability at PO, compared to constraining PI and masking PO during test, is smaller than 0.2%. This encourages us to come to the assumption that the values of PI can not be changed between the first pattern and second pattern, and the values of PO are not observable in our test. This assumption is referred to as the restricted broad-side condition [Kaji06]. Time expansion circuit is obtained from making a copy of the original circuit and connecting PPOs of the original circuit (time-frame 1) to PPIs of the copied circuit (timeframe 2), removing flip-flops in between. Since sequential elements are removed, the time expansion circuit is a combinational circuit. Under the restricted broad-side condition, PI signals remain the same for time-frame 1 and time-frame 2, therefore PI pins of both circuits can be connected. Moreover, it will only be meaningful for a fault effect to propagate to a PPO, thus all gates and lines that do not reach any PPO can be removed. This produces a time expansion circuit for restricted broad-side testing as illustrated in Fig. 5. With such a circuit, we can employ techniques for conventional combinational ATPG to generate our test patterns. Since the time expansion circuit is in effect the same as the original circuit under the restricted broad-side condition, a test pattern valid for the time expansion circuit will be valid for the original circuit as well.
5
Fig. 5 Time expansion circuit for restricted broad-side testing [Kaji06].
2.2 SDQL – a metric for delay fault test quality In the transition fault model, test patterns are generated independent of fault size for a given circuit, while test coverage is calculated based on not only the locations, but also the actual sizes of faults in the fault list. Therefore for a set of test patterns for delay fault in a circuit, the fault coverage may vary greatly if calculated for faults at the same locations but with different sizes. To evaluate delay test quality, a statistical delay quality model (SDQM) was proposed in [Sato05a, Sato05b]. In this model, the probability for undetected small delays in a circuit is calculated as the statistical delay quality level (SDQL). SDQM takes the actual delay defect distribution into account. Assume the delay fault is of size s, and F(s) is the probability density for a small delay defect of size s to occur at a line in the circuit. The distribution function is given by F ( s ) = ae − λ s + b [Sato05b]
(1)
where λ is a shape parameter of exponential distribution, and a, b are parameters associated with actual defect distribution data. λ , a and b can be obtained by investigating the practical defect distribution data of manufactured circuits with a specific production technology. It is reasonable to set F(s) to 0 for when s is big enough, in which case the delay fault behaves more like a stuck-at fault, since the stuck-at fault test coverage is usually very high. For a delay defect, assume the difference between the system clock period (same as test clock period in at-speed testing) and the delay of the critical path is Tmgn, and the difference between system clock period and the delay of the sensitized path, along which the fault is activated and propagated by the test pattern generated from our ATPG program, is Tdet. As shown in Fig. 6, Tmgn and Tdet divide the delay size in to three parts:
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(1) When s is smaller than Tmgn, it is impossible (and unnecessary) to detect such a transition fault since it will not cause an error. (2) When s is greater than Tmgn and smaller than Tdet, the fault is not detected (but will cause an error). This is the case we do not want to happen. The probability for the fault to remain undetected can be calculated as Tdet
∫
F ( s )ds . [Sato05b]
(2)
Tmgn
(3) When s is greater than Tdet, the fault is detected. Assume N is the number of lines in a circuit, the total probability for a transition fault to occur in the circuit, also referred to as the statistical delay quality level (SDQL) of the circuit, is 2 N Tdet
∑∫
F ( s )ds . [Sato05b]
(3)
K =1 Tmgn
SDQL can be used to evaluate the delay test quality. Clearly, a smaller SDQL value indicates a better test quality. From formula (3), we immediately see two ways to improve SDQL. One is to maximize Tmgn, which is of not quite meaningful in practice. The other is to minimize Tdet. Since the system clock timing can not be changed, the only way to get a smaller Tdet is to maximize the sensitized path delay, which means we have to prepare a longest possible path for the fault in our test pattern. SDQL corresponds to the area of “undetected” part in Fig. 7. The upper curve shows the percentage of undetectable faults for different delay sizes caused by defects, and the lower curve shows the percentage of detected faults, which is the fault coverage. Our goal of generating high-quality transition fault tests can be interpreted as to minimize the “undetected” area on this figure.
System clock timing
path delay
Critical path Tmgn
Sensitized path Tdet
t
0 Fig. 6 Detectable delay size.
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Fig. 7 Percentage of undetectable, undetected and detected delay faults vs. delay size [Kaji06].
2.3 Basics of combinational ATPG The goal of test generation is to find a set of test patterns, which, when applied at the input of a faulty circuit, will cause a faulty circuit to produce at the output a different value (or values) from that of a fault-free circuit. An ATPG program does this automatically. It takes a circuit model (usually at logic level) and a list of possible faults as inputs, and generates a set of test patterns for the faults. It should be noticed that all the faults in the list correspond to one specific fault model. There are different types of ATPG algorithms for combinational circuits, as shown in Fig. 8. Among them, algorithms based on path sensitization are most popular, and significant improvements have been made to this kind of algorithms over years [Bush00]. Path sensitization process consists of three steps [Bush00]: (1) Fault activation, in which a difference between faulty circuit and fault-free circuit is generated at the fault site. This is done by assigning a value opposite to the faulty value to the signal driving the fault site. (2) Fault propagation, in which the difference is propagated to an observable output. This is done by assigning proper values to lines along one ore more paths from the fault site to the output (3) Line justification, in which line assignments made in previous steps are justified. Justification is defined as the process of finding a set of input values that cause a signal line to have the desired value [Kirk88]. It should be noticed that the order of fault activation and fault propagation can be exchanged, depending on whether we want to find an activation path first or to find a propagation path first. In the following sub-sections, we will briefly introduce the basic terms and techniques used in combinational ATPG algorithms based on path sensitization, which are the basis of the ATPG algorithm for high-quality transition fault test proposed in this
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report, by looking at some significant algorithms of this type. Since it is impossible to have an in-depth discussion on algorithms for combinational ATPG here and we would like to concentrate on basic concepts, the details, especially details of more advanced techniques are omitted and referenced to the original papers. Combinational ATPG Algorithms Simulation Based Algorithms
Boolean Satisfiability Based Algorithms
Path Sensitization Based Algorithms
D-algorithm
PODEM
FAN
SOCRATES
Fig. 8 Types of combinational ATPG algorithms. 2.3.1
D-algorithm
Roth’s D algorithm [Roth66] is based on the five-valued algebra introduced by Roth himself. Table 3.1 shows the symbols and meanings in this algebra. Symbol X denotes an unassigned signal value. Symbol D means the signal value is 1 in a fault-free circuit and 0 in a faulty circuit. Symbol D means the signal value is 0 in a fault-free circuit and 1 in a faulty circuit. FaultSymbol Value Faulty free 0 0/0 0 0 1 1/1 1 1 1/0 1 0 D 0/1 0 1 D X X/X X X Table 1 Roth’s five-valued algebra. A D-cube is an input-output combination describing the characteristic of a logic gate, or, in other words, a model for a logic gate using five-valued algebra. For example, for a two-input AND gate, the D-cube set consists of “D 1 D” (input1, input2, output), “1 D D” and “D D D”. Notice that D can be replaced with D , but all Ds in a D-cube set for the gate have to be replaced together. A D-cube is also called a propagation D-cube. The primitive D-cubes of failure (PDF) are models of faults in the circuit. For example, the PDF of an AND gate contains “1 1 D” if a stuck-at-0 fault is at the output, and “0 X D ” and “X 0 D ” if a stuck-at-1 fault is at the output.
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A conflict is defined as the situation where a necessary signal assignment contradicts with one or more previously-made assignments. A conflict can be detected by the Dintersection [Roth66], which is an operation to check if different D-cubes (which have been selected, corresponding to assignments made) can be used together. A simple rule is that if one D-cube has a signal with specific value, then the other D-cubes for the same gate must assign either the same value or X to the signal. For example, “0 X X” ∩ “1 X X” = ∅ , which means two D-cubes are incompatible. This is referred to as a failed intersection. The complete set of rules for D-intersection and failing conditions can be found in [Roth66]. If the intersection fails, there is a conflict. We give a few more definitions necessary for understanding D-algorithm. Implication is the procedure to determine the value of input or output signal which is uniquely implied by existing assigned values. This process can be implemented by a truth table, extended by Roth’s five-valued algebra, of the gate. The singular cover of a gate is the minimal set of input signal assignments needed to decide a particular output signal value, i.e. either 0 or 1. It can be derived from its extended truth table. The singular cover for a two-input AND gate, for example, consists of “0 X 0”, “X 0 0” and “1 1 1”. A D-frontier is the set of gates which have D or D at their inputs and X at their outputs under the current circuit input assignments. It separates the circuit into two parts, one with fault effect and the other without fault effect. D or D signals on the D-frontier are closest to the output. Fig. 9 shows an example of a D-frontier in a circuit. A
X
X f
B
C D E
0
X sa1
1
h X l
D D-frontier
gD
D
D
i
j
X m
k X
X X
Fig. 9 D-frontier. Backtrack is the process of removing a signal assignment which is found to cause a conflict or block the D-frontier from propagating, and selecting an alternate assignment for a previously assigned signal. With the above concepts, the procedure of D-algorithm can be roughly described as follows. First the fault is modeled by a primitive D-cube of failure. Then, propagation Dcubes are selected to propagate the D-frontier to a circuit output. After that, the internal circuit signal assignments are justified by selecting singular covers. During these steps, if D-intersection procedure fails, perform backtrack. To sum up, the D-algorithm has following features: (1) The search space of the algorithm contains all signal lines in the circuit.
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(2) Because of dependencies in the signals in the circuit, the algorithm contains hidden conflicts, often causing it to continue far beyond the conflict point in the search space before the conflict is detected, which cause lots of unnecessary work [Kirk88]. (3) The algorithm is very complex because all combinations of paths must be examined [Kirk88]. 2.3.2
PODEM
Goel introduced the PODEM (Path-oriented Decision Making) algorithm in [Goel81]. This algorithm reduces the search space to all inputs of the circuit, rather than all signal lines. This is reasonable since for a combinational circuit only inputs need to be considered. All other lines are subject to inputs. Moreover, by trying to assign only input values, a conflict point is discovered earlier than D-algorithm [Kirk88], reducing the number of backtracks. PODEM introduced the concept of objective to ATPG algorithms [Bush00]. Objective reveals the heuristics used to guide ATPG algorithm to go through the search space. Objectives are decided by the algorithm and are the goals to achieve during the ATPG process. For example, when sensitizing a fault propagation path, the algorithm measures the difficulty of sensitizing that path by calculating the structural length of paths between the fault site and circuit outputs, and then selects an easiest path as the objective to achieve. Backtrace is used to achieve an objective. It is the process to determine which inputs should be set to what values to achieve the objective, thus also embodies the heuristics used to guide the algorithm. Backtrace uses the controllability / observability measures to determine which inputs to select. After objectives are determined and inputs are selected, backtrace assigns input values to justify the objectives. Another contribution of PODEM is the procedure to check if there exists a propagation path from the current D-frontier to an output. If such a path does not exist, the algorithm backtracks immediately. If it does, the algorithm sets the objective of obtaining a non-controlling value on the unassigned signal line of the D-frontier gate closest to the output, in order to extend the D-frontier forward. This procedure is called X-PATH-CHECK. A high-level algorithm flow of PODEM is shown in Fig. 10.
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Fig. 10 Algorithm flow chart of PODEM [Bush00]. To sum up, PODEM successfully limits the search space to inputs and introduced the backtrack procedure to set input values. This algorithm also makes use of the controllability / observability measures to guide the search. Different measures can work smoothly with PODEM [Bush00]. One of the widely used controllability / observability measures is SCOAP [Gold80]. 2.3.3
FAN
Several improvements have been made to PODEM in FAN [Fuij83] algorithm. These include the concept of headlines and techniques of multiple backtrace, immediate implications and unique sensitization. 12
The search space of FAN is reduced to headlines. Fanout stems are the fanout lines. A free line is an input line of a circuit or an output line of a gate, the predecessors of which are not in any fanout loop [Kirk88]. And a headline is a free line that drives a gate that is in a reconvergent fanout loop [Kirk88]. For example, in Fig. 11, A, B, C, D, E, f, g, h are free lines, only g and h are headlines, and i, j are fanout stemps. Headlines can be justified to desired values. Therefore, when a backtrace reaches a headline, it can stop because it knows a headline can be assigned any value. Backtrace to the inputs can be deferred until the algorithm knows the final headline objectives.
Fig. 11 Example circuit for headlines. Multiple backtrace is a technique used to reduce the number of backtracks during the searching process for most circuits [Kirk88]. In this technique, backtraces are done in a breadth-first way. The depth-first backtrace used in PODEM is inefficient sometimes [Bush00]. In the multiple backtrace, a signal conflict is found much sooner than the single backtrace procedure, which means that FAN will rapidly find a previously made assignment causing a conflict and reverse it much sooner than PODEM [Bush00]. Unique sensitization and immediate implications are techniques used to enhance the algorithm’s ability to take opportunities to directly assign values to uniquely determined signals. Examples of these techniques can be found in [Bush00]. To sum up, FAN reduced the search space of the algorithm to all headlines in the circuit, and uses the multiple backtrace to increase the efficiency of the searching process. Moreover, knowledge of the circuit topology is better utilized in FAN to find more uniquely determined signals. 2.3.4
SOCRATES
Based on FAN, an ATPG system SOCRATES (Structure-Oriented Cost-Reducing Automatic TESt pattern generation system) was introduced in [Schu88]. It includes an improved implication procedure, an improved unique sensitization procedure and an improved multiple backtrace procedure. In the improved implication procedure, the boolean relation ship ( p ⇒ q ) ⇔ (¬q ⇒ ¬p ) is used as an implication criteria. This means if the SOCRATES learns a forward implication triggered by setting signal p to 1, then it also learns a backward implication by setting q to 0. Fig. 12 shows an example for the implication procedure. To take the full advantage of the additional implication criteria, a learning procedure is executed in the pre-processing phase, where all circuit signals are systematically set to both 0 and 1, so that any implications to other signal values are 13
discovered. Among all implications from the learning procedure, only implications that are worthwhile are remembered, otherwise there will be a great consumption of memory space of the ATPG program. “Worthwhile” refers to those implications which can not be recognized by conventional implication procedures, since there is no much value in learning implications that can be obtained by a simple implication procedure.
Fig. 12 Implications from b = 1 and f = 0. (a) Implications from a = 1. (b) Implications from f = 0. To apply unique sensitization procedure effectively, SOCRATES uses two instructions. Detailed instructions, as well as the definition of dominance can be found in [Schu88]. As the improved implication procedure, the improved unique sensitization procedure results in an optimized reduction in the search space and helps to reduce the number of backtracks and detect conflicts earlier [Schu88]. In addition, the improved multiple backtrace procedure reduces the search space, and reduces the number of backtracks in many cases [Schu88]. To sum up, SOCRATES is an advanced ATPG method based on FAN, which further reduces the search space.
3 Proposed ATPG Algorithms 3.1 Algorithm selection The algorithm proposed in this work is based on path sensitization ATPG algorithms. As mentioned before, in the path sensitization process, the order of fault activation and fault propagation can be exchanged. That is, we could either find a fault propagation path first and then find an activation path, or find a fault activation path first and then find a propagation path. The proposed ATPG method contains two different algorithms: a propagation-first algorithm and an activation first algorithm [Kaji06]. The propagationfirst algorithm first finds a fault propagation path as long as possible, and then activates the fault. The activation-first algorithm first finds a fault activation path as long as possible, and then finds a fault propagation path by applying a part of the propagationfirst algorithm. In the ATPG procedure, which algorithm is selected depends on which algorithm could contribute more to the total path length potentially. The propagation-first algorithm is likely to be more useful when the difference of length between propagation paths is greater than the difference of length between activation paths. Consider this the other way round, the effort of finding a long activation path would be meaningless if the difference
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of length between activation paths is the same. Similarly, the activation-first algorithm is likely to be more useful when the difference of length between activation paths is greater than the difference of length between propagation paths. Therefore, for fault f, which algorithm is to be applied is determined according to the following procedure [Kaji06]: (1) Calculate the length of the structurally longest propagation path for f as p_max(f), and the length of the shortest propagation path for f as p_min(f). (2) Calculate the length of the structurally longest activation path for f as a_max(f), and the length of the shortest activation path for f as p_min(f). (3) If p_max(f) – p_min(f) > a_max(f) – a_min(f), then apply the propagation-first algorithm. Otherwise apply the activation-first algorithm. An example is shown in Fig. 13. In this case, since the difference between p_max(f) and p_min(f) is 2 and the difference between a_max(f) and a_min(f) is 4, the activationfirst algorithm is applied for f.
Fig. 13 Algorithm selection.
3.2 Propagation-first algorithm The propagation-first algorithm comprises two phases: First, sensitize a longest possible fault propagation path from the fault site to a PPO. Second, justifies the value for fault activation. Like other ATPG algorithms, this algorithm sensitizes the fault propagation path by extending the D-frontier until the D-frontier reaches a PPO. When there are several gates in the D-frontier, a conventional ATPG algorithm like PODEM will choose the gate which is the easiest to observe, according to observability measures of the gate such as SCOAP [Gold80] or simply the structural length from the gate to a PPO. This D-frontier gate selection criterion will not produce a long propagation path. The propagation-first algorithm, on the other hand, selects a D-frontier gate which can potentially maximize the propagation path, i.e. one with the maximum sum of distances from fault site to the gate and from the gate to a PPO. Fig. 14 shows an example of distances between D-frontier gates and fault site, as well as distances between D-frontier gates and PPOs. For each D-frontier gate i, dis(i) is the path length from the fault site to i, and p_max(i) / p_min(i) is the length of the 15
structurally longest / shortest propagation path from i to PPOs, where the length of a path is calculated as the number of gates on the path. A D-frontier gate with greatest sum of dis(i) + p_max(i) will be selected to propagate the D-frontier further. Fig. 15 gives an example of D-frontier gate selection in the propagation-first algorithm. In this example, gate a with a maximum possible propagation path length 15 is selected among other Dfrontier gates. Notice that a conventional ATPG algorithm would have selected gate c instead, since c is likely to be the easiest to observe, resulting in a maximum possible propagation path with length 14.
Fig. 14 Distances from D-frontier gates to fault site and to PPOs [Kaji06].
D-frontier dis(i) p_max(i) p_min(i) gate a 6 9 7 b 4 6 5 c 7 7 4 Fig. 15 Example of selecting a D-frontier gate.
3.3 Activation-first algorithm The activation-first algorithm also has two phases: First, find a fault activation path as long as possible. Second, sensitize a fault propagation path in the same way as the propagation-first algorithm, which can be done by applying the first phase of the propagation-first algorithm. During the first phase of the algorithm, the length of the fault activation path to be found is designated at first. Then a path from the faulty line (fault site) to PIs or PPIs is extended by stepwise concatenation of circuit lines. During the expansion, a branch and bound algorithm was used to iteratively search for potentially testable paths with greater
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lengths than the longest potentially testable path already found, where the length of the currently identified longest path is used as a lower bound to limit the search to the area where longer paths can be found [Kaji06, Shao02]. When a path is extended, signal values are assigned by the implication procedure of ATPG. If a conflict occurs in the implication procedure, backtrack is performed and another path is searched. In addition, when a path is extended, the algorithm checks whether there is at least one sensitizable fault propagation path from the fault site to a PPO, if this is no such path, backtrack is performed, which is similar to the X-PATH-CHECK procedure in PODEM.
3.4 Overall ATPG procedure The overall procedure of the proposed ATPG can be described by the flow chart in Fig. 16. This procedure includes transforming the circuit under test into a time expansion circuit for restricted broad-side testing, creating a fault list for the transition fault model, generating a set of test patterns and evaluating the quality of test patterns by calculating SDQL.
Fig. 16 Flow chart of overall ATPG procedure.
4 Result and discussion Experimental results of the proposed ATPG method with ISCAS89 benchmark circuits were given in [Kaji06]. It was shown that test patterns generated by the proposed ATPG method achieved about 10% reduction of SDQL value on average compared with test patterns generated by conventional ATPG programs, while maintaining almost the same fault efficiency (ratio of the number of faults detected and proved redundant to the total number of faults [Ohta01]). As discussed earlier in this report, smaller SDQL values indicate higher test qualities. The improvement of test quality for circuit s1423 can be visualized in Fig. 17. As we can see, the area of undetected faults is reduced. Therefore the goal of generating test patterns with higher test quality is achieved.
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Fig. 17 Effects of proposed method for s1423 [Kaji06]. The proposed ATPG method is a straight-forward way to generate high-quality transition fault test. Test cost can be reduced by applying a time expansion circuit for restricted broad-side condition and employing combinational ATPG algorithms. The proposed ATPG algorithms was implemented in [Kaji06] based on SOCRATES. But it should be noticed that the proposed ATPG method can be applied to any successful combinational ATPG algorithms, since the major improvements in algorithm are just the heuristics used to guide ATPG algorithms to sensitize a long fault path in search space. However, there are a few drawbacks in the proposed ATPG algorithms. One thing is that in the algorithms, the length of a path is calculated as the number of gates on the path. This is too simplistic, since paths with same structural length may have different delays. For example, consider the circuit in Fig. 18. The proposed algorithm may choose to propagate the D-frontier through the AND gate, since both path have the same structural length. It would be certainly better to propagate the D-frontier through the XOR gate, since the actual delay along this path is greater. The actual delay of the lines (gates) on the path should be considered instead in determining the longest path, which means the algorithm should search a weighted graph when calculating the actual path length.
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D Fig. 18 Example circuit for actual path delay. Another drawback is that in the path extension process, the proposed algorithms intend to find a longest structural path. However the structurally longest path may not be testable, and a better strategy would be to search only for longest testable path [Shao02a]. This can be done by identifying untestable paths [Shao01] before path selection, thus avoiding them during path extension process. A path expansion procedure to select a long testable path, based on the identification of untestable paths, was introduced in [Shao02b].
5 Summary In this report, we introduced a high-performance transition fault ATPG method to deal with the problem of delay fault testing for small delays. The transition fault model is used for test generation. We introduced broad-side testing to apply two-pattern tests to scan circuits. A time expansion circuit for restricted broad-side testing is used so that conventional combinational ATPG can be employed. To evaluate delay test quality, we also introduced SDQM and SDQL. After providing necessary basis of combinational ATPG algorithms, the proposed ATPG algorithms are explained. There are two algorithms, namely propagation-first algorithm and activation-first algorithm, and which algorithm to apply is determined for each fault according to an algorithm selection criterion. Test patterns generated by the proposed method are evaluated using SDQL, which showed the effectiveness of the proposed method. Finally, we discussed the advantages and disadvantages of the proposed ATPG method, and several possibilities for improvements were given.
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