A Methodology for Drop Performance Prediction and Application for Design Optimization of Chip Scale Packages Ahmer Syed, Seung Mo Kim, Wei Lin, Jin Young Khim, Eun Sook Song, Jae Hyeon Shin, and Tony Panczak Amkor Technology, Inc 1900 S. Price Road Chandler, AZ 85248 Phone: (480) 821-5000 Fax: (480) 821-2389
[email protected] Abstract As handheld electronic products are more prone to being dropped during useful life, package to board interconnect reliability has become a major concern for these products. This has prompted the industry to evaluate the drop performance of CSP packages while mounted on printed wiring boards using board level drop testing. Although a new board level test method has been standardized through JEDEC (JESD22-B111), characterization tests take quite a long time to complete, extending the design cycle. This paper proposes a method to compare and evaluate the drop performance through simulations at the design stage. A global-local approach is used to first determine the dynamic response of the board during drop and then to translate it into stresses and strain energy density in solder joints and intermetallic layers. The dynamic response of the board is validated by using data from actual board level testing as per JEDEC standard. The solder joint and intermetallic stresses are then related to drop to failure test data to derive a prediction model. The method is then applied to quantify the effect of package design parameters on the drop performance. Factors considered include material set, thickness of various material layers, pad size, and ball size. The same factors were tested in board level drop to further validate the prediction model. Experiments were also conducted to quantify the effects of package ball pad finish on the drop performance through board level testing according to JESD22-B111. The results indicate that the drop performance can be increased by a factor of 4 or more by changing package design and material variables. Introduction Reliability of handheld electronic products, such as mobile phones and PDAs, due to drop has become a major concern recently. Due to drop/impact event, the printed wiring board assembly inside the phone casing starts to vibrate causing a flexural motion of the board. The bending of the board puts solder joints and other interconnects under severe stress due to high level of G forces. This ultimately causes failures in solder joints, intermetallic layers at solder-pad interface, or board via cracking. The failure can occur either on the package side or the board side, but former is more prevalent. The best test method for determining if an IC package will meet drop/impact requirement for a product is the product level drop test. However, product level qualification tests are 0-7803-8906-9/05/$20.00 ©2005 IEEE
usually done at a stage where product is mostly finalized, minimizing the opportunities for further optimization. This also has the disadvantage that the information gathered on one product may not be applicable to another product due to difference in board design, component locations, and board support types and locations. Another problem with product level testing is that it is specific to one design and customer. A package supplier cannot determine at priori the potential behavior of a particular package for different board designs and customers nor can it conduct product level test. These issues can be avoided, however, by conducting board level tests. The board level test is conducted by using known input forces (acceleration) to the board, thus eliminating the variations due to product casing. If the same inputs are used every time using same board design, the drop performance of an IC package can be compared with another package. Using this concept, a board level drop test method was recently standardized through JEDEC, JESD22 –B111 [1], to compare the performance of IC packages under drop conditions. The method was developed by a task group comprising of several companies including Amkor, Nokia, Sony Ericsson, Ericsson Mobile Platforms, Texas Instruments, Flextronics, and W L Gore & Associates. The primary purpose of this method was to minimize the variations introduced by board design, construction, and material as well as test conditions. This ensures that if a difference in drop performance of two packages or two designs of the same package is detected, it is primarily due to component designs. This provides an opportunity to conduct drop tests at a very early stage of product development and to optimize the design to exceed customer requirements. Another advantage of the test method standardized is its ability to provide additional information useful for product board layout. Unlike board level temperature cycle test, the drop performance of a component and solder interconnects to the board is strongly related to component’s location on the board. Studies [8, 9] have shown that the failure in drop testing is due to flexing of the board and not due to inertia effects. Since the flexing of the board is not uniform through out the board, a component located on a region of less flexing will perform much better than if it is located on a region of more flexing. The JEDEC method seeks to get this location dependent data from one test. The method recommends mounting 15 components on the board in 3 rows of 5 components each. These 15 locations provide 6 sets of location dependent data point from each test after accounting
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for symmetry in design and support locations, as shown in Figure 1. Thus one test provides a range of drop to failure data depending on component location. This was thought more useful than gathering data on just one component per board located at the worst location. A location dependent data is more useful in real product layout design where a component can be placed on the board at a less damaging location if its drop performance is a suspect. Of course this has to be balanced out considering electrical, thermal, and routing aspects of the board design.
11 U11
12 U12
13 U13
14 U14
15 U15
6 U6
7 U7
8 U8
9 U9
10 U10
1 U1
2 U2
3 U3
4 U4
5 U5
Screw hole
Figure 1: Component locations and grouping on drop board as per JESD-B111. Table 1: Component Grouping for Data Analysis Group Board Locations A U1, U5, U11, & U15 B U2, U4, U12, & U14 C U6 & U10 D U7 & U9 E U3, & U13 F U8 A location dependent data on the same board is also useful in developing life prediction models. Since the drop performance is expected to be different at each location, this difference would primarily be due to the difference in damage levels of the weakest link (solder joint, intermetallic layers, via, pad to laminate interface, etc). Thus, an empirical life prediction model can be established by determining the damage level at each location and relating it to the corresponding number of drops to failure. The underlying assumption is that the failure mode for all failures remained the same, irrespective of component location. The development of the life prediction model requires a large number of data points for different component designs to have a high degree of confidence in predicted life. This task is time consuming and challenging as multiple failure modes can exist and the interfacial behavior is a strong function of materials used (solder alloys, pad plating, laminate material, etc). However, if the drop test reveals one major failure mode, this task becomes slightly more manageable. Even with all the data collected, it will be very difficult to predict the exact number of drops that a component can last at a particular location, because the number of drops to failures is in 10s and 100s, not in 1000s and millions. The accuracy of prediction for such a low number of drops becomes very questionable.
The best alternate is to provide a relative comparison, predicting a performance improvement not an actual number. This performance improvement has to be in number of drops and not in stress, strain or energy density reduction. But since the response is usually calculated in term of stress or strain, a relation needs to be developed between the response and the drop performance improvement. In other words, unless one knows X % reduction in stress causes Y % increase in drop performance, just the prediction of % reduction in stress is not very useful. In order to determine this relationship between damage parameter and the drop performance improvement, a large amount of test data and failure mode identification needed along with a simulation methodology that can calculate the damage parameters (stress, strain, energy density, fracture mechanics parameters) rather accurately. A number of excellent papers have been written on drop characterization and simulation [2 - 7]. The simulations have shown good correlation with measured results in terms of board response. However, all the approaches published thus far require the use of Explicit finite element software for product and board level drop simulation. This paper presents an approach for simulating board level drop test and to transform the board response to solder joints levels. The method used can be implemented in standard finite element software (e.g., ANSYS, ABAQUS) and there is no need to use special purpose software such as LS-DYNA or ABAQUS/Explicit. Advanced techniques such as submodeling and constraint equations are used to transfer global board level response to local component/solder joint level damage parameters. Test data is then used to relate the damage parameters with the number of drops to failure. Finally, improvement in drop performance is estimated using simulation approach which is also validated from test. Simulation Methodology The task of simulating the mechanical behavior of an electronic assembly due to drop/impact loading is not a trivial one. This requires a good understanding of dynamic response of structures due to impact loading and material behavior at a very fast rate of loading. The drop simulation can be accomplished by duplicating either a product level drop test or a board level drop test condition. The purpose of both of these simulations is to somehow transform the global loading into solder joint response. Some of the challenges involved in these simulations are: - Modeling various levels of interconnects from product casing to IC package so the loads are properly transformed, - Very large finite element models with various mesh densities to transition from millimeter scale to micron scale within one model - The level of mesh density also impacts the solution time not only because of model size but also due to time step size requirements during dynamic simulation. For board level drop simulation the task is a bit easier as casing as well as its interconnects to board are not modeled, but still daunting as effective and efficient accounting of component effects are required. With multiple components on a board and hundreds of solder joints per component, modeling each solder joint in a board level model impacts the
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efficiency of analysis. A global-local approach is needed and is used here where the global model of the board is much coarser but still accounts for component effects. This approach consists of the following four steps: - Calculation of stiffening effect of component - Global board level model including component stiffening effect - Sub-modeling approach to transfer boundary conditions to local component level model - Detailed solder joint level model with calculations of joint or intermetallic layer response to global loading Component Stiffening Effect: A typical approach for modeling component on a board level model is to use shell elements for the component body and beam elements for the solder joints. This requires calculating effective component stiffness as substrate, die, die attach, and mold compound are replaced by one effective material represented by shell elements. In addition, calculations are required to convert solder joint thickness, length, width, and material properties in a format required for beam representation. Even with this beam representation, a number of solder joints are replaced by one effective beam to keep the model size manageable. All of these calculation and assumptions can cause inaccuracies in the model.
This component level model is then analyzed using a three-point bend loading condition. The board nodes just outside of component body and parallel to two of the component edges are supported while a unit load is applied along the center line on the backside of the board model. The analysis provides the deflection at the center line due to unit force, which is then used in a 3-point bend equation to calculate the effective modulus of board-package combination. The effective modulus so calculated is then used in the global board level model, thus accounting for component’s stiffening effect. Global Board Level Modeling: The board level model consists of shell elements representing the mid-surface of the board. The elements have two sets of material properties, one for elements in the non-component region and other for component region. The component region is shown in Figure 3 by dark gray elements and has effective modulus and mass density based on component stiffness and mass. The screw holes on each corner are also modeled according to their size.
(a)
(a)
(b)
(b)
Figure 3: Global model for dynamic analysis of printed wiring board assembly; (a) component locations, (b) board displacement shape.
Figure 2: Component level model for effective stiffness and solder joint stress calculations; (a) Full 3-D model, (b) Cross-section and loading for 3-point bend. In the approach used here, the component and solder joint effects are accounted for by calculating effective stiffness of the component. This is done by creating a full component and board model using solid elements as shown in Figure 2. The component body model has all the geometric details of substrate, die, and mold compound. The solder joints are modeled as solid elements accounting for pad area and joint height (joint shape is assumed as cubical). Only the segment of board under the component is modeled using solid elements.
The board level model is analyzed by using the G input loading as per JEDEC standard (1500 G, 0.5 milliseconds duration, half-sine pulse). However, instead of using this acceleration as an input directly on the support points as in [5], a large mass method is used here. In this method a large mass element is attached to the nodes around the screw holes using rigid elements. The acceleration input is converted into force input by multiplying the acceleration with the large mass. This large mass method with rigid elements effectively applies the acceleration on the support points. This approach is a standard method in general purpose finite element
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software such as ANSYS and does not require explicit software such as LS-DYNA. With acceleration input effectively applied at the screw locations, the dynamic analysis is done using modal analysis and mode superposition approach. This provides a measure of board natural frequencies as well as displacement and strain histories.
alongwith the typical stress distribution in the intermetallic layer. The detailed corner joint model also includes layers of intermetallic between solder and pads on package and board side of the joint. This is needed as the failure during drop test is most often at the intermetallic layer or between intermetallic layers rather than through bulk solder. The corresponding material properties are used for these intermetallic layers. The solder material is modeled using time independent plasticity equations for SnPb or SnAgCu solder. Using the above simulation approach, the damage in the solder joints or IMC layers can be calculated for each component location on the board. In summary, following simulations are needed to simulate the board level drop test with 15 components mounted per board: - One analysis on component level model to calculate the stiffening effect, - One global PWB level analysis for applicable G levels and pulse duration - Six local analyses on the same component model, moving the center location to corresponding locations on the board and using sub-modeling approach for response calculation.
Figure 4: Coarse-detailed model interface and displacement continuity.
U8 Location
Figure 5: Solder joint and intermetallic layers and stress distribution in IMC layer
Max Sz = 110 MPa
Sub-modeling and Detailed Solder Joint Model: Once the global model is established and analyzed, its results need to be applied to the local component model to calculate solder joint response. Again, there are a number of approaches such as displacement or force application. However, ANSYS offers a sub-modeling feature that makes this aspect quite automatic. The sub-modeling approach also allows shell-to-solid interface which makes it quite easy to use the same solid model created for component stiffening effect calculation, Figure 2. This approach creates the automatic displacements applied to the local model. The local model created to calculate component stiffening effect is not detailed enough for solder joint response. Therefore, one more detail is added by modeling the corner joint with associated intermetallic layers and section of board and component. This detailed corner joint model replaces the coarse corner joint in the local component model and is connected to the component model through constraint equations, as shown in Figure 4. The details of the solder joint model and the intermetallic layer are shown in Figure 5
U14 Location
Max Sz = 200 MPa
Figure 6: Out-of-plane displacement distribution of the board at two locations and the resulting tensile stress in solder joints. Experience with JEDEC drop test method has also shown that most often it is the components in Group B (see Table 1) that fail first rather than the component located at the center of the board. The simulations for six group of locations show this difference clearly when the displacement and stress distribution at these locations are compared. Figure 6 shows the out of plane displacement distribution of the board segment under the components at location U8 and U14. While the board segment is deforming in pure bending mode at center location, the off center location towards the edge of the board is deforming due to bending as well as twisting. This additional twisting causes significantly higher stresses in
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corner joint (top-right corner in the figure) compared to joint which sees only bending deformation. The simulation for one component type showed 80% increase in solder joint tensile stress because of this additional twisting.
Longitudenal Strain (microstrain)
Experimental Verification In order to check the accuracy of this approach, measurements were made on drop test boards with strain gage mounted at different locations. The location of strain gages are shown in Figure 7 with four gages on the non-component side of the board and one on the component side between two components. The strain gages on the non-component side are located at positions aligned with the center of component and provide a measure of component’s stiffening effect.
The board was dropped multiple times to measure the strain response for 1500G, 0.5milliseconds acceleration input. The drop test was done as per JEDEC JESD22-B111 [1] standard. Figure 8 shows the strain response of the board at the five locations. The strains are lowest close to the screws and highest towards the center of the board. It is interesting to note that while first peak is negative for locations 2, 3, & 4, it is positive for location 1 even though the measurements are done on the same side of the board. This shows that the board is moving in the opposite direction close to screws than towards the center. Also, comparing strain for location 3 & 4, the values are slightly higher for location 4 than at location 3, which is right in the middle of the board. Finally, the strain values at location 3 and location 5 show the stiffening effect of component. The strain at location 5, which is just outside the component body is about 5 times higher than the strain at location 3. This is because component flattens the board underneath (lower strain) due to multiple solder joints connecting the board to the component. This stiffening is a function of component size and the number of solder joints. The difference is strain value underneath and just outside the component is the primary reason why solder joints in the outer row and corner are most susceptible during drop test. The sharp change in board curvature just outside of outer row of solder joints puts these outer joints in tension, causing the joints or intermetallics to fail. Figure 9 shows the predicted strain at the same locations from the global board model. Notice that the trend is very similar to measured results for location and stiffening effect of the components. The simulations also show positive strain on location 1, slightly higher strain on location 4 compared to location 3, and 5X higher strain for location 5 compared to location 3. This validates the approach used for modeling component stiffening and mass effects on the board.
Longitudenal Strain (microstrain)
Figure 7: Strain gage locations for strain measurement during drop test. 5000 Location Location Location Location Location
4000 3000 2000
1 2 3 4 5
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5000
Location Location Location Location Location
4000 3000 2000 1000 0 -1000 -2000 -3000 0
0
1 2 3 4 5
0.005
0.01
0.015
0.02
Time (seconds)
-1000
Figure 9: Predicted strain time history at five locations.
-2000 -3000 0
0.005 0.01 0.015 Time (seconds)
0.02
Figure 8: Measured strain time history at five locations.
Figure 10 compares the measured and predicted strain response on two locations. It can be clearly seen that the predicted natural frequency (inverse of time span between consecutive peaks) and amplitude are very close to the measured ones. The damping ratio was found to be about 7%. 476
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Loc 5 - Measured
4000
Loc 5 - Predicted
3000
Loc 4 - Measured Loc 4 - Predicted
2000 1000 0 -1000 -2000 -3000 0
0.005 0.01 0.015 Time (seconds)
0.02
Figure 10: Comparison of measured and predicted strain on two locations. Damage per drop vs. Drop to failure As can be seen from the time history plots of board strain in Figure 8 and 9, each drop event causes the board to vibrate at its natural frequency for some time before damping ultimately brings the board to rest. The amplitude of motion keeps on decreasing for each successive peak because of damping. In other words, each drop event is actually a sum of multiple cycles with continuously decreasing cyclic amplitude. During this whole time until the board comes to complete stop, damage is accumulating in solder joints and IMC layers depending on the magnitude of board flexure and whether it is bending in downward or upward direction. It has been shown [5] that the crack opening occurs during downward motion only when the joints are in tension. Thus, every positive peak will cause some crack growth if the magnitude of damage indicator (stress, strain, or energy density) is larger than the threshold value, as conceptualized in Figure 11.
If a fracture mechanics approach is adopted for life prediction, a relationship needs to be found between the fracture mechanics parameter and the rate of crack growth. This requires basic crack growth studies, which need to be done for various materials and intermetallic compounds related to pad-solder structure. However, realizing that the JEDEC drop test method provides a natural variation in drops to failure for different location, a much simplified engineering approach can be used to estimate the drop performance of a device. The JESD22-B111 board level drop test method can provide 6 location dependent data sets for each component tested. If failure mode is ascertained for each of these groups and it is consistent for most of these locations, this test can provide data which can range from a few drops to a few hundred drops on one component type. Repeating the test on a few other components can provide a wide enough range of data to fit a good life prediction model for a particular failure mode, once the damage parameter is calculated for each location. This damage parameter can be calculated using the simulation approach described above. All that is needed is to repeat the local component analysis for different locations, yielding 6 sets of stress, strain, or energy density. Figure 12 shows the Weibull plot of drops to failure for a CSP package. The data is from 5 boards, each dropped multiple times as per JEDEC condition. The data for symmetric locations is combined and is labeled as Group A, B, and E, as per Table 1. Only 2 of the five devices failed at the center location (U8) and that data is not plotted here. Also, there were not sufficient failures for locations in Group C and D. The data shows very similar performance for Group B & E, but Group A locations showed much better drop performance.
Weibull Group A Cumulative % Failed
Longitudenal Strain (microstrain)
5000
Magnitude of Damage Indicator (Stress, Strain, Energy Density)
5000 4000 3000 Crack Growth
2000 1000
F=16 / S=4 Group E F=9 / S=1
Threshold for Crack Growth
0
Drop to Failure Figure 12: Weibull plot of number of drops to failures per location group.
No Crack Growth
-1000
F=12 / S=8 Group B
-2000 -3000 0
0.05
0.1
Time (seconds)
0.15
The relative drop performance per location is compared with the relative principal stress and tensile stress in the intermetallic layer in Figure 13. The principal and tensile stress values were calculated using the simulation methodology described above and correspond to the first peak in board strain vs. time plot. Although, there is not much data
Figure 11: Variable cycles with one drop and threshold for crack growth. 477
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stress reduction at the intermetallic layer. Although, LGA version was not tested for this component, it has been shown [10, 11] that LGA version can improve drop performance by 2X.
1.2
Table 2: Parameters for design optimization and resulting stress reduction.
Principal Stress
1
Design Option
Tensile Stress
0.8
Case
BGA/LGA Mold Cap
0.4
1 2 3 4
0.2
99.00
0 0
1
2
3
4
5
Relative # of drops to failure Figure 13: Relative stress vs. drops to failure. For example a 65% improvement in drop performance can be expected if the principal stress can be reduced by 33%. It should be emphasized here that this is just one data set and more data is needed to determine the relationship which is applicable to wider range. Design Optimization Using the above concept of relating drop performance with the damage parameter at different locations provides a relative comparison or a measure of improvement in drop performance. This measure can be used to study the effect of design and material changes. Factors such as the effect of pad size, BGA vs LGA, substrate and package thickness as well as various packaging materials can be evaluated up-front to determine what design parameters are important to improve the drop performance. Table 2 shows an application of this concept where a 12x12mm, 289 lead CTBGA package was optimized for potential drop performance improvement. Factors considered were; a) ball pad opening on the package, b) package thickness, and c) BGA vs LGA. The tensile stress in the intermetallic layer (volume averaged) was predicted for each variation and the relative values are listed in Table 2. Based on Figure 13, a 1.5X to 2X improvement in drop performance is expected for each of these variations. To verify these predictions, actual drop tests were conducted on the same package with different pad openings and mold cap thickness. Multiple legs were tested using different drop conditions, board construction, and pad metallurgy. The Weibull distribution of number of drops to failure is plotted in Figure 14 for the components in the same group. The data shows 1.7X improvement in drop performance when the pad size is increased from 250 um to 300 um. Similarly, 1.5X improvement is achieved by decreasing the mold cap thickness from 0.7mm to 0.45mm. These improvements are in line with predictions based on 478
Cumulative % Failed
0.6
BGA BGA BGA LGA
0.7mm 0.7mm 0.45mm 0.45mm
Pad Opening 0.25mm 0.30mm 0.3mm 0.3mm
Tensile Stress (Relative) 100 69 52 45
Weibull 250 um Pad
90.00
W2 RRX - SRM MED
F=14 / S=10 300 um Pad
50.00
W2 RRX - SRM MED
F=9 / S=15 10.00 5.00
1.00 1.00
10.00
100.00
Drop to Failure
1000.00
β1=1.20, η1=152.26, ρ=1.00 β2=1.28, η2=258.89, ρ=0.94 99.00
Cumulative % Failed
Relative Stress at First Peak
available at this time, a clear relationship can be observed between number of drops to failure and principal or tensile stress.
Weibull 0.45 mm
90.00
W2 RRX - SRM MED
F=12 / S=7 0.70 mm
50.00
W2 RRX - SRM MED
F=15 / S=5 10.00 5.00
1.00 1.00
10.00
100.00
Drop to Failure
1000.00
β1=1.27, η1=240.16, ρ=0.99 β2=1.38, η2=162.93, ρ=0.99
Figure 14: Measured effect of component pad size and thickness on drop performance.
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Summary and Conclusions A methodology for simulating board level drop test is presented which shows very good correlation with experimental results. Advanced techniques of finite element analysis are used to determine the response of solder joints and intermetallic layers due to dynamic motion of printed wiring boards subjected to drop conditions. It is shown that a simple relationship can be developed between number of drops to failure and damage response of solder joints and interconnects. Using Principal Stress in intermetallic layer as a damage indicator, the application of simulation approach predicted improved drop performance by varying the design parameters of a chip scale package. The results were verified by actual board level drop tests on the same package. Reference 1. .JEDEC Standard JESD22-B111, Board Level Drop Test Method of Components for Handheld Electronic Products. 2. Lim, C.T. and Low, Y.J., “Drop Impact Testing of Portable Electronic Products,” 52nd ECTC Conference Proc., 2002, pp. 1270-1274. 3. Lim, C.T. and Low, Y.J., “Drop Impact Survey of Portable Electronic Products,” 53rd ECTC Conference Proc., 2003, pp. 113-120. 4. Tee, T.Y., Luan, J.E., Pek, E., Lim, C.T., and Zhong, Z.W., “Novel Numerical and Experimental Analysis of Dynamic Responses under Board Level Drop Test,” EuroSim Conference Proc., May, 2004. 5. Tee, T.Y., Luan, J.E., Pek, E., Lim, C.T., and Zhong, Z.W., “Advanced Experimental and Simulation Techniques for Analysis of Dynamic Responses During Drop Impact,” ECTC 2004, pp. 1089 – 1094. 6. Zhu, L., “Modeling Technique for Reliability Assessment of Portable Electronic Product Subjected to Drop Impact Loads,” 53rd ECTC Conference Proc., 2003, pp. 100104. 7. E.H. Wong, K.M. Lim, Norman Lee, Simon Seah, Cindy Hoe, and Jason Wang, “Drop Impact Test - Mechanics and Physics of Failure, 4th EPTC, pp. 327-333, Singapore, 2002 8. Wong, E. H., Private Communications 9. Tee, T. Y., Private Communications 10. A. Kujala (1, T. Reinikainen (2, W. Ren, “Transition to Pb–free Manufacturing Using Land Grid Array Packaging Technology”, ECTC 2002, pp 359-364 11. Syed A., Darveaux R., "LGA vs. BGA: What is More Reliable? A Second Level Reliability Comparison," Proc SMTA International, Chicago, IL, Sept. 2000, pp. 347352.
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