A Module Generator for High Speed CMOS Current Output Digital ...

A Module Generator for High Speed CMOS Current Output Digital/Analog Converters Robert R. Neff, Paul R. Gray, and Alberto Sangiovanni-Vincentelli Electrical Engineering and Computer Sciences University of California, Berkeley Abstract This paper presents a module generator for Digital/Analog Converter (DAC) circuits. A combination of circuit simulation and DAC design equations is used to estimate performance. A new constrained optimization method is used to determine design variable values. The layout is created using stretching and tiling operations on a set of primitive cells. Close coupling of optimization and layout allows accurate incorporation of layout parasitics in optimization. Prototypes have been demonstrated for an 8-bit, 100-MHz specification, driving a 37.5-ohm video load, and a static 10-bit specification, driving a 4mA full-scale output current. Both designs use a 5-V supply in a standard 1.2 µm CMOS process. 1

an optimal design is desired, a flat approach is better able to optimize all variables simultaneously. When a complex circuit behavior is difficult to separate and evaluate in a hierarchically, a flat approach is the only option. In this paper, a single-level optimization is applied to the current-switched DAC function, allowing simultaneous optimization of architecture and device level design variables, and easy incorporation of all aspects of performance, including layout related parasitics when predicting static and dynamic performance. For layout synthesis a stretching and tiling approach is used, enabling accurate performance prediction and rapid design implementation. II. Module Generation Methodology.

I. Introduction In mixed-signal integrated circuits, the analog part of the design often occupies a small portion of the physical die area but requires a disproportionately large amount of the design effort and time. One approach for reducing design time is to develop module generators for frequently occurring analog circuit functions, synthesizing blocks that are competitive with manual design in performance and die area (1). One frequently occurring function is the digital-analog converter (DAC). These range in requirements from low-speed, highaccuracy circuits, usually implemented with oversampled approaches, to relatively high speed, low to medium resolution applications, usually implemented with current-switched or resistor string DACs. This paper describes a methodology for low level module generation and its application to highspeed current switched DAC modules in a CMOS technology. By changing technology or specification inputs, new designs may be created in a few hours. This methodology is adaptable to other DAC and circuit architectures. Generation of mixed-signal analog blocks can be approached in several ways. In the top-down, hierarchical approach constraint values are passed down through layers of the design, with the bottom layer corresponding to the transistors. This approach was used in an earlier paper (2) with the currentswitched DAC used as an example. The hierarchical approach is very useful at higher system levels, but near the transistor level a flat optimization approach may offer advantages.When

Fig. 1 illustrates the module generation methodology. Input data is separated into information classes, which are used during the optimization step to find the best set of design variables. The design variables are then passed to the layout program, creating the DAC module. Design optimization can be further decomposed into two parts, the optimization algorithm and the design estimation process. Technology Info

DAC Specs

MOSFET model Matching = f(w,l) Design Files for Estimation

Circuit Simulations Circuit Synthesis: Optimization & Estimation

Layout Database Topology Information

Constrained, Mixed Integer Optimization

Optimized Design Description

DAC Design Equations tools: SpiceOptim & HSPICE

Create Tiling Script

Layout Templates DAC Layout Stretch and Tile

Find Minimum Cell Sizes and Size Cells. Create Cells

Circuit Verification: Extract and Simulate

DAC Module Layout

Tile DAC tools: DT, TA, STC

Circuit Verification: Fabrication and Test Figure 1. Module Generation Methodology

1. This research was supported by SRC grant 94-DC-324.

A.

Input Data

There are several types of data used by a module generator. The first data type is design constants, including technology information and certain module specifications, such as the device models, DAC resolution, and the power supply voltage. A second data type is performance specifications used as design constraints, such as DAC linearity, settling time, and bias voltage limitations. The third data type is the design variables. These are parameters for the module design, and are used to compute the sizes of devices and their arrangement in the module. Typically in analog module generation these are represented as continuous variables, but in the case of this module generator there are several variables which must have discrete values. Two examples of this are the number of lsbs per DAC segment, which must be a power of 2, and the number of bias cells, which must be an integer. This implies a mixed integer problem, influencing the choice of the optimization method used. B.

Design Estimation

The design estimation step is used to predict the performance of the circuit for a set of design variables and constants. It is important to predict these results accurately, including process variation, accurate device modeling, and performance of the DAC circuit. This work uses a combination of circuit simulation and analytic modeling. Circuit simulation is used when the full power of SPICE simulation is required for DC and transient modeling. It may be relatively ineffective when a high level result is required. Analytic models are effective when used to calculate system behavior based on well understood relationships. They are inaccurate when used to estimate MOS circuit bias conditions and transient delays, because of the simplifying device model assumptions which must be made. When the two are combined, the module designer can take advantage of both methods, using equations when a relationship is best expressed analytically, and simulation when an explicit expression is difficult to obtain. In this DAC module generator most of the performance estimates are obtained using this combined approach. When DAC linearity is estimated, device bias conditions are simulated to obtain small signal conductances, while device area is used to predict statistical variance of device Vt and Kp. These inputs are used to determine current variance for an LSB current source, which is combined with architecture information to estimate this contribution to DAC non-linearity. The HSPICE circuit simulator was found capable of equation evaluation as well as circuit simulation. All performance estimates for a set of design variable values are computed in one multiple-simulation run. For high speed DAC synthesis, three DC simulations were run to cover worst case bias margins and

INL conditions, a transient simulation was used for DAC settling, and a separate transient was used for determining DAC glitch energy. C.

Layout Methods.

Because of the regular, cellular nature of current-switched DACs, consisting of many similar segments, most manual DAC layouts are implemented with tightly packed abutting cells so as to minimize the interconnection area. The layout synthesis approach implemented here creates a layout with these qualities. The layout synthesis approach uses stretching of library cells for customization to design specifications, and tiling of the created cells to create a compact DAC module. This application to DAC module synthesis is new, but these techniques are well known in the digital world. Unlike more general place and route approaches, with this method the generation of the final layout from a set of design variables is predictable. Consequently the design estimation process can predict the parasitic wiring and diffusion capacitances which will be present in the DAC design for specific design variable values, and circuit performance can be predicted a priori. D.

Optimization

Design optimization for analog circuits is not a new topic (3), but optimizing this DAC modules presents some unique problems. The optimization process must meet constraints and minimize an objective function, such as circuit power or area. Also, the optimization process must be cognitive of the circuit estimation method, in which function evaluations are time consuming and function evaluations in the infeasible region may not produce reliable gradients. The mixed integer formulation creates additional difficulties. Direct approaches to this mixed-integer non-linear programming (MINLP) problem using branch and bound algorithms (4) do not complete in a reasonable time when used with circuit simulation. A faster algorithm for solving the MINLP problem was required. A promising technique separates the problem into a mixed-integer linear programming (MILP) sub-problem, and a separate non-linear programming (NLP) problem which creates linear constraints to form an outer approximation to the constraint space (5). For this implementation a simpler means of creating the outer approximation was found, using a supporting hyperplane algorithm (6). The key feature of these improved algorithms is that the search for the mixed integer solution is separated from the explicit use of circuit simulation/analysis. In this optimization, the mixed integer nature of the design space actually speeds convergence, by limiting the choices of possible solutions at the end of the optimization, and the solution time rivals the

III. DAC Architecture The DAC architecture is a current output structure, using PMOS devices to source current. This is compatible with video DAC application requirements, and the architecture may also be used with an I/V converter to create a voltage output. The architecture uses a two dimensional array of current sources (8), with a local row / column digital decode, which allows individual selection of each cell. The segment cells in the main section of the DAC are M lsb in value, and a section of lsb segments is placed across the top of the array. Digital information is routed in from the top and the sides of the array, and analog signals are passed through a central vertical bus, minimizing capacitive coupling between digital and analog signals. Where digital column signals must cross over analog signals they are shielded. Rows and columns are selected in an order which minimizes gradient effects from both process and supply drop gradients (9). Additionally, the right and left halves of the rows are selected in a complementary way, to reduce vertical gradient effects. Bias cells are placed in the center of each half row to cancel IR drop and gradient effects to first order. Row and column driver circuits are placed on the edge of the cell. These circuits include a clocked latch and a line driver. Latches are also placed in every cell to eliminate glitches due to differences between row and column signal delays. Fig. 2 shows the DAC cell placement. The DAC segment cell is illustrated in Fig. 3. After the cell select decode, the select signal is latched and an inverter creates complimentary levels for the current switch formed by MS1 and MS2. The current source devices M1 and M2 create a cascoded current source, for high output resistance, and a high swing bias is used (10). Segment current sources use M current source transistor pairs to create the segment current. Power supplies are separated for digital and analog functions. The LSB cells differ slightly, with single current sources and no digital decoding. The design has 19 independent design variables, including 4 for DAC architecture, 9 for analog performance related device sizing, and 6 for digital datapath device sizing.

CLK

Decode Column and LSB Latch and Drivers cells

bias

m-bit segment cells

Analog Bus

m-bit segment cells

bias

LSB

m-bit segment cells

cells

m-bit segment cells

Row Latch/Drivers

LSB

Decode

This algorithm has been used successfully on DAC, opamp, and bias circuit optimizations. Optimization time is dominated by HSPICE circuit simulations, used to compute constraints values and gradients using finite differences, with each DAC simulation requiring 30 to 60 seconds. The layout process is fast; it requires less than 5 minutes to complete.

LSB bits

Column Input (Mid. bits)

Row Input (MSB bits)

time for the equivalent NLP problem using the MINOS package (7). Also, it only requires accurate constraint computation in the region where the constraints are feasible, relaxing requirements on the circuit estimation function. Disadvantages of this algorithm are that it requires an initial feasible point and a convex constraint space, and that it finds locally optimal solutions. These have not been significant drawbacks in the module optimizations investigated in this work.

Analog signal I/O Figure 2. DAC Module layout clk

Col Sel Row Sel Row-1 Sel

Cell Select Decode

avdd

TSPC Latch avdd Bias Cbias

selbar

MS2 dump

avss

M1 M2 MS1

sel

out

Figure 3. Switched Current Source DAC segment cell schematics.

IV. Module Optimizations and Experimental Results The DAC optimization problem, including constraints to ensure both analog circuit performance, and digital signal integrity, comprises 19 design variables and 44 constraints. This is too large an optimization to complete in one step, but a natural split between the analog circuits and digital signal path occurs at the cell level latches. The optimization problem is solved with two optimizations run in sequence -- an ‘analog’ optimization with 13 variables run first, setting variables which affect analog circuit performance. This is followed by a ‘digital’ optimization with 6 variables including loading effects from the ‘analog’ results, which sizes circuits in the DAC digital signal path. All second order static and transient effects were included in these optimizations. A 1.2 µm process was modeled for this project. The discrepancies between fit BSIM 2 models and measured devices were compensated for in circuit estimation. Worst case design techniques were used to bracket performance predictions. Statistical device mismatch due to random and gradient effects used the model in Pelgrom (11), and mismatch parameters were extrapolated from there. Static linearity was predicted for 3-σ yield. INL due to I-R drops in supplies was modeled. Lead inductance effects on the output signal were included, but chip level issues such as substrate noise coupling and supply lead inductance were considered beyond the scope of the module optimization.

DNL(lsb)

INL (lsb)

0.20

0.6 0.4

0.10

0.2

0.00

0 -0.10 0 255 Code 0 255 Code Figure 5. INL and DNL plots for 8 bit DAC (worst case of 12 parts). 4

400

3

Vout(mV)

300 200

2

100

1 0

0 0 Figure 4. Die photo with 8-b part in lower left, 10-b part on lower right.

DAC modules were created to an 8-bit, 100 MS/s video specification and a static 10-bit spec. Circuit synthesis required 6 hours and 1 hour compute time for the two designs on a DEC Alpha 3000/300. Design development time for synthesis from start to finish is several months -- comparable to custom design. Circuit areas were 0.71 and 0.38 mm2. Fig. 4 is the test chip photograph. TABLE 1. Measured Performance of 8 bit video DAC Name

Specified

Estimated

Measured

Units

INL / DNL Total Error Tsettle (rise / fall) Tswit (rise / fall) Tdelay Glitch Rout Clock Rate

< 1.0 / 0.5 10 > 100

0.6 / 0.06 1.9 7.4 / 4.43 1.6 / 1.0 4.75 0.77 / 0.62 10.5 101

0.64 / 0.18 3 5.5 / 5.25a 1.8 / 1.1 NA 0.74 / 0.46 12.5 225

lsb lsb ns ns ns lsb*Ts kΩ MS/s

a. Settling to within 2% of final value.

TABLE 2.

Measured Performance of static 10-bit DAC

Name

Specified

Estimated

Measured

Units

INL DNL

2.0 0.5

1.87 0.16

2.1 1.6

lsb lsb

These DAC modules have been tested. For the 8-bit DAC, table 1 shows the performance specification, estimated 3-σ worst case performance from optimization, and measured performance. All 12 parts fabricated were functional, and met static specifications. INL and DNL are worst measured for these 12 parts. Linearity and transients are illustrated in Figs. 5 and 6. The 10 bit prototypes were tested for static linearity only. All parts were functional, but none met DNL specs. Worst case results are summarized in table 2.

Time 10

0

Time (ns)

20

Figure 6. Measured switching and glitch performance for 8-b DAC.(50Ω)

Most of the discrepancies between estimated and actual performance were caused by unmatched adjacent geometry between segment and lsb current sources. Process gradients were also slightly larger than expected. Corrections for both effects can be easily incorporated into the module generator. VI. Conclusions This work has demonstrated module generation for high speed current switched Digital/Analog Converters. Tight coupling of layout and synthesis resulted in compact layouts with accurate performance prediction. A new MINLP optimization algorithm is used. Sources of error have been identified for inclusion in future design cycles. References 1.

G. Jusuf, P.R. Gray, and A.Sangiovanni-Vincentelli, “CADICS Cyclic Analog-to-Digital Converter Synthesis.” Proc. ICCAD, Nov. 1990, pp. 286-289. 2. H.C. Chang, E. Liu, R. Neff, et al, “Top-Down, Constraint-Driven design methodology based Generation of Interpolative Current Source D/A Converters,” Proc. CICC, May, 1994, pp. 15.5.1-4. 3. W. Nye et al, “DELIGHT.SPICE: An Optimization-Based System for the Design of Integrated Circuits,” IEEE Trans. CAD, 7(4), April 1988. 4. P.C. Maulik, L. R. Carly, and R. A. Rutenbar, “A MINLP Approach to Analog Circuit Synthesis.” Proc. DAC, June, 1992, pp. 698-703. 5. M.A. Duran and I.E. Grossmann, “An Outer-Approx. Algorithm for a Class of MINLPs. Mathematical Programming, 36:307-339, 1986. 6. D.G. Luenberger, Linear and Nonlinear Programming, Addison-Wesley Publishing Co., 2nd Ed., 1984. 7. B.A. Murtagh and M.A. Saunders, “MINOS 5.1 User’s Guide,” Technical Report SOL 83-20R, Stanford University, Dec. 1983, rev. Jan. 87. 8. V. W-K Shen, and D. A. Hodges, “A 60ns Glitch Free NMOS DAC,” in ISSCC Dig. of Tech. Papers, 1983. 9. Y. Nakamura, T. Miki, et al, “A 10-b 70-MS/s CMOS D/A Converter,” IEEE JSSC, vol. SC-26, pp 637-642, April 1991. 10. L. Letham, B.K. Ahuja, et al., “A High-Performance CMOS 70-MHz Palette/DAC,” IEEE JSSC, SC-22(6), December 1987, pp. 1041-47. 11. M.J.M. Pelgrom, A. Duinmaijer, and A. Welbers, “Matching Properties of MOS Transistors,” IEEE JSSC, SC-24(5), Oct. 1989, pp. 1433-40.