a multilevel inverter with reduced number of switches

A MULTILEVEL INVERTER WITH REDUCED NUMBER OF SWITCHES A. Rakesh Kumar, PG Scholar, Department of EEE, Jerusalem College of Engg., Pallikaranai, Chennai-600100 [email protected]

V. Karthikeyan, Research Scholar, Jerusalem College of Engg., Pallikaranai, Chennai-600100 [email protected]

Abstract: This paper proposes a multilevel inverter with reduced number of switches. Compared to conventional inverters, the proposed VR topology for 17 level gives higher leveled MLI and thus harmonics is reduced. The use of an H bridge plays the key role of reducing the number of switches particularly for higher levels. Here, a new Sine Property method to adjust the step angles of each level in the output is implemented to reduce the harmonics in the output waveform. The simulation is performed using MATLAB package and the results are presented for R and RL load. The same is extended to three phase also. The harmonic content thus reduced is brought to IEEE standards. Index Terms: Multilevel inverter, Harmonics, Sine Property, H bridge, VR method.

I.

INTRODUCTION

The concept of multilevel power conversion dates back to 1980s. The concept of a basic Multi level inverter (MLI) is to add up several D.C sources with proper switching sequence to the switches so as to obtain stepped waveform which resembles much to A.C waveform. Hence D.C to A.C conversion is performed. The advantage of such a method is that it reduces voltage stress on load and quality of voltage and current waveforms is improved.. Some other recent topologies have evolved like cascaded H bridge inverter [1], flying capacitor inverter [2] and Neutral point clamping inverter [3]. There are more topologies which are the combination of the above mentioned topologies. Application of these inverters includes Pumps, Fans, Traction, STATCOM, and LNG Plant [4]. Other application includes Automotive applications, UPS, Wind energy applications, Photovoltaic applications etc,. G. Mondal et al have proposed an inverter with four dc sources. Only five level output voltage is achieved and hence there is a drawback in terms of efficient use of the dc

Dr. V. Jamuna, Professor, Jerusalem College of Engg, Pallikaranai, Chennai-600100 [email protected]

sources[5]. More switches are used than this proposed topology in [6] and hence suffers a drawback in terms of number of switches. In [7] by R. Stala, the topology suffers from capacitor balancing problem. Topologies that utilizes low switching frequency and high power devices are also suggested in [8], but the main drawback is that it has significant amount of low-order current harmonics. It is also unable to exactly manipulate the magnitude of output voltage due to an adopted pulsewidth modulation (PWM) method [9]. The output voltage is affected by the capacitor voltage when modulation index varies to its extreme value of one or zero as proposed by P. Lezana[10]. In [11] and [12], it suffers from the drawback of design and manufacturing of multi winding transformers. Ehsan Najafi et al [13] has proposed a similar topology with H bridge, but suffers from the drawback of additional switches. The sine PWM method that is implemented also introduces higher switching losses which also has been overcome in the present work.

II.

INVERTER TOPOLOGY

This topology is named as Voltage Reversal (V.R) topology and it is basically a combination of two circuits. They are Magnitude generator and Polarity generator. In Magnitude generator part, high frequency switches are used which are operated in high frequency to produce halfsine output, whereas the function of switches in Polarity generator is limited to low frequency since they just act to reverse the voltage. The switches in Magnitude generator operate at twice the frequency of the switches of Polarity generator. Hence a complete cycle is obtained by the combination of both the circuits. The figure 1 shows the 17 level inverter.

S1

Vdc S2

This section should be repeated for higher levels

The MATLAB-Simulink model of the V.R topology is shown in the figure 2.

S14 S3

Vdc

S15

S13

S17

S4

Vdc S12

S5

Vdc

OUTPUT

S18

S16

S11 S6

Vdc S10

Vdc Vdc

S7

S9 S8

Vdc -MAGNITUDE

GENERATOR- -POLARITY GENERATOR-

Fig. 1 Circuit Diagram of V.R topology for 17 level

As seen in the figure, different switches operate during the respective levels. During level zero, all the switches are turned off. During level one to level eight, in the Polarity generator, the switches S15 and S16 are on and during level nine to level sixteen the switches S17 and S18 are on.

Fig. 2 MATLAB - Simulink model of V.R topology

As shown in the MATLAB-Simulink circuit, a total of 18 IGBT’s are used and each IGBT is given separate pulses via the pulse generator block present in MATLAB. The pulses are given with equal pulse width and hence the output obtained without any modulation resembles to a triangular waveform. Hence, the THD content is high and the voltage and current harmonics content is at unacceptable levels. The V.R topology is far better than the other conventional topologies which is shown in the table I. As seen, the V.R topology requires the least number of components and switches compared to the present conventional topologies.

In the Magnitude generator, Level one follows the switching sequence of S2-S3-S4-S5-S6-S7-S8. For level two it is S2-S3-S4-S5-S6-S7-S9, for level three it is S2-S3-S4-S5S6-S10, for level four it follows as S2-S3-S4-S5-S11, for level five S2-S3-S4-S12, for level six S2-S3-S13, for level seven S2-S14, for level eight S1 alone is on. Hence it is also necessary that the switches S1, S2, and S14 should withstand high voltage load. In the above mentioned operation of switches in the Magnitude generator, the switches S15 and S16 are on in the Polarity generator. The whole cycle of operation of switches in the above mentioned sequence will repeat for negative cycle, but the difference being the operation of switches S17 and S18 in the Polarity generator.

Table I. Shows the total number of components required for different topologies in three phase circuit

Sinα(1)=0.5/n, Sinα(2)=1.5/n, Sinα(3)=2.5/n, Sinα(4)=3.5/n,.upto required no. of angles. 3. Find α(1), α(2), α(3), α(4),…… 4. Convert above into radians.

Fig. 3 Shows the number of switches required in three phase for the conventional topologies and V.R topology.

Hence, V.R topology is far superior in terms of number of switches and the associated number of levels generated compared to the other conventional topologies. III.

SINE PROPERTY METHOD

Many modulation techniques are provided like equal PWM, space vector modulation, sine PWM methods. But the switches need to operate at high frequency and hence switching losses are also associated with it. In [14], sine pulse width modulation is provided, but again there is need of high frequency switches and associated switching losses are unavoidable. These modulation techniques are the most conventional techniques used so far to reduce the THD content in the output.

5. Convert the above radians angle values into time duration (sec) by using the below formula. α(sec;1, 2, 3,4….)= α(rad;1, 2,3…..)*K, Where, K=0.0031847 Note: For different values of frequency, the value of K alone will change. The switching angles are converted to time period (seconds) for convenience of providing pulses in the MATLAB-Simulink circuit. However, step 4 calculations are sufficient if one aims at providing switching pulses in terms of radians or degrees. Hence, the Sine property is also flexible in terms of providing pulses to the switches. IV.

SIMULATION RESULTS

This section shows the simulation results performed taking R as well as RL load. The value of R is taken as 100 ohms and the corresponding current is found to be 3.251 amps. The current and voltage THD is found to be 4.57% by FFT analysis which is well within the IEEE standards.

The present work of reducing the THD content in the output, known as Sine Property method avoids the switching losses and hence the quality of output waveform is highly improved. The use of Sine Property gives the appropriate switching angles in terms of time (sec) so that the output waveforms resembles to sine waveforms. Instead of very high frequency operation as in conventional modulation techniques, this method will just adjust the step angles of each level to provide the output waveform a sine shape. Hence, reduced THD is achieved. The calculation of switching angle is done by the following processAssumptions: 1. Output is 50 Hz A.C. 2. Odd no. of leveled MLI. Calculations: 1. Find n by using the formula, n= (No. of levels-1)/2 2. Desired Firing angle (in terms of degree): Fig. 4. Shows the output voltage waveform using Sine property for R load and the associated FFT analysis

The MATLAB simulations are also done for an RL load. The resistance and inductance value are taken as 10 ohms and 318e-3 H. The FFT analysis for both the current and voltage waveforms are done and the THD is found to be 1.10% and 7.85% respectively. The current is found to be 2.919 amps.

Fig. 6. Shows the output current waveform using Sine property for RL load and the associated FFT analysis

Fig. 5. Shows the output current waveform using Sine property for R load and the associated FFT analysis

The MATLAB-Simulink circuit for three phase is shown in figure 8 and the simulation is performed. The FFT analysis reveals the THD value to be 4.19%. The simulation is performed taking R load. It is also appreciating to obtain the fundamental component enhanced around 325 volts in both the cases of R and RL load. Hence, the r.m.s voltage of 230 volts is very much possible. Fig. 7. Shows the output voltage waveform using Sine property for RL load and the associated FFT analysis

V.

CONCLUSION

In this paper, a 17 level V.R inverter topology with the possibility of going for higher level MLI is proposed. The use of Sine property method reduces the harmonic content in the output. Here the H bridge reduces the complexity of the conventional circuit by avoiding the switching strategy of negative cycle. This topology is suitable particularly for higher level inverter where the effect of reduced switching losses due to less number of switches is observed. This topology when used in converters for PV systems [15], HVDC and FACTS offers maximum benefits in terms of reduced switching losses and cost benefits. The simulation results performed on the 17 level inverter are a justification of the improved performance of the inverter. REFERENCES

Fig. 8. Shows MATLAB-Simulink circuit for three phase

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Fig. 9. Shows the three phase output voltage waveform for R load and the associated FFT analysis

[10]. P. Lezana and J. Rodriguez, “Mixed multicell cascaded multilevel inverter,” in Proc. IEEE ISIE, 2007, pp. 509–514. [11]. D. A. B. Zambra, C. Rech, and J. R. Pinheiro, “A comparative analysis between the symmetric and the hybrid asymmetric nine-level series connected H-bridge cells inverter,” in Proc. Eur. Conf. Power Electron. Appl., 2007, pp. 1–10.

[12]. R. Teodorescu, F. Blaabjerg, J. K. Pedersen, E. Cengelci, and P. N. Enjeti, “Multilevel inverter by cascading industrial VSI,” IEEE Trans. Ind. Electron., vol. 49, no. 4, pp. 832–838, Aug. 2002. [13].Ehsan Najafi, Abdul Halim Mohamed Yatim “Design and Implementation of a New Multilevel Inverter Topology” IEEE transactions on industrial electronics, vol. 59, no.11, November 2012, pg 4148-4154. [14]. Joachim Holtz, “Pulse width Modulation-A Survey”, IEEE transaction on industrial electronics, Vol. 39, No. 5, December 1992. Page 410-420. [15]. Carlo Cecati, Fabrizio Ciancetta, and Pierluigi Siano, “A Multilevel Inverter for Photovoltaic Systems With Fuzzy Logic Control” IEEE Transaction on industrial electronics , Vol. 57, No. 12, December 2010, pg 4115-4125. A.Rakesh Kumar is currently pursuing his M.E Power Electronics and drives in Jerusalem college of Engineering, Anna University, Chennai. He received his B.E degree in electrical and electronics from D.M.I College of Engineering, Anna University, India in 2011. His research interest includes Multilevel inverter and embedded systems.

Karthikeyan. V received his B.E (Electrical & Electronics Engineering) from Madurai Kamaraj University in 1999 and his M.E (Power Electronics & Drives) from Anna University, Chennai in 2005. He is currently working toward his Ph.D. in the Department of Electrical and Electronics Engineering, Jerusalem College of Engineering, Chennai. He has been working in teaching field for about 7 years. His research interests are Power Converters, Power Quality and Renewable Energy Systems. He is a member of IEEE Power Electronics Society (PELS) and Life member of ISTE.

V.Jamuna is Professor in Electrical and Electronics Engineering Department, Jerusalem College of Engineering, Chennai, India. She received her B.E. degree in Electrical & Electronics Engineering from St.Peter’s Engineering College, Madras University, Chennai, India in 1999, M.E. degree in Power Electronics and Drives from Anna University, Chennai, India in 2005, PhD from Anna University in 2010. She has secured fifth university rank in her P.G degree. She has 12 years of teaching experience. She has published over 20 technical papers in national and international conferences proceedings / journals. She is life member of Indian Society for Technical Education, Institution of Electrical and Electronics Engineers. Her research interest includes Induction Motor Drives and Neural Network.