Mitel Semiconductor. Cheney Manor, Swindon, Wiltshire ... RF applications. The process features very ... a full suite of passive components and 3 levels of metal.
A New Complementary Bipolar Process featuring a Very High Speed PNP. M C Wilson, P H Osborne, S Nigrin, S B Goody, J Green, S J Harrington, T Cook, S Thomas and A J Manson. Mitel Semiconductor Cheney Manor, Swindon, Wiltshire, SN2 2QW, U.K. Abstract This paper introduces "Process HJ" a new high speed, fully complementary bipolar technology suitable for low power RF applications. The process features very high frequency PNP transistors of 20GHz and NPN transistors of 30GHz, respectively. Process HJ also incorporates a full suite of passive components and 3 levels of metal. In this paper process HJ is described and results, mainly for the PNP, presented.
1.
Introduction
The RF communications market, particularly mobile communications require technologies of very high performance and low power, in some cases driving technology towards expensive SiGe doped bases or SOI substrates. Here, a high performance wholly silicon complementary process technology has been developed. Generally, the complementary approach enables more efficient design of power consumption stages, synthesisers, amplifiers and active filters for high bandwidths. For this process a PNP was designed to have a comparable performance and current handling to the NPN so as to give much greater design flexibility. The resulting complementary is considered ideal
for low voltage, low power mixed signal RF and IF applications. Previously published complementary processes have been reported with a relatively low performance PNP [1],[2] or have not been fully isolated [3]. In this paper we introduce complementary process technology "Process HJ" and present electrical characterisation data and initial circuit performance.
2.
Process Description
Process HJ is based on an earlier double polysilicon self-aligned NPN technology [4] but has been extended to include small emitters down to 0.6µm (as-drawn), etched polysilicon with TEOS oxide planarisation, narrow trench isolation, planarised silicon dioxide inter-metal dielectric layers and composite oxide/nitride passivation. The resulting process has been scaled both laterally and vertically. The inclusion of a fully integrated, fully isolated PNP has been achieved with no loss of performance to the NPN. The process details have been described more fully elsewhere [5]. Process HJ includes NPN transistors, vertical PNP transistors, lateral PNP transistors, high and low value polysilicon resistors, low value capacitors (with an optional high value capacitor), integrated
inductors, ESD protection and substrate contacts. For full triple-layer metallisation the process uses 7 photomasks more than our high performance NPN-only process, ("Process HG"). The additional photo operations are for low tolerance implant clearance masks. The buried layers for the PNP are formed by deep implants, optimised for zero defects, but without any degradation in performance. The n-type epitaxial layer is determined by the NPN, and over-doped with an implanted p-well for the PNP. The minimum photolithographic feature is 0.6µm, for the emitters. Isolation is achieved by 0.8µm wide, 7µm deep trenches. Contact to the base regions is made using polysilicon extended contacts, doped appropriately. The emitter-base junctions are formed from shallow base implants and implantedpolysilicon emitters and activated by rapid thermal annealing. The process has 3-level metallisation with a contact pitch of 2.4µm at the first level. The NPN and PNP transistors are shown schematically in cross-section in figures 1 and 2.
3.
Results and Discussion
Typical device parameters are shown in Table 1. The current gains of NPN and PNP transistors were 150 and 50 respectively yielding beta-Early voltage products of 5250 and 1650 respectively. The collectoremitter breakdown voltages were 3.5V and 4.5V for the NPN and PNP devices, respectively. Figures 3 and 4 are average Forward Gummel plots of NPN and PNP transistors respectively and show constant gain over 6 decades of current, in each case. The curves are mean values from 686 sites distributed
across multiple wafers and lots. Good ideality was observed indicating good quality junctions. As stated earlier, an aim of this work was to achieve a complementary process with performance-matched NPN and PNP transistors. Initially, common process stages were used to form NPN and PNP but this resulted in a peak cut-off frequency for the PNP of only 9GHz and insufficient performance for a true complementary. As a result, the PNP transistors were formed independently to allow full optimisation and enhanced performance. This resulted in a much higher frequency and a near-true complementary. The results can be seen in figures 5 and 6 which show the variation of the cut-off frequency (fT) with collector current (Ic) at a Vce of 3V for both device types. The peak fT for the NPN was 30GHz at 1.3mA and for the PNP a much improved 20GHz at 0.9mA. In both cases, the degradation in cut-off frequency at high collector currents is attributed to the Kirk effect and carrier saturation at the basecollector junction. The PNP exhibits a slightly more pronounced degradation beyond the fT peak, compared to the NPN device, due to its higher collector resistance. The PNP collector was optimised for performance, voltagebreakdown and yield. The resulting PNP transistor exhibited an excellent peak fT, a 4.5V collector-emitter breakdown and a forward beta of 50. Figure 7 shows Gummel plots from multiple PNP transistor arrays. The arrays comprised up to 24K minimum geometry (0.6x1.6µm) transistors. In this case only results for 3K and 24K transistors are shown for clarity. In all cases the transistors exhibited current scaling with array size. The result is particularly significant for the PNP as it indicates the entire active regions,
including the deep implanted layers were of good quality.
4.
Circuit Performance
Initial circuit performance has been demonstrated using both NPN and PNP ring oscillators. The ROs for the NPN devices were 11-stage CML circuits with a divide-by-sixteen stage attached. For minimum geometry NPN devices the power delay product was 20fJ with a minimum gate delay of 31ps at 300µA. The ROs for corresponding PNP devices were 41-stage CML circuits and minimum geometry devices exhibited a power delay product of 40fJ with a minimum gate delay of 50ps at 300µA. Additional circuits have been designed including dynamic range RF amplifiers, RF down-converters and up-converters for media tuners and pre-amplifiers for optical disc drives.
5.
Summary
A new complementary bipolar technology has been described based on the successful integration of a very high performance PNP transistor into an existing high performance NPN process. Both transistor types have shown high current gains, good voltage-breakdowns and high Early voltages. Excellent PNP cut-off frequencies of 20GHz were achieved alongside NPN cut-off frequencies of 30GHz. Arrays of 24K PNP transistors exhibited good ideality and low leakage. This, in addition to a full range of passive components, make HJ ideal for low power, low voltage mixed signal, linear RF circuits.
6.
Acknowledgements
The authors would like to thank our Mitel collegues D Sawyer and A Madni and all members of the Swindon Fab. This work was part funded by the European Commission TIBIA II program.
7.
References
[1] J. Warnock et. al. "High performance complementary bipolar technology", 1993 VLSI Tech.Symp. Dig. Tech. Papers, pp75-76, Tokyo. [2] H Miwa et. al. "A complementary bipolar technology for low cost and high performance mixed analog/digital applications", Proc. IEEE 1996 BCTM pp185-188, Minneapolis. [3] T Onai et. al. "An NPN 30GHz, PNP 32GHz fT complementary bipolar technology," Proc. IEEE 1993 IEDM, pp63-65, Washington. [4] P C Hunt and M P Cooke, "Process HE: A highly advanced trench isolated bipolar technology for analogue and digital applications," Proc. 1988 IEEE CICC, p22.2.1, Rochester, New York. [5] M C Wilson et. al. "Process HJ: A 30GHz NPN and 20GHz PNP complementary bipolar process for high linearity RF circuits", Proc. IEEE 1998 BCTM, Minneapolis. To be published.
Table 1. Typical device parameters. Param. Cond. NPN PNP Unit Emit. 0.6 0.6 µm size x3 x3 Hfe Vbe=0.8V 150 50 Vcb=0V Ic(on) Vbe=0.8V 40 15 µA Vcb=0V BVcbo Ic=1µA 12 9 V BVces Ic=1µA 12 9 V BVceo Ic=1µA 3.5 4.5 V BVebo Ie=1µA 3 3 V Vaf 35 33 V fT Vce=3V 30 20 GHz (@Ic mA) (1.3) (0.9) Re 15 18 Ω Rc 100 320 Ω
Emitter
Base
30
Collector
25
Vce 3V
oxide
20 P+
P+
base
15
DC
epitaxy (n-)
10
Oxide
BN
5
CS
0 1E -05
CS
Substrate (p-)
1E -04
1E -03
1E -02
Ic (A)
Figure 1. Schematic cross-section of a NPN transistor. Emitter
Base
N+
Base
Collector
Oxide
Oxide Oxide
Well
N+
25
DC
pwell
Figure 5. fT vs Ic plot for 0.6x3.0µm emitter NPN.
BP
20
Vce=3V
BSUB
CS
Oxide oxide Substrate (p-)
15 CS
Figure 2. Schematic cross-section of a PNP transistor.
10 5 0 1E -05
1E -04
1E -03
1E -02
Ic (A)
Figure 6. fT vs Ic plot for 0.6x3.0µm emitter PNP.
Figure 3. Average Gummel plot for 0.6x3.0µm emitter NPNs.
1E -01 1E -02 1E -03 1E -04 1E -05 1E -06 1E -07 1E -08 1E -09 1E -10 0.50
Ic Ib
0.60
0.70
0.80
0.90
Vbe (V)
Figure 7. Gummel plots of parallel arrays of 3k and 24k PNP devices.
Figure 4. Average Gummel plot for 0.6x3.0µm emitter PNPs.
