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A New Concept of High-Voltage DC–DC Conversion Using Asymmetric Voltage Distribution on the Switch Pairs and Hybrid ZVS–ZCS Scheme Huai Wang Henry Shu-Hung Chung Adrian Ioinovici Suggested Citation H. Wang, H. S. H. Chung, and A. Ioinovici, " A new concept of high-voltage DC–DC conversion using asymmetric voltage distribution on the switch pairs and hybrid ZVS–ZCS scheme," IEEE Trans. on Power Electron., vol. 27, no. 5, pp. 2242-2259, May 2012.
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A New Concept of High-Voltage DC–DC Conversion Using Asymmetric Voltage Distribution on the Switch Pairs and Hybrid ZVS–ZCS Scheme Huai Wang, Student Member, IEEE, Henry Shu-Hung Chung, Senior Member, IEEE, and Adrian Ioinovici, Fellow, IEEE
Abstract—A new concept of high-voltage dc–dc power conversion is presented in this paper. Its distinctive feature lies in distributing the high input voltage asymmetrically between two primary-side series-connected switch pairs. This allows using switches of optimal ratings in their respective class: the lowvoltage switch pair implemented with MOSFETs only, and the high-voltage switch pair implemented with insulated gate bipolar transistors (IGBTs) only. As the switches in a switch pair are of the same type and voltage rating, they are maximally utilized. With an active snubber on the secondary side of the isolation transformer, a hybrid zero-voltage-switching–zero-current-switching (ZCS) scheme, which is different from the zero-voltage and zerocurrent-switching technique, is realized and makes all IGBTs be zero-current-switched and all MOSFETs be zero-voltageswitched from very light load to full load condition with minimal circulating energy. The ZCS snubber energy is completely released to the load, leading also to a duty-cycle gain. The operating principles, dc analysis, and design guidelines will be given. A 2-kW, 1500/48-V experimental prototype has been built and evaluated. The measured efficiency of the converter is found to be 92.4% at the rated condition. Index Terms—DC–DC power conversion, high input voltage, soft switching.
I. INTRODUCTION OR high-power applications requiring input–output electrical isolation, converters containing switch pairs are usually adopted. The most popular structure is the full-bridge (FB) converter [1], [2] with two switch pairs connected in parallel. Another one is the three-level (TL) converter [3]–[10], [22], [26] with two switch pairs connected in series so as to withstand high input voltage. Fig. 1 shows three possible switch pairs using MOSFETs and insulated gate bipolar transistors (IGBTs).
F
Manuscript received December 31, 2010; revised August 17, 2011; accepted October 11, 2011. Date of current version February 27, 2012. This work was supported by a grant from the Research Grants Council of the Hong Kong Special Administrative Region, China (Project No: CityU 112406). This paper was presented in part at the IEEE Energy Conversion Congress and Exposition, Atlanta, Georgia, September 12–16, 2010, and at the IEEE Applied Power Electronics Conference and Exposition, Fort Worth, Texas, March 6–10, 2011. Recommended for publication by Associate Editor M. Vitelli. H. Wang and H. S.-H. Chung are with the Center for Power Electronics and School of Energy and Environment, City University of Hong Kong, Kowloon, Hong Kong (e-mail:
[email protected];
[email protected]). A. Ioinovici is with the Department of Electrical and Electronics Engineering, Holon Institute of Technology, Holon 58102, Israel (e-mail:
[email protected]). Digital Object Identifier 10.1109/TPEL.2011.2173588
Fig. 1.
Three types of switch pair (MOS: MOSFET).
Table I tabulates the possible combinations of these switching pairs in the FB and TL converters. The two switches in each switch pair are operated complementarily. For switch pairs formed by two different types of switches, for examples, in Cases 2 and 5 listed in Table I, the maximum operating voltage is determined by the switch of the lowest voltage rating in the switch pair. The maximum limit of the input voltage and the optimal soft-switching scheme for each case are provided. For IGBTs, zero-current-switching (ZCS) is preferable because of the presence of the tail current during their turnOFF process. Otherwise, considerable switching losses will be induced if hard-switching or zero-voltage-switching (ZVS) is applied [11]. For MOSFETs, ZVS is preferable. From the perspective of meeting the input voltage requirement, high-voltage power conversion imposes greater challenges on the choices of the circuit topologies and switching devices to fulfill the needs of achieving high efficiency and power density. In general, the operating frequency of a switching device is inversely proportional to its power rating and the on-state resistance or saturation voltage of a switching device exhibits exponential growth with its voltage rating. This leads to a large volume of passive elements and considerable power losses in high voltage applications by using switching devices of high voltage rating. For the sake of comparison, Fig. 2 shows the available choices for dc–dc converters in terms of the circuit topology, single switch [23], [24] or combination of switch pair, and soft-switching scheme with respect to various input voltage and power levels. One kind of application is the auxiliary power converter in rolling stock transportation systems, such as light rails and metro trains, which are fed with standard high voltage dc lines (e.g., 1.5-kV, 3-kV) [12]. These high voltages are then inverted to supply ac loads and converted to various low dc voltage levels for on-board applications [13]. Conventional
0885-8993/$26.00 © 2011 IEEE
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TABLE I ANALYSIS OF DIFFERENT COMBINATIONS OF SWITCH PAIRS
Fig. 2. Available options on topology, combination of switch pair and soft-switching scheme for dc–dc power converters with different input voltages and output power levels.
electrical architecture performs the high input voltage to low load voltage dc–dc conversion through multiple stages and part of them operate at low frequency (e.g., 50/60 Hz), implying low efficiency and low power density. A promising solution for improving the conversion efficiency and reducing the physical volume is the use of a single-step conversion from a high voltage to a low voltage [14], [15]. In particular, there are three available solutions to convert the 1500 V line to low load voltages in a single step as presented in the chart of Fig. 2. The first one is an FB converter [16], [17], [25], in which high voltage devices are necessary. Switches with voltage rating of 1.7 or 2.5 kV should be used on the primary side. In [16], a secondary-side snubber, with one active switch turned ON and OFF twice in one cycle, is added to assist ZCS of the IGBTs. If the full-wave rectifier is replaced by a current doubler rectifier, two active snubbers are needed for ZCS of all four IGBTs [18]. In [17], two primary-side active snubbers are used to ensure ZCS of the four IGBTs, the auxiliary switches in the snubber are submitted the same voltage stress as the
main switches. The second solution is a TL converter [19], [20]. Four IGBTs with voltage rating of 1.2 kV can be used for the aforementioned specific application. Although ZCS is preferable for IGBTs as stated previously, these TL converters are implemented with ZVS schemes. The third solution is a multilevel structure discussed in [15] and [21]. Four switch pairs composed of eight relatively low voltage devices (i.e., 500/600 V MOSFETs) are used in [9] and [15] and they are switched ON/OFF with ZVS. The converter can achieve high frequency operation and low conduction losses. However, the advantage is counteracted by limited soft-switching range, as it is typical in ZVS converters. This paper proposes a novel dc–dc conversion concept that distributes the high input voltage asymmetrically between two series-connected switch pairs. Similar to Case 5 shown in Table I, with the same switching devices, the maximum input voltage can be increased with this concept. With asymmetric voltage stresses operation, the ZVS load range is wide varying from very light load to full load. The voltage distribution
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is determined by the duty cycles of the upper switches in the switch pairs. Specifically, this concept can be applied for the auxiliary power converters in railway applications fed by 1.5-kV dc lines. It features the following properties: 1) asymmetric voltage distribution, allowing the use of one pair of 600-V MOSFETs and another pair of 1200-V IGBTs; 2) hybrid ZVS– ZCS soft-switching scheme, which is fundamentally different from the zero-voltage and zero-current-switching [22] technique in which all the four switches are submitted to the same voltage, 3) the energy used for ZVS from the freewheeling stage to the energy transfer stage transition is provided by the dc-link capacitor and dc-blocking capacitor, implying a wide ZVS range for the MOSFET switch pair from very light loads to full load. Comparing with the converters having active snubbers on the primary side, the proposed secondary-side snubber has the following advantages. First, the voltage stress on the auxiliary switches is much lower, thus requiring low-voltage switches only. Second, the resonant energy for achieving ZCS is completely released to the load while the one in the primary-side snubber is circulating within the circuit or with the input. Thus, the proposed snubber minimizes circulating energy loss and results in a duty-cycle gain. There is a fundamental difference between the proposed method and the one in [26], even if the switches in a switch pair in both methods are operated asymmetrically. In [26], the duty cycles of the two switches in a switch pair are asymmetric. However, the two switch pairs are operated in a symmetric manner. Thus, the switches in the switch pairs still have the same voltage stresses. In the proposed concept, not only are the duty cycles of the switches in a switch pair asymmetric, the duty cycles between the two switch pairs are also asymmetric. Such method gives a new dimension to flexibly control the voltage stress across the switch pairs. This paper is organized as follows. Section II proposes the circuit structure and power conversion concept of the proposed converter. Section III presents its operating principles. Section IV presents the steady-state analysis of the proposed converter, including voltage distribution characteristic and voltage conversion ratio. Section V provides the design guidelines. Section VI presents the experimental results of a 2-kW, 1500/48-V prototype. II. CONVERTER WITH ASYMMETRIC VOLTAGE DISTRIBUTION ACROSS SWITCH PAIRS The circuit structure and the concept of the power conversion with asymmetric voltage distribution on the switch pairs are given as follows. A. Circuit Structure Fig. 3(a) presents the proposed converter with two switch pairs SP1 and SP2 , which are composed of two IGBTs S1 , S2 , and two MOSFETs S3 , S4 connected in series, respectively. The intermediate stage is a dc-blocking capacitor Cb and highfrequency isolation transformer. The turns ratio of the transformer from primary-to-secondary side is m and its leakage inductance is Llk . VC 1 , VC 2 , and VC b are the voltages across
the dc-link capacitors C1 , C2 and the capacitor Cb , respectively. To improve the output current capacity, a current doubler rectifier [27] is applied on the secondary side, formed by two inductor–diode branches Lf 1 –DR 1 and Lf 2 –DR 2 . A novel snubber composed of switches Sa 1 , Sa 2 , diode Da , capacitors Cr 1 , Cr 2 , and inductor Lr is shown in Fig. 3 to fulfill ZCS of S1 and S2 . Sa 1 is used to provide ZCS condition for S1 while Sa 2 is used to provide ZCS condition for S2 . The function of Sa 1 and Cr 1 is to reduce isec , and thus ip , from positive value to zero before S1 turns OFF. And the function of Sa 2 , Da , Lr , and Cr 2 is to increase isec from negative to zero before S2 turns OFF. B. Concept of DC–DC Conversion With Asymmetric Voltage Distribution Across Switch Pairs It will be proved in Section IV that the voltages on input capacitors C1 and C2 are inversely proportional to the duty cycles D1 and D2 , implying that k=
D2 VC 1 = VC 2 D1
(1)
where k is defined as the voltage distribution factor, D1 and D2 are the steady-state duty cycles of upper switches in each switch pair, S1 and S3 . As shown in Table I, the available solutions distribute the input voltage equally among the switch pairs (i.e., k = 1). Referring to (1), the concept proposed here allows asymmetric voltage stresses on each switch pair by adjusting the value of k. One of the implications is that it can provide an additional degree of freedom to select switching devices and allow for optimal combinations in terms of the operating frequency, switching loss, conduction loss, and cost effectiveness. III. OPERATION PRINCIPLES OF THE PROPOSED CONVERTER A simplified control block diagram illustrating the generation of the driving signals for S1 –S4 and Sa 1 , Sa 2 is presented in Fig. 3(b). The asymmetric duty cycles for S1 and S3 are obtained by using different control signals having a ratio of k for the pulsewidth modulation PWM1 and PWM2 modules in the DSP controller. With designed parameters for the ZCS snubber, the conduction interval of Sa 1 and Sa 2 are constant. Therefore, the turn ON and turn OFF instants of Sa 1 depends on the turn OFF time of S1 (i.e., the control signal vcon ). Sa 2 is turned OFF at the end of a switching cycle, implying a fixed turn ON time instant. The voltages across C1 and C2 are also sampled for overvoltage protection and fine tuning k if necessary for limiting the discrepancy between the actual voltage stress distribution and the desirable one. The operation consists of nine modes in one switching cycle. The timing diagram for a steady-state cycle is shown in Fig. 4(a). Fig. 4(b) and (c) shows the detailed operation of the two auxiliary snubber switches Sa 1 and Sa 2 , respectively. For the sake of simplicity, the analysis is referred to the secondary side of the transformer. The equivalent circuits in each operation mode are given in Fig. 5. The voltages across the input capacitors C1 , C2 , and dc-blocking capacitor Cb are assumed constant in steady state and the output inductors Lf 1 and Lf 2 are large enough to
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Fig. 3. Proposed hybrid ZVS–ZCS dc–dc converter with secondary-side ZCS snubber and asymmetric voltage distribution on primary-side switch pairs. (a) Circuit schematic. (b) Simplified control block diagram.
be considered as constant current sources. The parameters used in the following discussions are listed in Table II. Mode 1 [t0 –t1 ]—Transition from freewheeling stage to energy transfer stage I [see Fig. 5(a)]. Before S1 is turned ON, the currents through diodes DR 1 and DR 2 keep constant and the body diode of S2 is conducting as shown in Fig. 5(a)(i) and Fig. 5(a)(ii). When S1 is ON, the current in DS2 is diverted to S1 linearly due to the presence of parasitic inductance LS1 as shown in Fig. 5(a)(iii). After DS2 stops conducting, the current isec increases linearly due to voltage (VC 1 + VC 2 − VC b )/m applied on the leakage inductance Llk /m2 . Thus, the current in DR 1 decreases and reaches zero at t1 , while that in DR 2 increases to the load current. At t1 , current isec increases to iL f 1 and DR 1 is finally blocked. The duration of this mode is given by t1 − t0 = t0−1 = tdl1 +
t1 − t0 = t0−1 = tdl1 + = tdl1 +
LS1 iS2 (t12 ) VC 1
(LS1 + Llk ) [iL f 1 − miS2 (t12 )] + m (VC 1 + ΔV )
where iS2 (t12 ) is the current flowing through DS2 at the instant t12 , i.e., at the end of steady-state cycle, as given by (33). The absolute value of iS2 (t12 ) depends on the load conditions and increases with the reduction of the load. With practical design, at full load, iS2 (t12 ) is approximately equal to zero while at no load iS2 (t12 ) is −iL f 2,nom /m, where iL f 2,nom is the current flowing through Lf 2 under the nominal load condition. Moreover, the duration in which iS1 increases from zero to iL f 1 /m is very short, as compared to the switching period. To simplify the analysis, iS1 is assumed to increase linearly from zero to iL f 1 /m as shown in Fig. 4(a) and the value of LS1 is negligible compared to Llk . Therefore, the duration of t0−1 in (2) is approximated by
(2)
Llk iL f 1 m (VC 1 + VC 2 − VC b )
Llk iL f 1 . m (VC 1 + ΔV )
(3)
Meanwhile, Lr and Cr 2 are in a resonant mode until iS a 2 (current flowing through the body diode of Sa 2 ) reaches zero within t0−1 as shown in Figs. 5(a)–(i) and 4(c).
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Fig. 4. Timing diagram of the proposed converter. (a) General timing diagram during one cycle. (b) Detailed timing diagram during t3 to t5 . (c) Detailed timing diagram during t1 0 to t1 2 .
Mode 2 [t1 –t4 ]—Energy transfer stage I [see Fig. 5(b)–(d)]. During this mode, the energy is transferred from the input to the load through the switches S1 and S4 . This mode can be divided into three substages. Substage I [t1 –t2 ] [see Fig. 5(b)]—Charging of capacitors Cr 1 and Cr 2 . At t1 , the voltage across the secondary-side winding of the transformer becomes positive; thus, the diodes DS a 1 and Da conduct. Capacitors Cr 1 and Cr 2 are charged in a resonant manner with the leakage inductance Llk . The initial value of isec is iL f 1 . Therefore, isec (t) = iL f 1 +
VC 1 + ΔV sin ωr 1 (t − t1 ) mZr 1
vC r 1 (t) = vC r 2 (t) =
VC 1 + ΔV [1 − cos ωr 1 (t − t1 )]. m
By referring isec to the primary side iS1 (t) = ip (t) =
VC 1 + ΔV iL f 1 + sin ωr 1 (t − t1 ) . m m2 Zr 1
After one-half resonant cycle, at t2 , the capacitor voltages vC r 1 and vC r 2 reach their maximum value 2(VC 1 + ΔV)/m and the current isec returns to iL f 1 . The diodes DS a 1 and Da are blocked and the voltages of Cr 1 and Cr 2 are clamped at the maximum level. The time interval of this substage is equal to half of the resonant cycle, that is,
(4) (5)
(6)
t2 − t1 = t1−2 =
π
Llk (Cr 1 + Cr 2 ) . m
(7)
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Fig. 5. Equivalent circuits of the operation modes. (a) Mode 1 (t0 –t1 ). (b) Mode 2 substage I (t1 –t2 ). (c) Mode 2 substage II (t2 –t3 ). (d) Mode 2 substage III (t3 –t4 ). (e) Mode 3 (t4 –t5 ). (f) Mode 4 (t5 –t6 ). (g) Mode 5 (t6 –t7 ). (h) Mode 6 (t7 –t8 ). (i) Mode 7 (t8 –t9 ). (j) Mode 8 substage I (t9 –t1 0 ). (k) Mode 8 substage II (t1 0 –t1 1 ). (l) Mode 9 (t1 1 –t1 2 ).
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TABLE II DEFINITIONS AND PARAMETERS USED IN THE FOLLOWING ANALYSIS
Substage II [t2 –t3 ] [see Fig. 5(c)]—Energy transfer with constant isec . During this substage, all of the voltages and currents in the circuits are assumed constant. Substage III [t3 –t4 ] [see Fig. 5(d)]—Commutation of S1 with ZCS. At t3 , Sa 1 turns ON with ZCS due to the presence of leakage inductance Llk , which starts resonating with Cr 1 to make the current through S1 drop to zero or become negative. The initial voltage of Cr 1 is vC r 1 (t3 ) = 2(VC 1 + ΔV)/m as discussed previously. Therefore, it can be obtained that isec (t) = iL f 1 −
VC 1 + ΔV sin ωr 2 (t − t3 ) mZr 2
VC 1 + ΔV [1 + cos ωr 2 (t − t3 )] m VC 1 + ΔV sin ωr 2 (t − t3 ) . isa1 (t) = mZr 2
vC r 1 (t) =
(8) (9) (10)
It implies that iS1 (t) = ip (t) =
VC 1 + ΔV iL f 1 − sin ωr 2 (t − t3 ) . (11) m m2 Zr 1
When the current through S1 drops to zero, and goes negative, DS1 conducts. S1 is turned OFF at t4 with ZCS when iS1 reaches its negative peak value as shown in Fig. 4(b) (iS1 = isec /m). Therefore, VC 1 + ΔV (12) m √ π Llk Cr 1 t4 − t3 = t3−4 = . (13) 2m Mode 3 [t4 –t5 ]—Transition from energy transfer stage to freewheeling stage I [see Fig. 5(e)]. After S1 is turned OFF at t4 , isec increases to zero from negative values, and then the body diode of S1 , DS1 , is blocked. Therefore, the primary-side transformer voltage drops as shown in Fig. 4(a). As the diode DR 1 is still in the blocking state, iL f 1 is fully supplied by the capacitor Cr 1 before S2 is turned on. After S2 is turned ON, Cr 1 is further discharged until its voltage vC r 1 (t4 ) =
drops to zero as shown in Fig. 4(b). The duration of this mode is approximately equal to t5 − t4 = t4−5 =
Cr 1 (VC 1 + ΔV ) . miL f 1
(14)
It should be noted that although S1 is OFF during this period, the diode DR 1 is still OFF and the resonant energy of Cr 1 is released to the load, contributing to a duty-cycle gain. Mode 4 [t5 –t6 ]—Freewheeling stage I [see Fig. 5(f)]. As vC r 1 reduces to zero at t5 , DR 1 turns ON naturally. iD R 1 increases from zero to iL f 1 while iS a 1 reduces to zero quickly as shown in Figs. 4(a) and 5(f)–(i). Therefore, Sa 1 can be turned OFF with ZCS after a short while since iS a 1 becomes zero. The diodes DR 1 and DR 2 are in freewheeling state. However, unlike that stage with symmetric operation between two switch pairs in TL converter [26], the current flowing through the transformer winding isec increases linearly due to a difference of the voltages on C2 and Cb . This phenomenon is owing to asymmetric operation of the two switch pairs, which will be investigated in Section V in detail. As shown in Fig. 5(f) isec (t) =
mΔV (t − t5 ) . Llk
(15)
This mode ends when t = Ts /2 and S4 is turned OFF with ZVS due to the presence of its parasitic capacitance CS4 . The duration of this mode is Ts (1 − D1 ) t6 − t5 = t5−6 = − tdr 1 . (16) 2 Accordingly, the current isec at t6 is given by mΔV mΔV Ts (1 − D1 ) − tdr 1 . isec (t6 ) = (t6 − t5 ) = Llk Llk 2 (17) Mode 5 [t6 –t7 ]—Transition from freewheeling stage to energy transfer stage II [see Fig. 5(g)]. After S4 is turned OFF at t6 , the equivalent circuit is shown in Fig. 5(g). With initial conditions vC S 3 (t6 ) = VC 2 and ip (t6 ) =
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isec (t6 )/m
It gives that
vC S 3 (t) = VC b + ΔV cos ωr 3 (t − t6 )
isec (t) = −iL f 2 +
1 (18) − ip (t6 ) Zr 3 sin ωr 3 (t − t6 ) 2 2ΔV sin ωr 3 (t − t6 ) + ip (t6 ) cos ωr 3 (t − t6 ) . ip (t) = Zr 3 (19) The process described by (18) and (19) is the resonance occurred among Llk , CS3 , and CS4 . CS3 is fully discharged and CS4 is fully charged by the energy stored in the leakage inductance. DS3 will conduct when the voltage of CS3 reaches zero as shown in Fig. 5(g)(ii). This transition takes place in a similar way as the corresponding process in symmetric FB or TL converters. However, the significant difference lies in that the energy that is provided by Llk is independent of load conditions, which can be observed from (17). It implies that S3 can be turned ON with ZVS from very light load to full load conditions without any additional assisted strategies. S3 is turned ON with ZVS in a short while after DS3 conducts. The current in DR 2 reaches zero at t7 while the current of DR 1 increases to the load current. At t7 , the primary-side current ip negatively increases to −iL f 2 /m. Therefore, the duration of this mode is given by t7 − t6 = t6−7 = tdl2
Llk iL f 2 . + m (VC 2 − ΔV )
(20)
Mode 6 [t7 –t8 ]—Energy transfer stage II [see Fig. 5(h)]. During this mode, DR 1 is conducting and DR 2 is blocked. Energy is transferred from Cb to load through the switches of S2 and S3 . All of the voltages and currents in the circuits can be assumed constant. Mode 7 [t8 –t9 ]—Transition from energy transfer stage to freewheeling stage II [see Fig. 5(i)]. At t8 , S3 is turned OFF with ZVS at the presence of CS3 . isec starts to charge CS3 and discharge CS4 with an approximately constant current isec (t8 )/2 (i.e., −iL f 2 /2). This mode ends when the voltage across CS4 reduces to zero. It implies that t9 − t8 = t8−9
2mCs VC 2 2mCs VC 2 = = −isec (t8 ) iL f 2
Mode 8 [t9 –t11 ]—Freewheeling stage II [see Fig. 5(j) and (k)]. After vC S 4 reaches zero, DS4 is conducting to clamp this voltage at zero. S4 can be turned ON with ZVS after t9 . Therefore, the duration of tdr 2 should be long enough to ensure vC S 4 reaches zero before S4 turns ON, that is, tdr 2 ≥ t8−9 . This mode can be divided into two substages and their equivalent circuits are presented in Fig. 5(j) and (k). Substage I [t9 –t10 ] [see Fig. 5(j)]—Linear increase of isec . During t9 –t11 , diodes DR 1 and DR 2 are conducting and the voltage between the nodes “A” and “B” as indicated in Fig. 5(j) is zero. The secondary-side winding current isec increases slightly from negative values due to the voltage difference ΔV .
(22)
Substage II [t10 –t11 ] [see Fig. 5(k)]—Resonance between Lr and Cr 2 . Cr 2 starts to resonate with Lr after Sa 2 turns ON with ZCS at t10 as shown in Fig. 4(c). The equivalent circuit is presented in Fig. 5(k) with the initial value of vC r 2 (t10 ) = 2 (VC 1 +ΔV)/m, implying that 2 (VC 1 + ΔV ) cos ωr 4 (t − t10 ) m 2 (VC 1 + ΔV ) iS a2 (t) = sin ωr 4 (t − t10 ) . mZr 4
vC r 2 (t) =
(23) (24)
This mode ends when vC r 2 drops to zero at t11 ; therefore, the duration of this substage is √ π Lr Cr 2 t11 − t10 = t10−11 = (25) 2 2 (VC 1 + ΔV ) iS a2 (t11 ) = . (26) mZr 4 According to (22), by neglecting the short period of tdr 2 and t11−12 , one gets isec (t11 ) = −iL f 2 +
m (1 − D2 ) ΔV Ts . 2Llk
(27)
Mode 9 [t11 –t12 ]—Energy transfer stage induced by Cr 2 [see Fig. 5(l)]. During this mode, resonance occurs among the components Lr , Llk , and Cr 2 . At t11 , the snubber diode Da starts conducting, and Cr 2 begins to resonant with both Lr and Llk . vC r 2 becomes negative and the diode DR 2 is blocked. The output inductor current iL f 2 is supplied by both isec and iS a 2 as shown in Fig. 5(l). By neglecting the effect of ΔV during this resonant period vC r 2 (t) = −[iS a2 (t11 ) − isec (t11 ) − iL f 2 ]Zr S sin ωr 5 (t − t11) (28) iS a2 (t) = iS a2 (t11 ) −
(21)
mΔV (t − t9 ) . Llk
Llk [iS a2 (t11 ) − isec (t11 ) m2 Lr + Llk
− iL f 2 ][1 − cos ωr 5 (t − t11 )] isec (t) = isec (t11 ) +
(29)
m2 Lr [iS a2 (t11 ) − isec (t11 ) + Llk
m2 Lr
− iL f 2 ][1 − cos ωr 5 (t − t11 )].
(30)
It implies that the primary-side current flowing through S2 is given by iS2 (t) = −
isec (t11 ) mLr isec (t) =− − 2 [iS a2 (t11 ) m m m Lr + Llk
− isec (t11 ) − iL f 2 ] [1 − cos ωr 5 (t − t11 )] .
(31)
Within one-half of the resonant cycle, isec increases from negative values to zero, and then to positive values. iS a 2 drops
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to zero and then goes to below zero as indicated in Fig. 4(c). Therefore, S2 and Sa 2 can be turned OFF with ZCS after their currents becomes negative, respectively. It can be noted that during this period, the diode DR 2 is blocked and the energy in Cr 2 is transferred to the load, contributing a duty-cycle gain. The duration of this substage is given by t12 − t11 = t11−12 = π Leq Cr 2 . (32) According to (26) and (27) and (31) and (32) iS2 (t12 ) =
(1 − D2 ) ΔV Ts iL f 2 2mLr − − 2 m 2Llk m Lr + Llk 2 (VC 1 + ΔV ) m (1 − D2 ) ΔV Ts × − . (33) mZr 4 2Llk
mCs VC 2 4Leq (VC 1 + ΔV ) tdl2 + − ΔD2 = 2 iL f 2 Ts Ts Lr /Cr 2 (VC 2 − ΔV )Ts Llk iL f 2 m2 Leq (1 − D2 )ΔV − − . (40) m(VC 2 − ΔV )Ts Llk (VC 2 − ΔV ) Detailed proof of (37)–(40) is given in Appendix B and C. It should be noted that the aforementioned equations for ΔD1 are for heavy load conditions when the secondary winding current isec can be assumed to be zero during t01 and t45 . Under light load conditions, with the consideration of isec , the first term [i.e., t45 /(2Ts )] of ΔD1 is approximately presented by C r 1 (V C 1 +Δ V ) , where ¯isec is the average current of isec during 2m (i L f 1 −¯i s e c )T s t45 . The fourth term of ΔD1 is zero due to that isec itself is sufficient to supply the load current, implying that there is no duty-cycle loss during the turn ON transition of S1 . According to (37) and (38), the conversion ratio is given by
IV. STEADY-STATE ANALYSIS M=
A. Steady-State Voltage Stress on Cb The voltage across the dc-blocking capacitor Cb can be derived by calculating the voltage-second values in one steadystate cycle between the midpoints of the two switch pairs, that are, nodes “A” and “B” as indicated in Fig. 3. It can be obtained that 1 VC b = VC 2 + (D1 VC 1 − D2 VC 2 ) 2 Cs VC2 2 Cs VC2 2 VC 1 tdl1 + − . (34) − ip (t6 ) Ts −ip (t8 ) Ts Ts Detailed proof of (34) is given in Appendix A. In practical design, the third term is negligible compared to other ones because of a very small value of Cs and small difference between ip (t6 ) and −ip (t8 ). Therefore, VC b is approximately equal to VC b = VC 2 +
1 VC 1 tdl1 (D1 VC 1 − D2 VC 2 ) − . 2 Ts
(35)
According to (35) ΔV = VC 2 − VC b =
VC 1 tdl1 1 − (D1 VC 1 − D2 VC 2 ) . Ts 2 (36)
B. Voltage Conversion Ratio The voltage-second balances written on the inductors Lf 1 and Lf 2 give Vo 1 = (D1 + ΔD1 ) VC 1 + ΔV 2m
(37)
1 Vo = (D2 + ΔD2 ) VC 2 − ΔV 2m
(38)
where
√ Cr 1 (VC 1 + ΔV ) Llk Cr 1 ΔV ΔD1 = 2 + − 2miL f 1 Ts mTs VC 1 Llk iL f 1 − mTs (VC 1 + ΔV )
(39)
1 (D1 + ΔD1 ) (D2 + ΔD2 ) Vo = . Vin 2m D1 + ΔD1 + D2 + ΔD2
(41)
Practically, the net effect values of ΔD1 and ΔD2 are negligible compared to D1 and D2 . Therefore, (41) can be simplified into M=
Vo 1 D1 D2 ≈ . Vin 2m D1 + D2
(42)
By substituting (1) into (42), the conversion ratio can be represented by M=
1 k D1 2m 1 + k
(43)
C. Voltage Distribution Across Switch Pairs According to (37) and (38) VC 1 Vin (D2 + ΔD2 ) − ΔV (D1 + ΔD1 + D2 + ΔD2 ) . = VC 2 Vin (D1 + ΔD1 ) + ΔV (D1 + ΔD1 + D2 + ΔD2 ) (44) By neglecting ΔV, ΔD1 , and ΔD2 , the steady-state voltage distribution factor is given by k=
k=
VC 1 D2 = . VC 2 D1
(45)
Therefore, the voltage across the switches in each switch pair can be adjusted by varying D1 , D2 , and thus k, allowing for the choice of the optimal combination of switching devices. It should be noted that the input-to-output voltage ratio is not necessary to be constant. The duty cycles of D1 and D2 will be updated accordingly with the required voltage conversion ratio. During the startup, the voltage distribution can be ensured by selecting the ratio between the capacitance values of C1 and C2 . The capacitors C1 and C2 are charged up instantaneously at the beginning to the initial values defined as VC 1 (0) and VC 2 (0), which are assumed to be inversely proportional to their capacitance values. It gives that VC 1 (0) C2 = . VC 2 (0) C1
(46)
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TABLE III DESIGN SPECIFICATIONS OF THE EXPERIMENTAL PROTOTYPE
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a) ZCS condition of S1 : According to (11), to ensure that iS1 drops to zero before t4 Cr 1 ≥
Llk i2L f 1 (VC 1,m in + ΔV )2
(47)
where VC 1,m in is the minimum voltage stress on C1 . b) ZCS condition of Sa1 : After S1 turns OFF at t4 , the energy stored in Cr 1 is released to load until the current in Cr 1 decays to zero; therefore, iS a 1 becomes zero and then Sa 1 can be turned OFF with ZCS without special constraints on the snubber parameters. c) ZCS condition of S2 and Sa 2 : According to (26), (27), (29), and (31), to ensure that iS 2 and iS a 2 drops to zero before t12 , the capacitance value of Cr 2 should fulfill the inequalities TABLE IV RANGES OF DUTY CYCLES WITH RESPECT TO m
Cr 2 ≥
Lr [(1 − D2,m in ) ΔV Ts ]2 4 [(Llk /m2 − Lr ) (VC 1,m in + ΔV )]2
Lr < Llk /m2 .
The DSP controller provides a soft-start function that makes the effective duty cycle increase slowly, and controls the two capacitor voltages (i.e., VC 1 and VC 2 ) in the designed ratio. V. DESIGN GUIDELINES The design guidelines for the proposed converter are illustrated by an experimental prototype. The specifications are tabulated in Table III. This paper focuses on the determinations of the turns ratio of the transformer, leakage inductance (or external inductance if necessary) Llk , the voltages difference ΔV, and the snubber passive components Cr 1 , Cr 2 , and Lr . For other components selection, the design guidelines are similar with conventional cases (e.g., the converter discussed in [9]) and will not be presented here. A. Design Issues 1) Issues on the Turns Ratio of the Isolation Transformer and Duty Cycle Ranges: According to (43) and (45) and the specifications listed in Table III, the duty cycle ranges with respect to different turns ratio of the isolation transformer are shown in Table IV. To allow the proper operation, the values of D1 and D2 should be within [0, 0.5] and [0, 1], respectively. m = 4 is selected to retain reasonable margins of D1 and D2 . Moreover, compared to the cases when m is less than 4 (e.g., m = 2, m = 3), it will reduce the primary-side currents to achieve lower conduction losses of the switching devices. 2) Issues on the Soft-Switching Conditions:
(48) (49)
d) ZVS condition of S3 : As discussed in Section III, the voltage difference ΔV is used to charge the leakage inductance of the transformer Llk during freewheeling stage t5−6 and then the energy stored in Llk provides the ZVS condition for turning ON S3 within the interval [t6 , t7 ]. According to (18), the following condition should be adopted to ensure that the voltage across CS3 drops to zero before S3 turns ON: √ VC 2,m ax 2Llk Cs (50) ΔV ≥ (1 − D1,m ax ) Ts /2 − tdr 1 where VC 2,m ax is the maximum voltage stress on C2 . According to (50), provided that there is a slight difference in the voltages between VC 2 and VC b , S3 will be in ZVS. Practically, the variations of the midpoint voltage between C1 and C2 only affect the duration of the switching transition of S3 . e) ZVS condition of S4 : It is practically easy for S4 to achieve ZVS as the converter is still operating in energy transfer stage before S4 is turned ON. The secondary-side active snubber provides ZCS condition for the IBGTs. Without it, all IGBTs could be switched with ZVS, but not a favorable operation. Moreover, S3 might also be hard-switched at turn ON. 3) Issues on the Current Limits of Switching Devices: a) Current limit of S1 : The maximum current stress of S1 , iS1,m ax , occurs within t1−2 . It should not exceed the preselected maximum current rating of the switching device S1 , defined as IS1,m ax . According to (6), it is given by iS1,m ax =
VC 1,m ax + ΔV iL f 1 + ≤ IS1,m ax . m m Llk / (Cr 1 + Cr 2 )
(51)
b) Current Limit of the Primary-Side Winding During the Freewheeling Stage t5−6 : During the freewheeling stage t5−6 , the current in the primary-side winding flows through S2 and S4 and its magnitude should be less than the preselected maximum current ratings of these devices. According to (17), the condition
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is given by ip (t6 )m ax = ≈
ΔV Llk
Ts (1 − D1,m in ) − tdr 1 2
According to (47)
(Cr 1 + Cr 2 )m in > Cr 1,m in =
(1 − D1,m in )ΔV Ts ≤ min{IS2,m ax , IS4,m ax } 2Llk (52)
where IS2,m ax and IS4,m ax are the preselected maximum current ratings of S2 and S4 , respectively. c) Current limit of Sa 2 : The maximum current flowing in Sa 2 occurs at t11 and from (26), one gets iS a2,m ax =
2 (VC 1,m ax + ΔV ) < IS a2,m ax m Lr /Cr 2
(53)
where IS a 2,m ax is the preselected maximum current rating of Sa 2 and VC 1,m ax is the maximum voltage stress on C1 . 4) Issues on the conduction time of Sa1 and Sa2 and resonant time of t1−2 : The conduction time of Sa 1 is t3−5 and that of Sa 2 is t10−12 . To ensure proper operation of the switching devices, the minimum conduction durations should be larger than reasonable values (e.g., larger than five times of the total turn ON/OFF time of Sa 1 and Sa 2 , respectively). Therefore, according to (13), (14), (25), and (32), the conditions are given by √ Cr 1 (VC 1,m in + ΔV ) π Llk Cr 1 + ≥ 5 (tr 1 + tf 1 ) (54) 2m miL f 1 √ π Lr Cr 2 + π Leq Cr 2 ≥ 5 (tr 2 + tf 2 ) (55) 2 where tr 1 and tf 1 are the turn ON and turn OFF times of Sa 1 , respectively. tr 2 and tf 2 are the turn ON and turn OFF times of Sa 2 , respectively. The time duration of t1−2 is given by (7), which will affect the conduction loss of S1 . The longer the t1−2 is, the larger the conduction losses are induced. Therefore, t1−2 is designed to be less than 25% of the conduction time of S1 . It gives that π Llk (Cr 1 + Cr 2 ) Ts ≤ 25%D1,m in . (56) m 2
1) Boundaries of Llk and Lr : According to (53) Cr 2 ≤
4 (VC 1,m ax + ΔV )
By substituting the minimum value of Cr 1 + Cr 2 represented by (60) into (56) m(VC 1,m in + ΔV )D1,m in Ts mVC 1,m in D1,m in Ts ≈ . 8πiL f 1 8πiL f 1 (61) Therefore, according to (49), (59), and (61), the boundaries of Lr and Llk are given by Llk
20(VC 1,m ax + ΔV )(tr 2 + tf 2 ) 20(tr 2 + tf 2 )VC 1,m ax ≈ . 3πmIS a2,m ax 3πmIS a2,m ax (59)
1) Minimization of the Circulating Current During Freewheeling Stage t5−6 : According to (52), the circulating current in the freewheeling stage t5−6 will jump up with the increase of ΔV under specific Llk . Moreover, by referring to (53) and (66), it can be observed that small value of ΔV is beneficial to reduce the lower boundary of Cr 2 , therefore, allowing reduction of the current stress of Sa 2 . ΔV is designed with its minimum value
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Fig. 6. Graphically trade-off conditions for designing of L lk and C r 1 (m = 4, V C 1 , m in = 900 V, V C 1 = 1000 V, V C 1 , m a x = 1100 V, iL f 1 = 27.8 A, IS 1 , m a x = 20 A, and T s = 20 μS). (a) ΔD1 versus L lk and C r 1 . (b) Approximated current stress of S1 versus L lk and C r 1 .
represented by (65). Therefore ΔV = ΔVm in
√ VC 2,m ax 2Llk Cs = . (1 − D1,m ax )Ts /2 − tdr 1
(69)
According to (36) and (45) ΔV =
VC 1 tdl1 . Ts
(70)
It reveals that the desired value of ΔV presented by (69) can be achieved by selecting a proper dead-time tdl 1 and is irrelevant with load conditions. 2) Trade-Off Between ΔD1 and the Current Stress of S1 : Based on (39) and (51), Fig. 6 graphically presents the values of ΔD1 and current stress of S1 with different Llk and Cr 1 . Each pair of values of Llk and Cr 1 within the boundaries presented by (62) and (68) are reiterated by (54) and (56) and only the ones that meet the conditions are shown in Fig. 6. It should be noted that the value of Cr 2 is neglected for the sake of simplification during the checking process. Moreover, the values of the current
Fig. 7. Graphically trade-off conditions for designing of L r and C r 2 (m = 4, V C 1 , m in = 900 V, V C 1 = 1000 V, V C 1 , m a x = 1100 V, L lk = 36 μH, iL f 2 = 13.9 A, IS a 2 , m a x = 48 A, T s = 20 μS, and td l 2 = 0.278 μS). (a) ΔD2 versus L r and C r 2 . (b) Current stress of Sa 2 versus L r and C r 2 .
stress shown in Fig. 6(b) are approximated ones with Cr 2 = 0. This approximation will not affect the design of Llk and Cr 1 as Cr 2 is much smaller than Cr 1 and the selection of Cr 2 is independent of Cr 1 as shown later. It can be observed that large values of Llk and Cr 1 are beneficial to achieve the duty-cycle gain and increase its value. However, high value of Cr 1 will induce large current stress of S1 , leading to increasing conduction losses. 3) Trade-Off Between ΔD2 and the Current Stress of S2 : According to (40) and (53), Fig. 7 plots the surfaces of ΔD2 and the current stress of Sa 2 with varying values of Lr and Cr 2 . Each pair of values of Lr and Cr 2 within the boundaries presented by (63) and (66) should meet the condition in (55). It can be noted that higher value of Lr is beneficial to increase the value of ΔD2 and reduce the current stress of Sa 2 . Large value of Cr 2 is also preferable to obtain more duty-cycle gain; however, it will induce high current stress on Sa 2 . VI. PROTOTYPE AND EXPERIMENTAL VERIFICATIONS A 2-kW, 1500/48-V prototype is built to verify the proposed dc–dc conversion concept. The specifications are as shown in
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TABLE V COMPONENT SELECTIONS OF THE PROTOTYPE
Fig. 8.
Design flowchart for ΔV , L lk , L r , C r 1 , and C r 2 .
Table III. The design flowchart of ΔV , Llk , Lr , Cr 1 , and Cr 2 based on the design guideline in Section V is presented in Fig. 8. According to Table IV, the turns ratio of the isolation transformer is selected as m = 4 and the duty cycles D1 and D2 are within [0.349, 0.427] and [0.698, 0.854], respectively. Figs. 6 and 7 are plotted with the preselected switching devices which have the following parameters: IS1,m ax = 20 A, IS a 2,m ax = 48 A, tr 1 = tr 2 = 22 ns, and tf 1 = tf 2 = 29 ns. To compromise ΔD1 and current stress of S1 , maximum allowable Llk is chosen and minimum value of Cr 1 is selected. With the design specifications, Llk = 36 μH and Cr 1 = 34 nF. Lr is selected with the allowable maximum value and trade-off considerations should be made for the selection of Cr 2 . According to (66) and Fig. 7, Lr is limited within 1.93 μH. Therefore, Lr is selected with 1.6 μH to maintain a reasonable difference from that of Llk /m2 and to retain margin for tolerance considerations of practical inductors. Cr 2 is chosen to be 10 nF. Accordingly, the component parameters of the converter are presented in Table V. Llk is designed to be 36 μH. It is realized by connecting an externally added inductor of value 25 μH in series with the leakage inductance of the transformer of value 11 μH. Film capacitors instead of electrolytic capacitors are used for the dc link due to their high-voltage blocking capability. The dc-blocking capacitor Cb is also implemented by film capacitor with low equivalent series resistance to sustain high current and reduce its power losses. Fig. 9 shows the photo of the prototype (without showing the DSP control board). Fig. 10 describes the driving signals for the primary-side switches. It can be observed that different duty cycles are
Fig. 9. 2-kW 1500/48-V prototype (Dimensions: 18.5 cm × 13.3 cm × 9.2 cm).
Fig. 10.
Asymmetric driving signals for the two switch pairs.
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Fig. 11. Switching waveforms of S1 –S 4 . (a) ZCS turn ON/OFF of S1 and S2 under full load condition. (b) ZVS turn ON/OFF of S3 and S4 under full load condition. (c) ZCS turn ON/OFF of S1 and S2 under 10% load condition. (d) ZVS turn ON/OFF of S3 and S4 under 10% load condition. (e) ZCS turn ON/OFF of Sa 1 and Sa 2 under full load condition.
applied to the two switch pairs to achieve the asymmetric voltage distribution on them. The gate signals for S1 and S3 have a phase difference of around 180◦ . Fig. 11 presents the switching waveforms of the proposed converter under full load and 10% load conditions. It can be observed that the IGBT switches S1 and S2 are turned ON/OFF with ZCS and the MOSFET switches S3 and S4 are switched by ZVS. Soft switching can be achieved from very light load to nominal load conditions. Moreover, the voltage stresses on S3 and S4 are around 500 V as shown in Fig. 11(b), implying that it
achieves an asymmetric voltage distribution with k = 2, which is in well agreement with the theoretical predictions. The ZCS waveforms for the auxiliary switches Sa 1 and Sa 2 are presented in Fig. 11(e). Fig. 12 shows the voltage waveforms across the input capacitors C1 and C2 at start up. The voltage distribution ratio is found to be 1.998, which is in consistent with (45) and (46). Fig. 13 shows the relationship of open-loop voltage and output current with fixed duty cycle and input voltage. The output voltage increases with the reduction of load current due to
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Voltage across C 1 and C 2 during start-up.
Fig. 13. Open-loop voltage and current characteristics with fixed duty cycles and input voltage.
increased effective duty cycles. As the practical voltage drops on diodes, active switches and parasitic resistors have not been considered in the theoretical calculations, the calculated output voltages are observed to have some discrepancies with the simulation and experimental ones. Fig. 14 presents the measured efficiencies of the prototype. It reveals that the proposed converter exhibits high efficiency within wide load ranges as shown in Fig. 14(a). The efficiency under nominal load condition is 92.4%. The power losses in main components are analyzed in Fig. 14(b). The key loss is on the rectifier diodes. With the aid of soft switching, the power dissipated on the two switch pairs is only 0.72% of the input power. The efficiency without the ZCS snubber is also presented in Fig. 14(a), indicating an efficiency reduction of 1.7% under nominal load mainly due to the turn OFF losses of IGBTs S1 and S2 . The efficiencies with open-loop voltage varying from 48 to 52.1 V (corresponding to Fig. 13) under different load conditions are shown in Fig. 14(a). The power losses are mainly composed of two parts. The first part is almost constant, such as the core losses of isolation transformer and output inductors, power supplies for gate drivers and control circuits, and part
Fig. 14. Measured efficiencies of the experimental prototype. (a) Efficiencies under different load conditions. (b) Power losses in main components under nominal load condition (others: dc-link capacitors, dc-blocking capacitors, auxiliary power supplies for control and gate drivers, and so on).
Fig. 15.
Power losses analysis under different load conditions.
of the power losses in the ZCS snubber. The second part is increased with the output power. The efficiency drops at light load due to that the first part power losses will become dominant. Accordingly, the portion of the power loss in the main components is analyzed in Fig. 15 under heavy load, medium load, and light load conditions.
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TABLE AI VOLTAGE BETWEEN NODES “A” AND “B” AND CORRESPONDING TIME INTERVALS
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during one steady-state cycle is given by Ts vA B (t)dt VT = 0
D1 Ts − tdl1 = VC 2 tdl1 + (VC 1 + VC 2 ) 2 2C s V C 2 /i p (t 6 ) (1 − D1 )Ts ip (t6 ) + t + VC 2 VC 2 − 1 2Cs 0 −2C s V C 2 /i p (t 8 ) ip (t8 ) +0+ t dt − 2Cs 0 (1 − D2 )Ts 2Cs VC 2 − + VC 2 2 −ip (t8 ) 1 = VC 2 Ts + (D1 VC 1 − D2 VC 2 )Ts 2 2 Cs VC 2 Cs VC2 2 − + − VC 1 tdl1 . ip (t6 ) −ip (t8 ) Compared to the prototype in [15] with same specifications, the proposed one achieves 16.2% volume reduction and 1.6% and 8.2% efficiency improvement under full load and 50% load, respectively. VII. CONCLUSION A novel concept of dc–dc conversion with asymmetric voltage distribution across switch pairs is proposed and applied for a particular kind of high input voltage application. It allows using optimal choices of switching devices to achieve highfrequency and high-efficiency operations. A hybrid ZVS–ZCS soft-switching technique is developed to make the switching losses of MOSFETs and IGBTs negligible. The asymmetric operations of the MOSFET switch pair and IGBT switch pair induce a voltage difference between dc-link capacitor C2 and dc-blocking capacitor Cb . This voltage difference is independent of load conditions and is the energy source for achieving ZVS of the lagging switch in the MOSFET switch pair. The proposed snubber for ZCS of the IGBT switch pair completely releases the snubber energy to the load, resulting in a duty-cycle gain. The two switch pairs can be soft-switched from very light load to full load conditions with minimum circulating energy. The control stage is implemented with a single digital controller without additional hardware circuitry as compared to its counterpart in FB or TL converters. The switches of the snubber commutate with ZCS. The concept is verified by a 1500/48-V 2-kW prototype. Experimental results are in good agreement with the theoretical analysis. A voltage distribution factor of two is achieved and the measured efficiency at nominal load is 92.4%. APPENDIX A DERIVATION OF (34) The voltage between nodes “A” and “B” are tabulated in Table AI during the corresponding intervals. The volt-time value
(A1)
As the volt-second of the isolation transformer during one steady-state cycle is zero, the average voltage of VC b is given by D1 VC 1 − D2 VC 2 VC b = VC 2 + 2 Cs VC2 2 Cs VC2 2 VC 1 tdl1 − . + − ip (t6 )Ts −ip (t8 )Ts Ts
(A2)
APPENDIX B DERIVATION OF (37) AND (39) The overall volt-second value of the inductor Lf 1 is equal to zero in one steady-state cycle. According to Table AII, t2 VC 1 + ΔV [1 − cos ωr 1 (t − t1 )] − Vo dt m t1 t4 VC 1 + ΔV [1 + cos ωr 2 (t − t3 )] − Vo dt + m t3 t5 VC 1 + ΔV iL f 1 − + (t − t4 ) − Vo dt m Cr 1 t4 VC 1 + ΔV − Vo t2−3 − Vo t5−12 = 0. (A3) − Vo t0−1 + m Therefore, it can be obtained from (A3) that √ Vo Cr 2 (VC 1 + ΔV ) 1 Llk Cr 1 = + D1 + 2 VC 1 + ΔV 2m 2miL f 1 Ts mTs tdl1 Llk iL f 1 − − . (A4) Ts mTs (VC 1 + ΔV ) By substituting (70) into (A4), it results √ Cr 2 (VC 1 + ΔV ) 1 Llk Cr 1 Vo = + D1 + 2 VC 1 + ΔV 2m 2miL f 1 Ts mTs ΔV Llk iL f 1 − − . (A5) VC 1 mTs (VC 1 + ΔV )
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TABLE AII VOLTAGE ACROSS OUTPUT INDUCTOR L f 1 AND CORRESPONDING TIME INTERVALS
APPENDIX D TERMINOLOGIES 1) Asymmetric voltage distribution—The input voltage is distributed asymmetrically between two primary-side seriesconnected switch pairs. 2) Voltage distribution factor k—The ratio between the voltages across the two primary-side series-connected switch pairs. 3) ZVS duty-cycle loss—A reduction of the mark-space ratio of the transformer primary or secondary voltage due to the ZVS. 4) ZCS duty-cycle gain—An increase of the mark-space ratio of the transformer primary or secondary voltage due to the ZCS. 5) Output voltage ripple—The peak-to-peak value of the voltage ripple at the output of the converter. REFERENCES
TABLE AIII VOLTAGE ACROSS OUTPUT INDUCTOR L f 2 AND CORRESPONDING TIME INTERVALS
APPENDIX C DERIVATION OF (38) AND (40) The overall volt-second value of the inductor Lf 2 is equal to zero in one steady-state cycle. According to Table AIII and (26), (27), in a similar fashion as the derivations of (A4), one gets Vo VC 2 − ΔV mCs VC 2 1 4Leq (VC 1 + ΔV ) = + D2 + 2 2m iL f 2 Ts Lr /Cr 2 (VC 2 − ΔV )Ts tdl2 Llk iL f 2 m2 Leq (1 − D2 )ΔV − − − . Ts m(VC 2 − ΔV )Ts Llk (VC 2 − ΔV ) (A6)
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WANG et al.: NEW CONCEPT OF HIGH-VOLTAGE DC–DC CONVERSION
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Huai Wang (S’07) was born in China in 1985. He received the B.Eng. degree in electrical and electronic engineering from the Huazhong University of Science and Technology, Wuhan, China, in 2007. He is currently working toward the Ph.D. degree from the Department of Electronic Engineering, City University of Hong Kong, Kowloon, Hong Kong. In 2009, he was an intern student at ABB Corporate Research Center, Switzerland, for six months. During his Ph.D., he has published more than 15 papers and filed 1 international patent. His research interests include high-voltage medium-power dc–dc conversions, fast dynamic control for converters, and dc-link capacitance reduction technology. Mr. Wang is the recipient of several paper and project awards from industry, the IEEE, and the Hong Kong Institution of Engineers. He is currently the committee member of the IEEE Power Electronics Society Technical Committee on high performance emerging technologies.
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Henry Shu-Hung Chung (M’95–SM’03) received the B.Eng. and Ph.D. degrees in electrical engineering from the Hong Kong Polytechnic University, Kowloon, Hong Kong, in 1991 and 1994, respectively. Since 1995, he has been with the City University of Hong Kong (CityU), Kowloon, where he is currently a Professor in the Department of Electronic Engineering. He has authored or coauthored six research book chapters, and more than 270 technical papers including 130 refereed journal papers in his research areas. He holds 16 patents. His current research interests include timeand frequency-domain analysis of power electronic circuits, switched-capacitorbased converters, random-switching techniques, control methods, digital audio amplifiers, soft-switching converters, and electronic ballast design. Dr. Chung is the recipient of the Grand Applied Research Excellence Award from the CityU in 2001. He was the IEEE Student Branch Counselor and was the Track Chair of the technical committee on power electronics circuits and power systems of the IEEE Circuits and Systems Society during 1997–1998. He was an Associate Editor and a Guest Editor of the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—PART I: FUNDAMENTAL THEORY AND APPLICATIONS during 1999–2003. He is currently an Associate Editor of the IEEE TRANSACTIONS ON POWER ELECTRONICS and the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—PART II: EXPRESS BRIEFS.
Adrian Ioinovici (M’84–SM’85–F’04) received the bachelor degree in electrical engineering and the Dr.Eng. degree from the Polytechnical Institute of Iasi, Iasi, Romania, in 1974 and 1981, respectively. In 1982, he joined the Holon Institute of Technology, Holon, Israel, where he is currently a Professor in the Department of Electrical and Electronics Engineering. During 1990–1995, he was a Reader and then a Professor in the Department of Electrical Engineering, Hong Kong Polytechnic University, Hong Kong. He is the author of the book Computer-Aided Analysis of Active Circuits (New York: Marcel Dekker, 1990) and of the chapter “Power Electronics” in the Encyclopedia of Physical Science and Technology (New York: Academic, 2001). He has published more than 100 papers in circuit theory and power electronics. His current research interests include simulation of power electronics circuits, switched-capacitor-based converters and inverters, soft-switching dc power supplies, and three-level converters. Dr. Ioinovici has been the Chairman of the Technical Committee on Power Systems and Power Electronics of the IEEE Circuits and Systems Society. He was the Associate Editor of the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—PART I: FUNDAMENTAL THEORY AND APPLICATIONS and of the Journal of Circuits, Systems, and Computers. He has been an Overseas Advisor of the IEICE TRANSACTIONS, JAPAN. He was the Chairman of the Israeli Chapter of the IEEE Circuits and Systems Society between 1985 and 1990, and served as the General Chairman of several conferences such as the International Society for the Comparative Study of Civilizations (ISCSC) in 1986 and 1988 (Herzlya, Israel), and Southeast Private Equity Conference in 1994 (Hong Kong). He has organized and chaired special sessions in power electronics at the International Symposium on Circuits and Systems (ISCAS) 1991, ISCAS’92, ISCAS’95, ISCAS’2000, and was a member of the Technical Program Committee at the conferences ISCAS’91, ISCAS’95, ISCAS’06, Power Electronics Specialists Conference (PESC) 1992-PESC’95, the Track Chairman at ISCAS’96, ISCAS’99, ISCAS’2005, the Co-Chairman of the Special Session’s Committee at ISCAS’97, the Co-Chairman of the Tutorial Committee at ISCAS’06, and the Co-Chair of the Special Session Committee at ISCAS’10, Paris. He was a Guest Editor of special issues of the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS (August 1997 and August 2003) and a special issue on Power Electronics of Journal of Circuits, System, and Computers (August 2003).
