A New Space Vector Pulse width Modulation for Reduction of ...

IEEE - International Conference On Advances In Engineering, Science And Management (lCAESM -2012) March 30, 31,

694

A New Space Vector Pulse width Modulation for Reduction of Common Mode Voltage in Three Level Neutral Point Diode Clamped Multilevel Inverter C. Bharatirajai, S. Raghu R.Palanisami Research Scholar, SRM University, Chennai, fudia PG Scholar,SRM University 2,

I,

2,3

categories, according to their topology: Neutral point clamped Abstract- In this paper, the space vector modulation technique for an

(NPC), Flying capacitor (FLC), and Cascade H-bridge.

neutral point clamped (NPC) three-level Inverter is

described and investigation of the common mode voltage rejection also done. Based on the two level inverter, the paper further deals with space vector PWM technique for an three level inverter with

19 of 27 available voltage vectors are used in order to reduce the amplitude of CM voltage to be one sixth of the dc-link voltage by adding zero-sequence component to the fundamental component,

Among the high-power converters mentioned above, the NPC inverter introduced 25 years ago is the most widely used in all types of industrial applications, in the range of 2.3 to 4.16 kV, with some applications up to 6 kV. In the recent years MU, has acquired great industrial importance mainly due to its

thus selecting of the required voltage vector. The Simulation with

advantages, such as lower common mode voltage,

a IHP induction motor drive system is setup in Mat lab and the

voltage stress on power switches, lower dv/ dt ratio to supply

same results validated effectively by hardware -DSP 320F2812

lower

processor

drastically

and

its

shows

that

the CM

voltage is

effectively

mitigated and the maximum output voltage is not affected.

harmonic

contents

improved

in

output

dynamic

voltage

and

performance,

lower

current, extended

operating range, reduced line harmonics, and an adjustable

Index Terms- Space vector pulse width modulation (SVPWM), 3 level Diode Clamped Multilevel Inverter, NPC, Common Mode Voltage (CMV).

power factor at the point of common coupling. In the NPC the major problem is common mode voltage due to that inverters generating high frequency and high amplitude

common mod e voltages, which ind uces =shaft Voltages' on the rotor

side.

When

the

induced shaft voltage exceeds the

breakdown voltage of the lubricant in the bearings, result in I.

large bearing currents. This causes premature failure of the

INTRODUCTION

Multilevel inverters have gained much attention in the application areas of medium voltage and high power. This area of multilevel inverters came to the attention of researchers as soon as it was proposed by

Nabae A in 1981. Multilevel power

converters are being increasingly adopted for medium voltage and

high

inverter

power

applications.

topologies

synthesize

Voltage a

voltage

source

multilevel

waveform

from

several voltage levels, usually obtained from several capacitors or D.C sources. The commutation of the power switches allows the addition of voltages to these sources, which reach higher voltage at the output,

As the number of levels

increases, the output waveform approaches the reference sine­ wave more and more, thus we can get accurate result as the number of level increases.

Highly popular are the voltage­

source multilevel inverters, which can be divided into three

motor bearings and also poses EMI issues. In open end winding configuration, isolated DC links are needed to avoid heavy currents due to the common mode voltages in the phase windings. The best solution for all these is to eliminate the CMV itself. The major applications of NPC can be classified into two broad areas, they are: Large Motor Drives[l]: As the name indicates they are mainly used for high power loads e.g. pumps in the petrochemical industry, fans in cement industry, traction in transportation industry,

steel

rolling mills

in cement industry,

blowers,

compressors and conveyors, downhill conveyor system etc. Power Systems Applications: The typical applications are STATCOM,

UPFC,

power

quality,

power

conditioners,

reactive power compensator, grid connected systems etc. More recently MUs have been used for an increasingly a variety of applications which includes induction machine and

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695

employed, represented as P, 0 and N, as shown in table 3. So a 3 total of 3 = 27switching states are available. With these

motor drives, active rectifiers, filters, interface of renewable energy sources, flexible AC transmission systems (FACTS),

and static compensators. NPC MLI's are highly robust and

switching combinations, the voltage at the inverter output

highly flexible system.

terminal can be generated with three levels (E/2, 0, -E/2). Out of the 27 vectors, the 24 active vectors frame the trajectory of the hexagon and the zero vectors forms the axis of the

Although

Multilevel

proven

hexagon. Similar to the two level inverters, hexagon comprises

technology, there is still a significant amount of research work

of 6 sectors each having 4 regions each. SVPWM in three­

in the following area. New topology, new modulator methods

level inverter can easily be implemented considering the

and

flowchart as shown in figure 3.

control

conditions,

NPC

strategies, increasing

Inverter

operation of

is

already

under

efficient

and

faulty/abnormal reliability,

new Table 1: switching sequence for NPC

application.

Switching

II.

Voltage Six

states

SVPWM TECHNIQUE FOR THREE LEVEL INVERTER (NPC)

Figure 1 illustrates the main circuit for a three level inverter. The circuit includes two diodes and four power switches

S2x

p

ON

ON

0

OFF

ON

N

OFF

OFF

S3x

S4x

OFF

level

OFF

ON

E

OFF

0

ON

-E

ON

(MOSFET or !GBT) in each phase.

THE PROPOSED SIMPLIFIED SVPWM ALGORITHM

III.

From figure 2 it is evident that all the six sectors are identically the same. This paper introduces the simplified algorithm based on the concept that the similarity of all six

Vd,

sectors

results

sequence

in

the

on-time

arrangement

being

calculation the

same

and at

switching

all

sectors.

Implementation of this algorithm needs the reallocation of reference vector lying at any sector to sector 1 by rotating

through nTT/3 (n= 1, 2, 3, 4, 5, 6).

..

I

_---'f ''

S·ecto,-

',iu _�' Io:-\ -N

der'"

Referer.1c-e·vect:o:rto..cat:lo:n. ina tion

RO'Ea lting ref"erer1ce vecltor 1:0 se ctor - l

Figure I Three phase three level inverter (NPC)

� dct:cn:n mEl. bon D\N�eU rim e c.alcula rion v'" [')1-1)[;.1

Vco 11 1 -11101

S.�""i1:chi:n.g order­

dc:tcnn. mn non &. .£1.1100 C-El. rion Pulse gener,a lion

Figure 3: flowchart for 3 level SVPWM implementation 1"11 ; 111';"

Sector

- V '-111111111

1If-----"-....---'-'---ij"'----:It--"---*--.

IX

determination

is

hence

followed

by

rotation

The location of reference vector within the sector can be determined as in [1] from (1) & (2). ml= m

n

[cos e -

m2= 2m mn �

n [sin

sin

8/J2]

8/J2]

J3 ma

Figure 2 switching sequence for switches NPC, Sector-I In order to ensure complementarities between four switches

of

reference vector to sector one irrespective of sector number[2].

where =m; value between 0 to1

of each phase, there has to be three kinds of switching states

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(1 ) (2) (3)

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0-1-1

I

I

I I•

Figure 4: Triangle determinaton

I

•

•

•

•

•

•

I I

0;

If ()( is between 1800 0.5, then V is in Region 4. C.

voltage Vdc, the CMV is always different from zero and may

Calculating the switching times, To> Tb, Tc

take the values of -Vdcl6 or -V de/2, depending on the inverter

Ta, Tb, Tc switching times for Sector A is given in Table.2 Figure 4: m\ and m2 calculation from sector l. r=:; V-ref Where -rna

=

-V

3(

"I' d

Since the VSI cannot provide purely sinusoidal voltages and has discrete output voltages synthesized from the fixed dc bus

)

switch states selected. During the switch state changes, the CMV changes by -Vdcl3, regardless of the changing stat�s. The CMV transitions are shown in Table. 3. The change In

CMV from +Vde/2 to +Vde/6 constitutes step of Vde/3. When

And then, If m" m2 and (m,+m2) < 0.5, then V* is in Region 1,

the level changes from +Vde/6 to -Vde/6, the change is again

if m, > 0.5, then V* is in Region 2, If m2 > 0.5, then V* is in

Vde/3[12].

Region 3, if ml and m2< 0.5 and (m\+m2) > 0.5, then V* is in Table 3: Common mode generation according to the vectors

Region 4. Table 2: Timing calculation for the sectors

Region I Ta l.l *111*Ts *sin((1ri3)-a) Tb �J2(1-(2* 1.1 *sin( ct+m'3)) Te 1.1 i,'T/sina Region III Ta �/2(l-2* 1.1 *m* sina) Tb �/2(2 * 1.1 *111*sin(1[/3+0.)-1 )

Region II ....

Ts(1-1.1 *m*sin(ct/rJ3)) 1.1 *T5 *m*sinu. T512((2*1.1 *m*sin(1V3-a))-1)

Re�on IV T/2(2* 1.1 *m*sin(a)-I) 1.1 *m*Ts*sin((n/3)-a)

Te �/2(1+2*1.1 *m*sin( et-1[/3)) Ts(1-(1. P'm*sin(u+n/3))

Group

Switching states of 3-level inverter

CMV

A

III

Vdcl2

B

110,101,011

Vde 13

C

1-11,]]-1,-111 ,001,010,100

Vde 16

D

000,01-1,0-11,10-1,]- 10, - 101,-1 10

0

E

- 1- 11,- 11-1,1-1-1,00 1,0-10,-1 00,

-

- Vde 16

F

-] 0-1,0-1-1,0-]-1

- Vde /3

G

-1-1-]

- Vde 12

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697

Each Phase-leg has three different states (+1, 0,-1), denoting

The control concepts to divide the output voltage references

the

into two parts: the fundamental component and the zero­

phase

output

voltage

is

clamped to

positive dc-bus

(+Vdel2), dc-link neutral point (0) and negative dc bus (-Vde/2),

sequence component. Usually, the controller inner current loop

respectively.

will give the output voltage reference. Through the imaginary

Considering

three

phase-legs,

there

are

27possible combinations of switching states as shown in

coordinate (line voltage coordinate) transformation given in

Fig.2.For each voltage vector, the corresponding CM voltage

[13], the fundamental component can be subtracted, and the

is different and can be calculated by (4). For example, vector

optimized zero-sequence component is selected based on the

(1, 1,1) will generate the CM voltage Vcm=V de/2, while (1,0,0)

controller's purpose, such as balancing the d C-link

will generate Vcm=Vdel6. The CM voltages and the associated

voltage, minimizing the switching loss or reducing EM!.

voltage vectors can be summarized in Table.3. As seen, the

Afterwards, the optimized zero-sequence is added to the

mid-point

possible values of CMV voltages are(+Vdel2, -Vdel2, Vdel3,­

fundamental component to get the fmal voltage reference.

Vdel3,

+Vdel6). For the voltage vectors, 19 of the 27

Essentially, this process simplifies the selection of the adjacent

will generate CM voltages with amplitude less than or equal to

vectors around the triangle in the space vector diagram, as

Vde/6, which are selected to be used in the CM voltage

shown in Fig.6.

-Vde/6,

mitigation control. It will not affect the maximum output voltage that the converter can achieve since the maximum voltage

vectors

are

still

available.

Consequently,

V. SIMULATION RESULTS

eight

redundant voltage vectors usually used for balancing the dc­

A.

Simulation Results and Discussion

link capacitor voltage are not available because of the CM voltage constraints of the controller. To that end, two separate

The simulation system was setup in MatlabII.a. The motor is a

diode rectifiers are put in front of the inverter, clamping and

IHP induction motor with a rated voltage of 200V and current

balancing the dc-link mid-point voltage as shown in Fig.I.

of 5A. An open loop constant V/f control is used to regulate the motor speed and the dc-link voltage is set at 200V. In the

B.

Proposed Common mode voltage (CMV) Rejection -SVM

generalized SVPWM technique the common mode voltage exist due to short vectors due to that CMV exist four stages

An algorithm for injecting the optimized zero-sequence

±Vdc

I 2,±Vdc I 3,±Vdc I 6,0. In the proposed technique by

signal is derived. Also it finds out how to use the zero-

injecting the zero sequence signal is added to the fundamental

sequence voltage to achieve the =two-phase' mod e operation

component to get the fmal reference voltage the CMV has

for reducing the converter switching losses. A common mode

reduced to two stages ,±Vdc

I 6,0

The switching frequency is

voltage mitigation method is then proposed which effectively

45kHz. Simulation results are shown in Fig.7, where Fig.8 (a)

mitigates the CM voltage within 1/6 of the DC-link voltage.

shows the CM voltage without mitigation method at the motor

Moreover gives a simple method to directly map the reference

stator

voltage to the converter switches by using the concept of

corresponding CM voltage can be ±Vdc

voltage level. Zero-sequence signal injection Concept from the

,which can be possible to all dc-link voltage. Fig.8 (b) is the

voltage

frequency

of

25Hz

and

50Hz.

The

I 2,±Vdc I 3,±Vdc I 6,0

PWM

CM voltage waveform when the mitigation method is applied.

algorithm can be implemented and applied to several different

As seen, the CM voltage amplitude is effectively reduced to

proposed

method

in

[13],

a

universal

multilevel

Vd/6 at stator frequency of 25Hz. Simulation parameters are as

multilevel converter topologies.

follows:

PhmA

lW

o Phm B

1 o 1

PhmC

W

I

I I

:

I I I

o II

I I I I I I I I I

I Tl I I.-

I I I I I I I I

I

I

T

T3 T4

I I I I I I I I I I I

.,1

Ts

Figure 6: Phase voltage in one PWM switching cycle Fig 7.line to line voltage for Three level inverter

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698

GA.T OCT 22 15 5Q.00:!011

Fig I O.line to line voltage for Three level inverter-NPC Inveter

Fig 8 (a).Convertional PWM Common mode voltage of three level ";e:!:,

inverter (VdJ3 = 33% Vdc )

Ava ... T�i.� o

SATOCT?21�.lG2.t20"

Fig 8 (b). Proposed SVM Common mode voltage of three level inverter Fig I I . Proposed SVM Common mode voltage of three level inverter

( VdJ6 = 19 % Vdc) B.

( VdJ6 = 19 % Vdc)

Hardware Results and Discussion

A 1kW experimental system is also built to validate the proposed CM voltage mitigation method as shown in Fig.6, which consists of switching modules, a control board, a sensor board

and

R-L

load.

The

control

board

is

based

on

theTMS320F2812 DSP. The dc-link voltage is set to 300 V and the switching frequency is 4 kHz. The load is 3-phase 1HP Induction motor The experimental results are shown in Fig. 8, where Fig.8 (a) shows the CM voltage waveform without applying the mitigation control, CM voltage with amplitude of Vdcl3,

Vdc/6

appear.

Fig.8

(b)

illustrate

that the Voltage

amplitude is effectively controlled to be within Vdcl6 after the mitigation

method

is

experimental results of

utilized. both

the

The

depicts

the

simulation models.

figure

The

Fig 12 .Hardware Setup - Three level inverter-NPC Inveter

experimental results validate the improved performance of the

VII. CONCLUSIONS

multi-level inverter over an ordinary two level inverter in This

terms of output voltage level and THD%. �AT(')r:T""lrir,'?'(lA ?fill

paper

presented

a

CM

voltage

mitigation

method

associated with three-level NPC voltage source converters. Voltage vectors are selected in order to reduce the CM voltage down to Vdc/6, which is achieved by adding a constraint to the Simplified Space Vector PWM controller. The relationship between CM voltage and the sum of the three phase output

voltage level is derived and summarized. The zero-sequence component is chosen based on the constraint and added to the fundamental component, which enables the CM voltage to be no larger than Vdc/6 while still keeping the maximum output voltage value. Simulation with a IHP induction motor drive system is setup in Mat lab and the same results validated effectively by hardware -DSP 320F2812 processor.

Fig 9 .Iine to line voltage for Three level inverter-NPC Inveter

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Wired Neutral Point Clamped Converters II , iEEE 36th Power Electronics

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Research Scholar, SRM University, Chennai C.BHARATIRAJAi He

was born in Namakkal, Tamil Nadu, INDIA in 1980. He obtained the B.E Degree in EEE from Kumar guru College Of Technology,( KCT) Coimbatore, Tamil Nadu, India in 2002 and the M.E degree In power electronics and Drives from Government College of Technology ( Anna University Coimbatore (GCT)), Tamilnadu in 2006. In 2002 -2004 He worked in TESCOM Electronics, Bangalore, India Presently he is Assistant Professor in the Department of Electrical Engineering, SRM University, Kattankulathur, Chennai, India. He is presently pursuing Doctoral degree from SRM University, Tamil Nadu, India He presented many research papers in various national and international conferences and journals. His research interests include Power Electronics Drives and Multilevel inverters, SVPWM Techniques. [email protected].

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He was born in Karuppampalayam, Karur, Tamil Nadu, India in 1990. He obtained the B.E Degree in EEE from M.Kumarasamy engineering college (Anna University Coimbatore), Karur, Tamil Nadu, India in 2011. He is presently pursing M.Tech degree in power electronics and drives from SRM University, Kattankulathur, Chennai, Tamil Nadu, India. His research interests include Power Electronics Drives and Multilevel inverters,Various PWM Techniques. [email protected]

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