A Notebook on Electronic Circuits II

A Notebook on Electronic Circuits II Prepared By Er. Shree Krishna Khadka teaching.official @gmail.com

Inside 1. 2. 3. 4. 5. 6. 7.

Differential Amplifiers Instrumentation and Isolation Amplifiers Logarithmic Amplifiers Introduction to Communication Circuits Data Conversions Switched Power Supply Circuits Power Conversion Circuits

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Electronic Circuits II

WHCSE BLEX V

Differential Amplifier Contents: o o o o o

Differential Amplifier: Introduction Basic Operation Transistor Gain Non Ideal Characteristics Advantages & Application

1 Prepared By: SriKisna Khadka BLEX 2006 Batch: WHCSE

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Differential Amplifier Introduction Differential Amplifier is a fundamental component of every op-amp. It has two separate inputs and two separate outputs. It consists of two transistors with emitter connected together, which amplifies the difference of signals applied between two input terminals. The basic circuit representation and symbolic diagram of Differential Amplifier is shown below. Q1 and Q2 transistors are said to be perfectly matched having identical values of β, re etc; so called Ideal Differential Amplifier (IDA). +Vcc

Rc

Rc VO1

Vi1

VO2

Q1

Q2

Vi1

VO1

Vi2

VO2

Vi2

i

-VEE Fig 1: Basic Circuit Diagram of Differential Amplifier

Fig 2: Symbolic Diagram of Differential Amplifier

Basic Features

The main feature of the differential amplifier is the very large gain when opposite signals are applied to the inputs as compared to the very small gain resulting from common inputs. The ration of this difference gain to the common mode gain is called common mode rejection ratio. Basic Operations o Single Ended Operation: Input signal applied to one terminal and other input terminal connected to ground. In this case a single input signal is applied. However, due to the common-emitter connection, the input signal operates both transistors resulting in output from both collectors. o Double Ended Operation: If two opposite polarity input signals are applied. Hence, output from both collectors result due to the difference of both inputs. o Common Mode Operation: If same input is applied to both inputs which results in opposite signal at each collector, these signals cancel out each other so that the resulting output signal is zero. In practical matter, the opposite signals do not completely cancel and a small signal results. 2 Prepared By: SriKisna Khadka BLEX 2006 Batch: WHCSE

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Single Ended Operation

A signal applied to one input terminal of a Differential Amplifier induces a voltage with respect to ground on the amplifier’s other output terminal.

+Vcc

Vi1

Rc

Rc

VO1

VO2 Q2

Q1

Vi1 Vi2=0

Vbe2

i Ve1

VO2

Vi2

Vbe1 = Vbe2 Vbe1

VO1

-VEE

Fig : Single Ended Operation of IDA

 Q1 is common emitter amplifier so, Vo1 is an amplified and inverted version of Vi1.  Ve1 is in-phase with, and one half the magnitude of Vi1. So it is clear that Ve1 is the emitter to ground voltage of both transistors. When Ve1 goes positive, Vbe2 = -Ve1.  Even though the base of Q2 is grounded, there exists an ac base to emitter voltage on Q2 that is out of phase with Ve1 and therefore out of phase with Vi1. Consequently, there is an ac output voltage Vo2 produced at the collector of Q2 and it is out of phase with Vo1. In many applications, the output of a differential amplifier is taken from just one of the transistor collectors (e.g. from VO1). In this case, the input is a difference voltage and the output is a voltage with respect to ground. This use of amplifier is called Single Ended Output Operation.

The Voltage Gain in this mode is:

Single Ended Output (𝐀 𝐕 ) =

𝐕𝐎𝟏 𝐕𝐢𝟏 −𝐕𝐢𝟐

=

𝐕𝐎𝟐 𝐕𝐢𝟏 −𝐕𝐢𝟐


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Example

If

Vi1 Av Vi2 Then, Vbe1 & Vbe2

= = = = =

100 mV (Peak-Peak Sine Wave) -100 (For Both Q1 & Q2) 0V 50 mV -50 mV

= = = = = =

Vb1 - Ve1 Vi1 - Ve1 50 mV AvVbe1 -100×50 -5 V (Peak)

Now, For Q1: Vbe1 



Vo1

Again, For Q2: Vbe2





Vo2

= = = = = = =

Vb2 - Ve2 Vi2 - Ve2 0-50 -50 mV AvVbe2 (-100)×(-50) 5 V (Peak)

= =

100 mV (P-P), and 10 V (P-P)

Here, Vi1 – Vi2 Vo1 – Vo2

Since, Vo1 and Vo2 are out of phase, the magnitude of the difference voltage gain (Vo1Vo2)/(Vi1-Vi2) is 100. While the voltage gain Vo/Vi for each side is only 50. Therefore the difference voltage gain is the same as the gain Vc/Vbe of each transistor.

Double Ended Operation

While applying the two inputs with equal but out of phase signals, the outputs obtained are as shown in the figure. By Superposition, each output is the sum of voltages resulting from each input acting alone. So, the outputs are exactly twice the level they would be if only one input signal were present.


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+Vcc

Vi1

Rc

Rc

VO1

VO2

Vi2

Ve1

Vi2

VO2

Vi1

VO1

Vi2

VO2

=

Vbe2

i

VO1

+

Vbe1 = Vbe2 Vbe1

Vi1

-VEE

Vi1

VO1

Vi2

VO2

Fig : Double Ended Operation of IDA

Fig2 : Superposition Principle

The Voltage gain in double ended operation mode of differential amplifier is given by: Double Ended Output Gain (𝐀 𝐕 ) =

𝐕𝐎𝟏 −𝐕𝐎𝟐 𝐕𝐢𝟏 −𝐕𝐢𝟐

Example

The magnitude of the voltage gain Vc/Vbe for each transistor is 10. If Vi1 and Vi2 are out of phase, 100 mV peak signals applied simultaneously to the inputs, find: (a) The peak values of VO1 and VO2. (b) Double ended voltage gain. (c) Single ended voltage gain. Solution: (a) 𝐕𝐎𝟏 (Peak) = 10 V (b) Since, 𝐕𝐢𝟏 = −𝐕𝐢𝟐 then, 𝐕𝐢𝟏 − 𝐕𝐢𝟐 = 200 mV And, 𝑽𝐎𝟏 = −𝐕𝐎𝟐  𝐕𝐎𝟏 − 𝐕𝐎𝟐 = 20 V Now, Double Ended Voltage Gain (𝐀 𝐕 ) =


(c) Again, Single Ended Voltage Gain (𝐀 𝐕 ) =

=

𝟐𝟎𝐕 𝟐𝟎𝟎𝐦𝐕


=

= 100

10V 200mV

= 50

Note: o Double ended output is the same as Vc/Vbe for each transistor. o Single ended output is one half the double ended gain. o Since, VO1-VO2 is out of phase with Vi1-Vi2, the correct specification for double ended voltage gain is 100. 5 Prepared By: SriKisna Khadka BLEX 2006 Batch: WHCSE

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Common Mode Operation

A Differential Amplifier is able to reject common signals. Since, outputs are amplified versions of the difference between the inputs, the outputs are zero for common mode operation. Any dc or ac voltage that appears simultaneously in both signal inputs is called common mode signal. The ability of an amplifier to suppress common mode signals is called common mode rejection (e.g. Electrical Noise). But in practice, there exists a very minimum output signal.

+Vcc

Rc

Rc VO2

VO1 Q1

Vi1

VO1

Vi2

VO2

Q2

VCM

VCM

i -VEE Fig : Common Mode Operation of IDA

Hence, Common Mode Gain (𝐀 𝐜𝐦 ) =

(𝐕𝐨𝟏 −𝐕𝐨𝟐 )𝐜𝐦 𝐕𝐜𝐦

Common Mode Rejection Ratio (CMRR) CMRR is defined as:

𝐂𝐌𝐑𝐑 = |

𝐃𝐢𝐟𝐟𝐞𝐫𝐞𝐧𝐭𝐢𝐚𝐥 𝐌𝐨𝐝𝐞 𝐆𝐚𝐢𝐧(𝐀𝐝 ) | 𝐂𝐨𝐦𝐦𝐨𝐧 𝐌𝐨𝐝𝐞 𝐆𝐚𝐢𝐧(𝐀𝐜𝐦 )

The value of CMRR is very large. So, usually we express CMRR in terms of dB.

𝐂𝐌𝐑𝐑 𝐝𝐁 = 𝟐𝟎𝐥𝐨𝐠 𝟏𝟎 |

𝐀𝐝 𝐀𝐜𝐦

|


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Example Q.1) When the inputs to a certain differential amplifier are Vi1 = 0.1sint and Vi2 = -0.1sint, it is found that the outputs are Vo1 = -5sint and Vo2 = 5 sint. When both inputs are 2sint, the outputs are Vo1 = -0.05sint and Vo2 = 0.05sint. Find CMRR in dB. Solution: Here, We use peak values. 𝐕𝐎𝟏 −𝐕𝐎𝟐

 Difference Mode Gain (𝐀 𝐝 ) =

=

𝐕𝐢𝟏 −𝐕𝐢𝟐

−𝟓−𝟓

(𝐕𝐨𝟏 −𝐕𝐨𝟐 )𝐜𝐦

& Common Mode Gain (𝐀 𝐜𝐦 ) =

=

𝟎.𝟏−(−𝟎.𝟏)

𝐕𝐜𝐦

=

−𝟏𝟎 𝟎.𝟐

−𝟎.𝟎𝟓−𝟎.𝟎𝟓 𝟐

= −50

=

−𝟎.𝟏 𝟐

= −0.05

Finally, 𝐂𝐌𝐑𝐑 = |

𝐃𝐢𝐟𝐟𝐞𝐫𝐞𝐧𝐭𝐢𝐚𝐥 𝐌𝐨𝐝𝐞 𝐆𝐚𝐢𝐧(𝐀𝐝 ) | 𝐂𝐨𝐦𝐦𝐨𝐧 𝐌𝐨𝐝𝐞 𝐆𝐚𝐢𝐧(𝐀𝐜𝐦 ) 𝐂𝐌𝐑𝐑 𝐝𝐁 = 𝟐𝟎𝐥𝐨𝐠 𝟏𝟎 |

𝐂𝐌𝐑𝐑 𝐝𝐁 = 𝟐𝟎𝐥𝐨𝐠 𝟏𝟎 |

𝐀𝐝 𝐀𝐜𝐦

|

−𝟓𝟎 | = 𝟔𝟎dB −𝟎. 𝟎𝟓

Q.2) The magnitude of the voltage gain Vc/Vbe for each transistor is 100. If Vi1 and Vi2 are out of phase, 100 mV-peak signals applied simultaneously to the inputs, find: (a) The peak values of Vo1 and Vo2. (b) The magnitude of the double ended voltage gain and (c) The magnitude of the single ended output gain.

Solution: Vo1 = 50×100 + 50×100 = 10 V(Peak), and Vo2 = 10 V(Peak) Vi1 = -Vi2 Vi1-Vi2 = 2×100 = 200 mV Vo1 = -Vo2 Vo1-Vo2 = 2×10 = 20 V Single Ended Output Gain(𝐀 𝐒 ) =


Double Ended Output Gain (𝐀 𝐝 ) =

=


𝟏𝟎𝐕 𝟐𝟎𝟎𝐦𝐕

=

= 𝟓𝟎

20V 200mV

= 𝟏𝟎𝟎


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WHCSE BLEX V

Transistor Gain Since, the differential amplifier consists of two identical transistors (Perfectly Matched in Ideal Case), the gain of which can be calculated with consideration of an emitter resistance when looking from emitter to base of a transistor. This phenomena can be analyzed with π-model as shown below.

ib

Rc VO

Vbe

VO bre

Rc

bib

re Vbe Fig: Transistor Gain of DA & p-Model of Transistor

Transistor Gain (GT) =

𝐕𝐎 𝐕𝐛𝐞

=

−𝐢𝐜 𝐑 𝐜 𝐢𝐛 𝛃𝐫𝐞

−𝐢𝐛 𝛃𝐑 𝐜

=

𝐢𝐛 𝛃𝐫𝐞

=−

𝐑𝐜 𝐫𝐞

As we have: Single Ended Output Gain (𝐀 𝐒 ) = =


=

𝐕𝐎𝟏 𝐕𝐛𝐞𝟏 −𝐕𝐛𝐞𝟐

=

𝐕𝐎𝟏 𝟐𝐕𝐛𝐞𝟏

𝟏 × Transistor Gain(GT ) 𝟐

Double Ended Output Gain (𝐀 𝐝 ) =


=


−

𝐕𝐎𝟐 𝐕𝐢𝟏 −𝐕𝐢𝟐

=

𝟐𝐕𝐎𝟏 𝟐𝐕𝐛𝐞𝟏

= Transistor Gain(GT ) Hence, from above calculation it is known that the double ended output gain is exactly equal to the transistor gain whereas the single ended output gain is one half the gain of transistor.


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Non Ideal Characteristics 1. Input Offset Voltage

Mismatch between the tow sides of a differential pair result in a differential dc voltage Vo even when the two input terminals are tied together and connected to a common dc voltage Vcm. This signifies the presence of an input offset voltage Vos, which is given by:

VOS =

𝐃𝐢𝐟𝐟𝐞𝐫𝐞𝐧𝐭𝐢𝐚𝐥 𝐎𝐮𝐭𝐩𝐮𝐭 𝐕𝐨𝐥𝐭𝐚𝐠𝐞 (𝐕𝐨 ) 𝐃𝐢𝐟𝐟𝐞𝐫𝐞𝐧𝐭𝐢𝐚𝐥 𝐎𝐮𝐭𝐩𝐮𝐭 𝐆𝐚𝐢𝐧 (𝐀𝐝 )

The output offset in Bipolar Differential Pair results from mismatches in the load resistances Rc1, Rc2 and from junction area-β and other mismatches in Q1 and Q2. 2. Input Bias & Offset Current

In perfectly identical differential pair, the two input terminals carry equal dc current i.e. IB1 = IB2. This is the input bias current. But the mismatches in the amplifier circuit and mostly a mismatch in β make two input dc bias current unequal. Hence the resulting difference is the input offset current IOS and is given by: 𝐈𝐎𝐒 = |𝐈𝐁𝟏 − I𝐁𝟐 |

3. Input Common Mode Range

It is the range of common input voltage VCM over which the differential pair behaves as a linear amplifier for differential input signals. The upper limit of the common mode range is determined by Q1 and Q2 leaving the active mode and entering to the saturation mode of operation of BJT. The lower limit is determined by the transistor that supplies the biasing current I leaving its active region of operation and thus no longer functioning as a constant current source.


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Advantages & Applications Differential amplifier configuration is the most widely used in analog integrated circuit design as an input stage of op amp. They are also well suited for IC fabrication as they have the following characteristics:

o The performance of differential pair depends critically on the matching between the two sides of the circuit. IC fabrication is capable of providing matched devices whose parameters track over wide range of changes in environmental conditions. o Differential amplifiers utilize more components than single ended circuit that contribute IC technology for the availability of large numbers of transistors at relatively low cost. o Differential circuits are much less sensitive to noise and interference than single ended circuits. o Differential configuration enables us to bias the amplifier and to couple amplifier stages together without the need of bypass and coupling capacitors and this property can be utilize in the design of discrete circuit amplifiers.

Differential amplifiers are the basic component of all electronic voltmeters. Differential amplifiers with FETs are used to isolate the low resistance voltmeters from the circuit under test, thereby avoiding errors on account of loading effects. Hence, we see that the differential pair certainly responds to large difference mode signals. In fact, with relatively small difference voltages we are able to steer the entire bias current from one side of the pair to the other. This current-steering property of the differential pair allows it to be used in logic circuits. The differential pair implements the single pole double throw switch that we employed in the realization of the current mode inverter. Emitter Coupled Logic (ECL) is the fastest logic circuit family. High speed is achieved by operating all transistors out of saturation, thus avoiding storage time delays and by keeping the logic signal swings relatively small (about 0.8V or less), thus reducing the time required to charge and discharge the various load and parasitic capacitances. Saturation in ECL is avoided by using BJT differential pair as a current switch.


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Instrumentation & Isolation Amplifier Contents: o o o o

Instrumentation Amplifier: Introduction Characteristics & Types of Instrumentation Amplifier Isolation Amplifier: Introduction Application & Types of Isolation Amplifier


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Instrumentation Amplifier Introduction An Instrumentation Amplifier (IA) is a dedicated differential amplifier with extremely high input impedance (avoids loading effects of transducers), high CMRR (which makes this amplifier very useful in recovering small signals buried in large common mode offsets and noise signals) and precise gain setting by single internal or external resistor. Instrumentation amplifiers are generally required in any measurement system (that uses electrical transducers) to enhance the signal level which is often of low strength so that it can be used for further processing. Instrumentation Amplifier (IA) is a closed loop device with carefully set gain. The opamp itself is an open loop device with some very large (but variable) gain. This allows the instrumentation amplifier to be optimize for its role as signal conditioner of low level (often dc) signals in large amounts of noise. The op-amp in contrast, can be used to build a wide variety of circuits but does not make as good as a difference amplifier as does an Instrumentation Amplifier. Instrumentation Amplifier consists of two stages. The first stage offers very high input impedance to both input signals and allows to set the gain with a single resistor. The second stage is a differential amplifier with the output, negative feedback and ground connections all brought out.

Characteristics (Ideal Vs Practical Characteristics of Instrumentation Amplifier) Ideal Characteristics Infinite input impedance. Zero output impedance. Infinite CMRR. A constant gain factor with no gain error. Zero amplifier noise or gain. Zero dc offset.

SN

1 2 3 4 5 6

Practical Characteristics Extremely high input impedance. Low output impedance. High CMRR. High gain accuracy. High gain stability with low temp. co-eff. Low dc offset.

Types of Instrumentation Amplifier The low-input resistance problem of the difference amplifier can be solved by buffering the tow input terminals using voltage followers i.e. a voltage follower is connected between each input terminal and the corresponding input terminals of the difference amplifier resulting a superior circuit known as Instrumentation Amplifier. There are basically three types of Instrumentation Amplifier according to the number of op-amp used. They are: o o o

Single Op-amp Instrumentation Amplifier Two Op-amp Instrumentation Amplifier, and Three Op-amp Instrumentation Amplifier


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Single Op-Amp Instrumentation Amplifier The presence of common mode signal or voltage VCM and differential voltage V1-V2 are characteristics of most transducers. The common mode voltage VCM may be a noise pick up. R2 I2 R1

-

I1

V1

VO +

V2 VCM

R3

R4

Fig: Single Op-amp Instrumentation Amplifier With Zero Source Impedance

From above figure:

𝐕+ = ( Also, or,

𝐕𝟐 +𝐕𝐂𝐌 𝐑 𝟑 +𝐑 𝟒

)𝐑 𝟒

……. (1)

𝐈𝟏 = 𝐈𝟐 𝐕𝟏 +𝐕𝐂𝐌 −𝐕 + 𝐑𝟏

= 𝐑𝟐

or,

𝐕𝐎 = 𝐕 + −

or,

𝐕𝐎 = 𝐕 + (𝟏 +

𝐑𝟏

𝐕 + − 𝐕𝐎 𝐑𝟐

(𝐕𝟏 + 𝐕𝐂𝐌 − 𝐕 + ) 𝐑𝟐 𝐑𝟏

𝐑𝟐

)−

𝐑𝟏

(𝐕𝟏 + 𝐕𝐂𝐌 )

Substituting the value of V+, we get: 𝐑𝟒

𝐕𝐎 = (𝐕𝟐 + 𝐕𝐂𝐌 )(

𝐑 𝟑 +𝐑 𝟒

𝐕𝐎 = (𝐕𝟐 + 𝐕𝐂𝐌 )[

𝐑 𝟏 𝐑 𝟒 +𝐑 𝟐 𝐑 𝟒 𝐑 𝟏 (𝐑 𝟑 +𝐑 𝟒 )

𝐑 𝟏 𝐑 𝟒 +𝐑 𝟐 𝐑 𝟒

𝐕𝐎 = 𝐕𝐂𝐌 [

)(𝟏 +

𝐑 𝟏 (𝐑 𝟑 +𝐑 𝟒 )

−

𝐑𝟐 𝐑𝟏

𝐑𝟐 𝐑𝟏

]−

)−

𝐑𝟐 𝐑𝟏

𝐑𝟐 𝐑𝟏

(𝐕𝟏 + 𝐕𝐂𝐌 )

(𝐕𝟏 + 𝐕𝐂𝐌 )

𝐑 𝟏 𝐑 𝟒 +𝐑 𝟐 𝐑 𝟒

] + 𝐕𝟐 [

𝐑 𝟏 (𝐑 𝟑 +𝐑 𝟒 )

]−

𝐑𝟐 𝐑𝟏

𝐕𝟏


…




𝐑 𝟏 𝐑 𝟒 +𝐑 𝟐 𝐑 𝟒 −𝐑 𝟐 𝐑 𝟑 −𝐑 𝟐 𝐑 𝟒


𝐑 𝟏 (𝐑 𝟑 +𝐑 𝟒 ) 𝐑 𝟏 𝐑 𝟒 −𝐑 𝟐 𝐑 𝟑


𝐑 𝟏 (𝐑 𝟑 +𝐑 𝟒 )

] + 𝐕𝟐

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𝐑 𝟏 𝐑 𝟒 (𝟏+𝐑 𝟐 /𝐑 𝟏 )

] + 𝐕𝟐 [

𝐑 𝟏 (𝐑 𝟑 +𝐑 𝟒 )

𝐑 𝟒 (𝟏+𝐑 𝟐 /𝐑 𝟏 )

𝐑𝟐

𝐑 𝟑 (𝟏+𝐑 𝟒 /𝐑 𝟑 )

𝐑𝟏

[

]−

]−

𝐑𝟐 𝐑𝟏

𝐕𝟏

𝐕𝟏 ….. (2)

Since, Instrumentation Amplifier should reject common mode signal completely, VO should be made independent of VCM i.e. no term with VCM should come in the expression of VO, this requires, 𝐑𝟏𝐑𝟒 = 𝐑𝟐𝐑𝟑 or,

𝐑𝟐

=

𝐑𝟏

𝐑𝟒 𝐑𝟑

Hence, equation…(2) becomes,

𝐕𝐎 = 

𝐕𝐎 =

𝐑𝟒 𝐑𝟑 𝐑𝟐 𝐑𝟏

𝐕𝟐 −

𝐑𝟐 𝐑𝟏

𝐕𝟏

(𝐕𝟐 − 𝐕𝟏 )

So, in order to ensure the rejection of common mode signal, the resistor ratio must be carefully matched.

𝐑𝟐 𝐑𝟏

and

𝐑𝟒 𝐑𝟑

The value of this resistor ratio also sets the gain for differential signals of Instrumentation Amplifier i.e. for zero source impedance, the gain is solely determined by the feedback resistors. R2

R1

-

I

V1

VO +

V2 R3

ZIN

R4

Fig: Input Impedance of Single Op-amp Instrumentation Amplifier With Zero Source Impedance

In above figure:

𝐑𝟐 𝐑𝟏

=

𝐑𝟒 𝐑𝟑


…




Assuming, R2 = R4 and R1 = R3, The input differential impedance is: Applying loop equation:

𝐙𝐈𝐍 =

𝐕𝟐 −𝐕𝟏 𝐈

𝐕𝟐 − 𝐕𝟏 − 𝐈𝐑 𝟏 − 𝐈𝐑 𝟑 = 𝟎 𝐕𝟐 − 𝐕𝟏 − 𝐈𝐑 𝟏 − 𝐈𝐑 𝟏 = 𝟎

or, or,

𝐕𝟐 −𝐕𝟏

or,

𝐙𝐈𝐍 = 𝟐𝐑𝟏

𝐈

WHCSE BLEX V

(R1 = R3)

= 𝟐𝐑 𝟏

So, the single op-amp instrumentation has input impedance of 𝟐𝐑 𝟏 , which is not high

enough.

Limitation of Single Op-amp Instrumentation Amplifier 1. It is difficult to chance the gain because it should maintain the ratio that a common mode signal gets rejected completely.

𝐑𝟐 𝐑𝟏

=

𝐑𝟒 𝐑𝟑

. So

2. When instrumentation amplifier is required to have large differential gain, R1 should relatively be small which means its input impedance decreases and results in source loading.

R2 I2 RS1

R1

-

I1

V1

VO +

V2 RS2

VCM

V+

R3

R4

Fig: Single Op-amp Instrumentation Amplifier With Source Impedance

From Figure,

𝐕+

=(

𝐕𝟐 +𝐕𝐂𝐌 𝐑 𝐒𝟐 +𝐑 𝟑 +𝐑 𝟒

)𝐑 𝟒

……. (1)

If RS1 = RS2, Balance Condition If RS1 ≠ RS2, Unbalanced Condition


…




Also,

WHCSE BLEX V

𝐈𝟏 = 𝐈𝟐 𝐕𝟏 +𝐕𝐂𝐌 −𝐕 +

or,

𝐑𝟏

=

𝐕 + − 𝐕𝐎 𝐑𝟐

If the source impedance are not zero but equal i.e. RS1 = RS2, the only effect is gain error because the ration remains still the same. i.e. And,

𝐑𝟐 𝐑 𝟏 +𝐑 𝐒𝟏

=

VO =

𝐑𝟒 𝐑 𝟑 +𝐑 𝐒𝟐 𝐑𝟐 𝐑 𝟏 +𝐑 𝐒𝟏

(𝐕𝟐 − 𝐕𝟏 )

However, if the source impedances are unequal, the common mode rejection is degraded and there is error. Two Op-Amp Instrumentation Amplifier Assuming ideal op-amp, the virtual short circuit at the inputs of op-amps cause the input voltage to appear at the two terminals of resistor R2. Thus the differential input voltage V1-V2 appears across R2 and results a current I = (V1-V2)/R2 to flow through R2 and hence through two other resistors R1 as well. V1

+

VO1

1 I

R1

I

R2

I

R1

VO

2 V2

+

VO2

Fig: Two Op-amp Instrumentation Amplifier

This current in turn produces a voltage difference between the output terminal of the op-amps. The output of op-amp 1 is: 𝐕𝟏 −𝐕𝟐

𝐕𝐎𝟏 = 𝐕𝟏 + 𝐈𝐑 𝟏 = 𝐕𝟏 + (

𝐑𝟐

)𝐑 𝟏


…




WHCSE BLEX V

And the output of op-amp 2 is: 𝐕𝟏 −𝐕𝟐

𝐕𝐎𝟐 = 𝐕𝟐 − 𝐈𝐑 𝟏 = 𝐕𝟐 − ( 𝐕𝟏 −𝐕𝟐

Therefore, Now,

𝐕𝐎𝟏 − 𝐕𝐎𝟐 = 𝐕𝟏 − 𝐕𝟐 + 𝟐(

𝐑𝟐

𝐕𝐎 = 𝐕𝐎𝟏 − 𝐕𝐎𝟐 = (𝐕𝟏 − 𝐕𝟐 )(𝟏 +

)𝐑 𝟏

)𝐑 𝟏

𝟐𝐑 𝟏 𝐑𝟐

𝐑𝟐

)

Since, V1-V2 is the difference voltage, (1+2R1/R2) is the gain. If, R1 = R, R2 = aR then, Gain = 1 + 2/a Other Configurations of Two Op-amp IA R1

R2 = R1 R1

-

V1

R1 1

+

-V1

Voltage Follower

R2

2 +

VO


 In this configuration both op-amps are operating in an inverting mode of operation. Hence, the output can be determined as:

𝐕𝐎 = {−

𝐑𝟐 𝐑𝟐 𝐑𝟐 𝐕𝟐 } + {− (−𝐕𝟏 )} = − (𝐕 −𝐕 ) 𝐑𝟏 𝐑𝟏 𝐑𝟏 𝟐 𝟏

Thus we can change the value of R2 for varying the gain without affecting CMRR. However, we need four closely matched resistors of value R1 to ensure good CMRR.


…




WHCSE BLEX V

R4

R2 R1

-

R3 1

V1

-

VO1 = (1+R2/R1)V1

+

2

V2

VO

+


 This configuration shows a very high input impedance as given by: 𝐕𝐎 = 𝐕𝟐 (𝟏 + If

𝐑𝟐 𝐑𝟏

=

𝐑𝟒 𝐑𝟑

𝐑𝟒 𝐑𝟒 𝐑𝟐 )− (𝟏 + )𝐕𝟏 𝐑𝟑 𝐑𝟑 𝐑𝟏

𝐑

𝐑

, then 𝐕𝐎 = (𝟏 + 𝐑𝟐)(𝐕𝟐 − 𝐑𝟐 𝐕𝟏 ) 𝟏

𝟏

Therefore, this circuit provides high input impedance however, still there is difficulty in 𝐑 𝐑 varying the gain because we have to maintain the resistor ratio 𝟐 = 𝟒. 𝐑𝟏

𝐑𝟑

Three Op-Amp Instrumentation Amplifier It consists of two stages. The first stage also called input stage, consists of two carefully matched op-amps A1 and A2 and the associated resistors. Each input voltages V1 and V2 are applied to the non-inverting input terminals of its op-amp. The op-amps A1 and A2 are configured as voltage followers therefore, the first stage offers very high input impedance to both input signals. V1

+ A1 -

VO1

R3

R4

I1

I1

R1 I

R2

A3 +

VO

R1 R3

V2

A2 +

VO2

R4 +

V

Fig: Three Op-Amp Instrumentation Amplifier


…




WHCSE BLEX V

The second stage is a differential amplifier with negative feedback and output terminal brought out. We can set the gain of this stage to unity by choosing the value of R3 and R4 equal. The two resistors R1 of first stage are internal to the integrated circuit while R2 being the gain setting resistor that can be externally connected. The differential input voltage (V1-V2) appears across R2 and results a current I = (V1V2)/R2 to flow through R2 and hence through R1 as well. This current in turn produces a voltage difference between the output terminal of the op-amps A1 and A2. From above figure: 𝐕𝐎𝟏 = 𝐕𝟏 + 𝐈𝐑 𝟏 = 𝐕𝟏 + ( 𝐕𝐎𝟐 = 𝐕𝟐 + 𝐈𝐑 𝟏 = 𝐕𝟐 − (

𝐕𝟏 −𝐕𝟐 𝐑𝟐 𝐕𝟏 −𝐕𝟐 𝐑𝟐

𝐕𝐎𝟏 − 𝐕𝐎𝟐 = (𝐕𝟏 − 𝐕𝟐 )(𝟏 + 𝟐

)𝐑 𝟏 )𝐑 𝟏 𝐑𝟏 𝐑𝟐

)

Here, 𝐕𝟏 − 𝐕𝟐 is the difference voltage and (𝟏 + 𝟐 stage. To find VO, we have to calculate V+ as: 𝐕+ = Also,

𝐕𝐎𝟏 −𝐕 + 𝐑𝟑

=

𝐑𝟐

) is the gain provided by the first

𝐕𝐎𝟐 ………(i)

𝐕 + −𝐕𝐎 𝐑𝟒 𝐑𝟒

𝐕𝐎 = 𝐕 + (𝟏 +

or,

𝐑𝟒 𝐑 𝟑 +𝐑 𝟒

𝐑𝟏

𝐑𝟑

)−

𝐑𝟒 𝐑𝟑

𝐕𝐎𝟏

Substituting the value of V+, we get: 

𝐕𝐎 =

𝐑𝟒

=

𝐑 𝟑 +𝐑 𝟒

= =

Here,

𝐑𝟒

𝐑𝟑

𝐑𝟑

𝐑𝟑

=

𝐑𝟒

𝐑𝟒

𝐕𝐎

𝐕𝐎

𝐑𝟒 𝐑 𝟑 +𝐑 𝟒

𝐕𝐎𝟐 (𝟏 +

𝐑𝟑

𝐑 𝟑 +𝐑 𝟒

𝐕𝐎𝟐 (

𝐕𝐎𝟐 −

𝐑𝟒

𝐑𝟑

𝐑𝟒 𝐑𝟑

)−

)−

𝐑𝟒 𝐑𝟑

𝐑𝟒 𝐑𝟑

𝐕𝐎𝟏

𝐕𝐎𝟏

𝐕𝐎𝟏

(𝐕𝐎𝟐 − 𝐕𝐎𝟏 ) ….(2)

is the gain of second stage. Substitution the values of VO1 and VO2 we get:

𝐑𝟒 𝐑𝟑

(𝟏 + 𝟐

𝐑𝟏 𝐑𝟐

)(𝐕𝟐 − 𝐕𝟏 ) ….. (3) 19 Prepared By: SriKisna Khadka BLEX 2006 Batch: WHCSE

…




𝐑𝟒

Hence, the overall gain is

𝐑𝟑

(𝟏 + 𝟐

𝐑𝟏 𝐑𝟐

WHCSE BLEX V

), which is known as differential gain. Usually

the output stage of this instrumentation amplifier is unity gain differential amplifier by choosing R4 = R3. 𝐕𝐎

= (𝟏 + 𝟐

𝐑𝟏 𝐑𝟐

)(𝐕𝟐 − 𝐕𝟏 ) ……(4)

Gain can be varied easily by changing the value of single resistor R2 in three op-amp instrumentation amplifier while other arrangements involves involve variation of two resistors simultaneously. The input impedance seen by such source V1 and V2 is ideally infinite or practically very high thus there will be no gain error due to finite or unbalanced source impedances. Since first stage provides unity gain for common mode signal and second stage is differential stage, it will completely reject common mode signal, provided that R3 and R4 of output stage are accurately matched. Examples Q.1 Find the value of R1 and R2, so that gain

Q.2 Certain IA has a gain of 40dB & a CMRR

can be adjusted over the range 2 to 1000. Assume R3 = R4.

of 100dB. It is used in a noisy environment in which the signal has a level of 50mV & the common mode noise level is 100mV.

Solution: We know that, the gain of three op-amp IA is: G = 1 + 2R1/R2 For, G = 2, 2 = 1+2R1/R2 = 1+2R1/(Rf+ Rv) ….(i) For, G = 1000 1000 = 1+2R1/R2 = 1+2R1/Rf …..(ii)

Here, Rf is fixed value of resistor (R2) for maximum gain = 1000. When the variable resistor value (Rv) is increased, the gain of IA decreases. We have to find the range of R2. (from Rf to Rv). So that we can adjust the gain from 2 to 1000. Let Rv = 100K Then, equation …(i) becomes: 2 = 1+2R1/R2 = 1+2R1/(Rf+ 100) … (iii)

From equation … (ii) 1000Rf - Rf = 2R1 i.e. 2R1 = 999Rf … (iv)

Determine: (a) Common Mode Gain (b) Signal Output (c) Noise Output (iv) Output Signal Voltage to Noise Ratio

Solution: Given, Ad=40dB, CMRR=100dB, Vi=50mV & Vcm=100mV. (a) CMRRdB = 20log10|Ad/Acm|

100

= 20log10|Ad/Acm| … (i)

But, (Ad)dB = 20log10|Ad| 40 = 20log10|Ad|  Ad = 10(40/20) = 100 Now, From equation …(i), we get: 100 = 20log10|100/Acm|  100/Acm = 10(100/20) = 105 i.e. Acm = 100/105 = 10-3

From equations (iii) and (iv) 2 = 1+999Rf/(Rf+100) i.e. 2Rf+200 = Rf+100+999Rf i.e. 998Rf = 100 i.e. Rf = 0.1K

(b) Vo

= AdVi

= (40dB)×50mV = 10(40/20)×50×10-3 =5V

So, from equation … (iv) 2R1 = 999×0.1 = 100.1K i.e. R1 = 50.05K

(c) no = AcmVcm = 10-3×100mV = 10mV

So, we can vary R2 from 0.1K to 100.1K to change the gain from 1000 to 2.

(d) SNR = Vo/no = 5V/10mV = 50000


…




WHCSE BLEX V

Isolation Amplifier Introduction Isolation Amplifier is similar to the instrumentation amplifier having a fixed differential

gain over a wide range of frequencies, high input impedance and low output impedance. Isolation Amplifiers are used when two stages are to be separated in such a way that output depends on the input but any variations in the output has no effect on the input. Application  In biomedical instruments, where safety is mandatory i.e. to restrict the leakage current through patient below 10μA.  In voltage industrial process, where common mode voltage is very large in the range of 100V to KV and common mode rejection is required.  In a system, where there is large mismatch between the source impedances but still very high CMRR is required. Types of Isolation Amplifier Electromagnetically Coupled Isolation Amplifier Sensor Circuit

Instrumentation Amplifier

Modulator

Coupling

Transmorfer

O/P Part

Fig: Electromagnetically Coupled Isolation Amplifier

An amplified signal is modulated with a high frequency signal and modulated signal is coupled to the output circuit through transformer. The transformer couples at the carrier frequency of the modulator but does not couple the other frequency signal so that, the dangerous current (e.g. 250V/50Hz) signal cannot pass to the input circuit. Optically Coupled Isolation Amplifier Vr

Ii Vi

Ri

-

Ii

Ii

IO

RO IO

+ Photo Emitter

Photo Detector

-

Opto-Coupler

VO + Fig: Optically Coupled Isolation Amplifier


…




WHCSE BLEX V

The input current (Ii) due to the input signal excites the photo emitter to produce the light. The intensity of the light depends on the input current. The photo detector of the output circuit detects the light emitted by the photo emitter and causes the output current (IO) to flow through RO. This output current provides the output signal. Here, IO  Ii i.e. IO & VO

= Ii = - IORO = - KIiRO = - K(Vi/Ri)RO = K’Vi

i.e. VO

( Ii = Vi/Ri) ( K’ = -KRO/Ri)

The advantage of optically coupled isolation amplifier is that it completely eliminates the electrical path between output and input sections. If Vi is negative, diode is reverse biased and the circuit cannot work. So, we need the next circuit so that it works for both positive and negative inputs. Vr

Ii Ri

Vi

-

Ii

IO

RO

R1

V1

IO + Photo Emitter

Photo Detector

-

Opto-Coupler

VO Fig: Optically Coupled Isolation Amplifier Operating In Both Positive & Negative Inputs

𝐕𝟏

Now, 𝐈𝐢 =

𝐑𝟏

+

+

𝐕𝐢 𝐑𝐢

We Know, 𝐈𝐎 ∝ 𝐈𝐢 𝐕 i.e. 𝐈𝐎 = 𝐊𝐈𝐢 = 𝐊( 𝟏 + 𝐑𝟏

𝐕𝐢 𝐑𝐢

)

And we have, 𝐕 𝐕𝐎 = −𝐈𝐎 𝐑 𝐎 = −𝐊( 𝟏 + 𝐑𝟏

𝐕𝐢 𝐑𝐢

)𝐑 𝐎

If R1 = Ri, then 𝐕𝟏

𝐕𝐎 = −𝐊(

𝐑𝟏

+

𝐕𝐢 𝐑𝟏

)𝐑 𝐎 = −𝐊

𝐑𝐎 𝐑𝟏

(𝐕𝟏 + 𝐕𝐢 ) = 𝐊′(𝐕𝟏 + 𝐕𝐢 )

(K’ = -KRO/R1)

Hence, the system can work at positive as well as negative input signal.


…




WHCSE BLEX V

Logarithmic Amplifier Contents: o o o o

Logarithmic Amplifier: Introduction Types of Logarithmic Amplifier Antilog/Exponential Amplifier Application of Log & Antilog Amplifier

Logarithmic Amplifier Prepared By: SriKisna Khadka BLEX 2006 Batch: WHCSE

23

…




WHCSE BLEX V

Introduction Logarithmic Amplifier produces an output that is proportional to the logarithm of its input. Since, the log function is non-linear, the logarithmic amplifier is also non-linear. It is used to amplify the signals having a wide dynamic range from few mV to V. E.g. for input of 1mV to 1V then output is from 1V to 10V. VO DVO

Gain = DVi/DVO

DVO

For small input, large gain For large input, small gain

Vi DVi

DVi

Fig: Logarithmic Transfer Characteristic

Logarithmic Amplifier finds its application for comprising wide range of input voltage. Types of Logarithmic Amplifier Logarithmic Amplifier using Single Op-amp & a Diode +

VD

-

If R

Vi

-

I +

VD

Fig: Logarithmic Amplifier Using Single Op-Amp & A Diode

The feedback element is the diode in this circuit. 𝐕𝐃 𝐕𝐓

We know: 𝐈𝐟 = 𝐈𝐬 (𝐞

− 𝟏)

Where, 24 Prepared By: SriKisna Khadka BLEX 2006 Batch: WHCSE

…



Is VT K T q 


WHCSE BLEX V

= Saturation Current (Function of Temperature) = Thermal Voltage = KT/q = Boltzmann’s Constant = 1.38×10-23 J/K = Absolute Temperature = 1.68×10-19 Coulomb = 1 Is, 𝐈𝐟 = 𝐈𝐬 𝐞 or, 𝐕𝐃 = VT ln

If Is

or, 𝐕𝐃 = VT (ln If − ln Is ) We have: I i.e. Vi/R But, Vo 

= If = If = -VD

𝐕𝐃 = VT (ln

Vi R

− ln Is ) Vi

)

i.e.

𝐕𝐎 = −VT (ln



𝐕𝐎 = 𝐊 𝟏 (ln K 2 Vi ), Where, K1 = −VT and K2 =

RIs

1 RIs

Thus, output voltage is proportional to the logarithm of the input voltage. Logarithmic Amplifier using Two Op-amps & Two Diodes

+

If Vi

R

VD1 -

R2

D1

-

I

Rf

V1

-

- VD2 +

V2

D2

+

VO

+

IR

Fig: Logarithmic Amplifier Using Two Op-Amps & Two Diodes


…




WHCSE BLEX V

Since, saturation current depends heavily upon temperature, the output voltage is affected by the temperature. So, the circuit must be made temperature independent. The above circuit is used for this temperature compensation. The saturation current term is removed by the use of current source IR. The current source forces current through D2, which in turn generates the voltage VD2. We have, V1 = −VT1 {ln or, V2 = −VT1 {ln

Vi R1 Vi R1

− ln Is1 } and V2 = V1 + VD2 − ln Is1 } + VT2 {ln IR − ln Is2 }

If two diodes are matched, then VT1 = VT2 = VT and Is1 = Is2 = Is  V2 = −VT ln

Vi

+ VT ln Is + VT ln IR − ln(Is ) VT

R1 Vi

i.e. V2 = −VT {ln

R1 I R

}

Now, VO = (1 +

Rf R2

)V2 = −VT (1 +

 VO = K1 ln(K 2 Vi )

Rf R2

) ln

Vi R1 I R

Where, K1 = -VT(1+Rf/R2) and K2 = 1/(R1IR)

This figure cannot work for negative Vi. In summary, output is proportional to the logarithm of input voltage. The output is independent of Is. And we can compensate temperature dependent term VT by using temperature sensitive resistor R2. Logarithmic Amplifier using Matched Transistors Vr IC1 Q1 R1 Vi

-

I1

R2

IC2 Q2

R5

+

V+

+ VO

R3

R4

Fig: Logarithmic Amplifier Using Matched Transistors

Applying KVL, 26 Prepared By: SriKisna Khadka BLEX 2006 Batch: WHCSE

…




Vr = I2 R 2 + VBE2 − VBE1 Here, I2 = IC2 + IB2 ≈ IC2  Vr = IC2 R 2 + VBE2 − VBE1

VBE = VT ln

So, VBE1 = VT1 ln

Vr R2

Vi

& IC1 ≈

R1

a

VBE

For Transistor: 

Where, IC2 ≈

WHCSE BLEX V

IE ≈ Ic ≈ Is e VT Ic Is IC1 IS1

& VBE2 = VT2 ln

IC2 IS2

The input to second op-amp is: V + = VBE2 − VBE1 I I V + = VT2 ln C2 − VT1 ln C1 IS2

IS1

Since, Q1 and Q2 are matched: VT1 = VT2 = VT & IS1 = IS2 = IS  V + = VT ln

IC2 IS

or, V + = −VT ln

− VT ln

IC1 IC2

IC1 IS Vi ⁄R 1

= −VT ln(Vr

⁄R 2

So, output voltage is: R VO = V + (1 + 4 )

) = −VT ln(

Vi R2

Vr R1

)

R3

Vi R2

VO = −VT ln(

Vr R1

) (1 +

R4 R3

)

Hence, in this case we can compensate the effect of VT by making R3 also temperature dependent. Antilog/Exponential Amplifier using Op-amps & Diodes +

VD1 -

Rf

D1 IR

IR -

Vi

R2

- VD2 +

V2 I2

D2

I2 +

V1

VO

+

R1

Fig: Antilog/Exponential Amplifier Using Op-amps & Diodes

Antilog amplifier produces output which is anti-logarithm of input voltage. 27 Prepared By: SriKisna Khadka BLEX 2006 Batch: WHCSE

…




From the figure: V1 =

WHCSE BLEX V

R1

V R1 +R2 i

The voltage drop across diode D1 is given by: VD1 = VT1 (ln

IR IS1

)

Now, R1 V R1 +R2 i

V2 = V1 – VD1 =

− VT1 (ln

IR IS1

) ……(1)

For second diode, D2: V2 = 0 – VD2= −VT2 (ln

I2 IS2

) ……(2)

If diodes D1 and D2 are perfectly matched, then IS1 = IS2 = IS and VT1 = VT2 = VT So, equating equation (1) with (2), we get: −VT2 (ln

I2 IS2

)=

R1 V R1 +R2 i

− VT1 (ln

IR IS1

)

or, −VT ln I2 + VT ln IS + VT ln IR − VT2 ln IS = or, VT ln

𝐈𝐑 𝐈𝟐

𝐑𝟏 V 𝐑 𝟏 +𝐑 𝟐 i

=

R1 V R1 +R2 i

…..(3)

We have: VO = I2 R f or, I2 =

𝐕𝐎 𝐑𝐟

Now, equation …(3) becomes: VT ln

𝐈𝐑 𝐑 𝐟

or, −VT ln or, ln

𝐕𝐎 𝐈𝐑 𝐑 𝐟

𝐕𝐎 𝐕𝐎 𝐈𝐑 𝐑 𝐟

=−

=

𝐑𝟏 V 𝐑 𝟏 +𝐑 𝟐 i

=

𝐑𝟏 V 𝐑 𝟏 +𝐑 𝟐 i

𝟏 𝐑𝟏 V 𝐕𝐓 𝐑 𝟏 +𝐑 𝟐 i

or, VO = IR R f exp(−

𝐕𝐢

𝐑𝟏

𝐕𝐓 𝐑 𝟏 +𝐑 𝟐

or, VO = K1 exp(K 2 Vi )

) Where, K1 = IR R f & K2 = −

𝟏

𝐑𝟏

𝐕𝐓 𝐑 𝟏 +𝐑 𝟐

Antilog/Exponential Amplifier using Matched Transistor 28 Prepared By: SriKisna Khadka BLEX 2006 Batch: WHCSE

…




WHCSE BLEX V

Vr R3 IC1 V+

IC2

Q1

R4 Q2 -

R5

R1 Vi

V+

VO

+

+

R2 Fig: Antilog Amplifier Using Matched Transistors

V+ = IC1 =

𝐑𝟐 V 𝐑 𝟏 +𝐑 𝟐 i

…..(1)

𝐕𝐑 −𝐕 +

(VR >> V+)

𝐑𝟑

IC1 =

𝐕𝐑 𝐑𝟑

Also, 𝐕 + = 𝐕𝐁𝐄𝟏 − 𝐕𝐁𝐄𝟐 And, we have: 𝐕𝐁𝐄𝟏 = VT1 (ln

𝐈𝐂𝟏 𝐈𝐒𝟏

) & 𝐕𝐁𝐄𝟐 = VT2 (ln

𝐈𝐂𝟐 𝐈𝐒𝟐

)

For matched transistors: VT1 = VT2 & IS1 = IS2 𝐕𝐁𝐄𝟏 = VT (ln

𝐈𝐂𝟏 𝐈𝐒

) & 𝐕𝐁𝐄𝟐 = VT (ln

𝐈𝐂𝟐 𝐈𝐒

)

Now, 𝐕 + = VT (ln

𝐈𝐂𝟏 𝐈𝐂𝟐

) = − VT (ln

𝐈𝐂𝟐 𝐈𝐂𝟏

) = −VT (ln

𝐕𝐎 𝐑 𝟑 𝐑 𝟒 𝐕𝐑

) (IC2 = VO/R4)

Equating (1) and (2), we get: −VT (ln or,

VO R3 R4 VR

VO R3 R4 VR

)=

= exp(−

or, VO = VR

R4 R3

𝐑𝟐 V 𝐑 𝟏 +𝐑 𝟐 i 1 𝐑𝟐 V) VT 𝐑 𝟏 +𝐑 𝟐 i

exp(−

or, VO = K1 exp(K 2 Vi )

1 𝐑𝟐 V) VT 𝐑 𝟏 +𝐑 𝟐 i

Where, K1 = VR

R4 R3

& K2 = −

R2 VT (R1 +R2 )


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WHCSE BLEX V

Application of Log & Antilog Amplifier 1. The log and antilog amplifiers can be used in combination for generation of arbitrary function by using the input to a power of some value. E.g. VO = Vi, where  is scaling factor and can be greater than 1 or less than 1. The interpretation of this application can be achieved as follows. Vi

VO1= K1ln(K2Vi)

Log

V2= VO1

Antilog

VO=K3exp(K4V2)

Fig: Application of Log & Antilog Amplifier

Here, 

VO1 V2 VO

i.e.

VO

= K1ln(K2Vi) = VO1 = K1ln(K2Vi) = K3exp{K4K1ln(K2Vi)} = K3exp{ln(K2Vi)K4K1} = K3(K2Vi) K4K1

For K1K4 = 1, K2 = 1 and K3 = 1,

= Vi 

VO

2. Log and antilog amplifier can be used for compression and expansion of signal. 3. They can be used in the design of analog multiplier and divider. Multiplier R

V1

VO1

Log

R

-

VO3

Antilog

+ V2

VO2

Log

R

Adder

Fig: Analog Multiplier Using Log & Antilog Amplifier

Here, VO1 = K1ln(K2V1) VO2 = K3ln(K4V2) VO3 = -K1ln(K2V1)-K3ln(K4V2) For K1 = K3 = 1 and K2K4 = 1,

VO3 = ln(V1V2)

Now, VO = K5exp{K6ln(V1V2)} = K5exp{ln(V1V2)K6} For K5 = K6 = 1,

VO = V1V2 30 Prepared By: SriKisna Khadka BLEX 2006 Batch: WHCSE

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WHCSE BLEX V

Divider V1

Log

VO1 Subtractor

V2

Log

VO3

VO

Antilog

VO2

Fig: Analog Divider Using Log & Antilog Amplifier

Here, VO1 = K1ln(K2V1) VO2 = K3ln(K4V2) Vo3 = VO1-VO2 = K1ln(K2V1) - K3ln(K4V2) For K1 = K3 = 1, VO3 = ln(K2V1/K4V2) Again, For K2/K4 = 1, VO3 = ln(V1/V2) Finally, VO = K5exp(K6VO3) = K5exp{ ln(V1/V2)} So, for K5 = K6 = 1,

VO = V1/V2

Four Quadrant Multiplier VR VA

Adder

V1

V1+VA

One Quadrant Multiplier

VR VB

Adder

(V1V2+V1VB+V2VA+VAVB)/K1

V2+VB

V2 (V2VA)/K1

-

+

Subtractor

(V1VB)/K1

VR

Fig: Four Quadrant Multiplier

-

(VAVB)/K1


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WHCSE BLEX V

In one quadrant multiplier the input signals should have positive polarity. If the input signals are not positive, then the circuit will not work. This there should be a circuit that can multiply the signals no matter what the polarity is. The above circuit is the necessary diagram for this purpose. It can work for any combination of input voltages as (+ +), (+ -), (- +), (- -). In this multiplier, there are three stages: adder, one quadrant multiplier and subtractor. Since, one quadrant multiplier works for only positive signals, the adder provides it with positive polarity by adding the input signal (V1 or V2) with the another signal having higher potential so that, the polarity of the signal at the output terminal of the adder becomes positive even if the input signal is negative. From the above figure, The output of one quadrant multiplier is: 𝐕𝐎𝟏 =

𝐕𝟏 𝐕𝟐 +𝐕𝟏 𝐕𝐁 +𝐕𝟐 𝐕𝐀 +𝐕𝐀 𝐕𝐁 𝐊𝟏

The subtractor subtracts the terms (V1VB)/K1, (V2VA)/K1 and (VAVB)/K1 from the above expression so as to provide the net output VO as given by: 𝐕𝐎 =

𝐕𝟏 𝐕𝟐 𝐊𝟏

Circuit Diagram for Four Quadrant Multiplier VR

IC3

Q3

R

A1 + Q1 IC1

R V1

A2

R

R

+ VB4 IC2

VE4 Q2

R V2

A3

R +

I

IC4 Q4 V1 V2 V3

R R

A4 +

VO

R

Fig: Circuit Diagram for Four Quadrant Multiplier


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WHCSE BLEX V

Stage 1: Adder: By A2 and A3 Stage 2: One Quadrant Multiplier: By A2, A3 and Q4 Stage 3: Subtractor: By A4 Derivation: 𝐕𝐎 = −𝐈𝐑 𝐕 𝐕 𝐕 = ( 𝟏 + 𝟐 + 𝐑 − 𝐈𝐂𝟒 )𝐑 𝐑

𝐑

𝐑

All the values are known except IC4. VBE4

IC4 = Is exp(

VT

) [ = 1]

Now, VBE4= = ? I VB4 = −VBE3 = −VT ln C3 Is

VE4 = 0 − VBE1 − VBE2 = −VBE1 − VBE2 = −VT ln ∴ VBE4 = VB4 − VE4 = −VT ln ∴ VBE4 = VT ln

IC1 IC2

IC3 Is

+ VT ln

IC1 Is

+ VT ln

IC1 Is

− VT ln

IC2 Is

IC2 Is

IC3 Is

So, IC4 = Is exp[ IC1 IC2 ∴ IC4 = IC3

I I VT ln( IC1 IC2 ) C3 s

VT

] = Is

IC1 IC2 IC3 Is

But,

IC1 = ∴ IC4 =

V1 +VRE R

V +V V +V ( 1 R R )( 2 R R ) VR R

V1

∴ VO = −( =

, IC2 =

+

V2

+

V2 +VR R

=

VR

& IC3 =

VR R

(V1 +VR )(V2 +VR ) RVR

−

V1 V2 +V1 VR +V2 VR +VR 2

R R R RVR V1 VR +V2 VR +VR 2 −V1 V2 −V1 VR −V2 VR −VR 2

𝐕𝐎 = 𝐊𝐕𝟏 𝐕𝟐

VR

)R

=

V1 V2 VR

= KV1 V2

Where, K = 1/VR


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WHCSE BLEX V

Square Root Function Using Multiplier VO2

I

VO

R I

R

VO

-

Vi

VO +

Fig: Square Root Function Using Multiplier

A multiplier circuit can be implemented to produce a square root function. As shown in above figure, the output voltage Vo is fed to the multiplier’s input terminals which produce the square of the output voltage as Vo is multiplied by itself. Hence, the feedback product is fed to the inverting terminal of an op-amp (which is virtually ground) to make a system complete to which a dc voltage supply Vi with source resistance R is already applied. Here,

𝟎−(−𝐕𝐢 ) 𝐑

=

𝐕𝐎 𝟐 −𝟎 𝐑

 𝐕𝐎 = √𝐕𝐢


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WHCSE BLEX V

Communication Circuits Contents: o o o o o o

Communication Circuits: Introduction Modulation & Its Types Modulation Circuits Frequency Conversion Demodulation Demodulation Circuits


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WHCSE BLEX V

Communication Circuits Introduction Communication is a system in which message signal or information is transferred from one point to another point i.e. the purpose of a communication system is to transmit an information bearing signal from source located at one point to destination located at another point some distance away. The following block diagram shows the components for communication. Information Source

Input Transducer

Information Destination

Noise & Disturbances

Communication Channel

Transmitter

Receiver

Output Transducer

Fig: Communication System

Block Diagram Description

 Information Source: A communication system serves to communicate a message or information; originates for the information source as in the form of words, groups of words, codes , symbols , sound, signals etc. We can say that the function of information source is to produce required message which has to be transmitted.  Input Transducer: The message from the information source may or may not be electrical in nature. In the case when message produce by the information source is not electrical in nature and input transducer is used to convert it into an electrical signal.  Transmitter: The transmitter modifies the message signal for efficient transmission. Transmitter is required to make the signal suitable for signal conduction over the channel. Modulation is the main function of the transmitter. In modulation the message signal is superimposed upon the high frequency carrier signal.  The Channel & Noise: Channel means the medium through which the modulated signal travels from the transmitter to receiver. The function of the channel is to provide a physical connection between the transmitter and the receiver. During the process or transmission and reception the signal gets distorted due to noise introduce in the system. Noise is an unwanted signal which tends to interfere with the required signal. Noise signal is always random in nature. Noise may interfere with signal at any point in a communication system, however the noise has its greatest effect on the signal on the channel.  Receiver: The main function of the receiver is to reproduce the message signal in electrical form the distorted received signal. This reproduction of the original signal is accomplished by a process known as the demodulation or detection. Demodulation is the reverse process of modulation carried out in transmitter.  Destination: It is the final stage which is use to convert an electrical message signal into it’s original form. 36 Prepared By: SriKisna Khadka BLEX 2006 Batch: WHCSE

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WHCSE BLEX V

Modulation The low frequency message signals are suffered from noise while transmitting from one point to another point. So, they are not suitable for communication purpose. They must be converted into the suitable form before transmission, which process is called modulation. The term modulation means ‘to change’ or ‘to modify’. The interest in amplitude modulation signals in measurement system is on account of two reasons: 1. Physical data that are to be measured, processed and interpreted are, many a times, amplitude modulated. 2. When carrying out dynamic measurements, the measurement systems are intentionally designed to introduce amplitude modulation on account of various advantages. There are, invariably, two parts to any method of modulation. 1. Carrier: This is the medium that carries the information or intelligence. 2. Signal: The signal is the information or intelligence to be carried. Need of Modulation

 Sound waves or low frequency waves cannot be transmitted to longer distances.  If low frequency message signal is transmitted, it will suffer from high frequency noise signals. And the original signal can not be separated from noise at the receiving side.  For transmitting low frequency signal directly, very large size antenna is required. As we know, Minimum length of antenna, =

 𝟒

and 

𝐂

𝟑×𝟏𝟎𝟖



𝐟

= =

Therefore, Lower the frequency, longer is the antenna required.  Modulation is used to shift the frequency range of message signal. Demodulation

It is the process of separating or reversing the message signal from modulated wave. It is performed at receiving side. Types of Modulation According to the variation in the characteristics of carrier signal due to the effect of message signal, modulation can be broadly classified into following categories. A. On the basis of Carrier Signal

1. Continuous Wave Modulation (Sinusoidal Wave as a Carrier) a. Amplitude Modulation (AM) b. Angle Modulation i. Frequency Modulation (FM) ii. Phase Modulation (PM) 2. Pulse Code Modulation (Periodic Signal/Rectangular or Digital Pulse as a Carrier) a. Pulse Amplitude Modulation (PAM) b. Pulse Duration Modulation (PDM) c. Pulse Position Modulation (PPM) 37 Prepared By: SriKisna Khadka BLEX 2006 Batch: WHCSE

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WHCSE BLEX V

B. On the basis of Base-Band/Message Signal

1. Analog Modulation (Base-Band Signal is Analog) a. Amplitude Modulation (AM) b. Frequency Modulation (FM) c. Phase Modulation (PM) 2. Digital Modulation (Base-Band Signal is Digital) a. Amplitude Shift Key (ASK) b. Phase Shift Key (PSK) c. Frequency Shift Key (FSK) d. Gaussian Shift Key (GSK) e. Quadrature Phase Shift Key (QPSK) f. Offset Quadrature Phase Shift Key (OQPSK) Amplitude Modulation If the amplitude of the carrier wave is varied in accordance with the message signal then it is called amplitude modulation. In a broad sense, an amplitude modulation is a process, in which the amplitude of carrier wave c(t) is varied about a mean value linearly with message/base-band signal m(t). Let us consider a Carrier Wave, 𝐂(𝐭) = 𝐀 𝐜 𝐜𝐨𝐬(𝟐𝛑𝐟𝐜 𝐭) & Message Signal 𝐦(𝐭) = 𝐀 𝐦 𝐜𝐨𝐬(𝟐𝛑𝐟𝐦 𝐭) Where, Ac & fc are Amplitude & Frequency of Carrier Wave. Am & fm are Amplitude & Frequency of Message Signal. After amplitude modulation, the modulated wave becomes: 𝐬(𝐭) = [𝐀 𝐜 + 𝐦(𝐭)]𝐜𝐨𝐬(𝟐𝛑𝐟𝐜 𝐭) 𝐦(𝐭) = 𝐀 𝐜 [𝟏 + ]𝐜𝐨𝐬(𝟐𝛑𝐟𝐜 𝐭) = 𝐀 𝐜 [𝟏 +

𝐀𝐜 𝐀𝐦 𝐜𝐨𝐬(𝟐𝛑𝐟𝐦 𝐭) 𝐀𝐜

]𝐜𝐨𝐬(𝟐𝛑𝐟𝐜 𝐭)

𝐬(𝐭) = 𝐀 𝐜 [𝟏 + 𝐦. 𝐜𝐨𝐬(𝟐𝛑𝐟𝐦 𝐭)]𝐜𝐨𝐬(𝟐𝛑𝐟𝐜 𝐭) Where, m = Am/Ac = Modulation Index Modulation Index & Percentage Modulation

In amplitude modulation system, the modulation index is defined as the measure of extent of amplitude variation about an unmodulated maximum carrier. It is represented by m. Mathematically, Modulation Index, 𝐦 =

|𝐱(𝐭)| 𝐌𝐚𝐱𝐢𝐦𝐮𝐦 𝐂𝐚𝐫𝐫𝐢𝐞𝐫 𝐀𝐦𝐩𝐥𝐢𝐭𝐮𝐝𝐞

Percentage Modulation, %𝐦 =

|𝐱(𝐭)|𝐦𝐚𝐱 𝐀

=

|𝐱(𝐭)|𝐦𝐚𝐱 𝐀

and

× 𝟏𝟎𝟎%

The modulation index indicates the degree to which the message signal modulates the carrier wave. It is also known as depth of modulation, degree of modulation or modulation factor. 38 Prepared By: SriKisna Khadka BLEX 2006 Batch: WHCSE

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WHCSE BLEX V

1. Under Modulation

The base-band or modulating signal will be preserved in the envelope of the amplitude modulated signal only if we have, |x(t)|max  A, (i.e. the modulation index is less than or equal to unity or the percentage modulation is less than or equal to 100%). If |x(t)|max < A Then it is called the under modulation. S(t)

Am Amax

Ac

Amin

Time Fig: Under Modulation

Let us consider the above waveform of a case of under-modulation. 𝐀 −𝐀 Where, 𝐀 𝐦 = 𝐦𝐚𝐱 𝐦𝐢𝐧 𝟐

And 𝐀 𝐜 = 𝐀 𝐦𝐚𝐱 − 𝐀 𝐦 = 𝐀 𝐦𝐚𝐱 − Modulation Index, 𝐦 =

𝐀𝐦 𝐀𝐜

=

𝐀𝐦𝐚𝐱 −𝐀𝐦𝐢𝐧 𝟐

𝐀𝐦𝐚𝐱 −𝐀𝐦𝐢𝐧 𝐀𝐦𝐚𝐱 +𝐀𝐦𝐢𝐧

=

𝐀𝐦𝐚𝐱 +𝐀𝐦𝐢𝐧 𝟐

& Percentage Modulation, %𝐦 =

𝐀𝐦 𝐀𝐜

× 𝟏𝟎𝟎%

2. 100% Modulation

In case, if |x(t)|max = A, the minimum peak to peak level of modulated wave (i.e. Amin) is zero, then modulation index (m) = 1 (or percentage modulation, % m=100%). This is called 100% modulation and the maximum power can be transmitted in this stage without distortion.

Fig: 100% Modulation

3. Over Modulation

In over modulation, the amplitude of modulated wave is greater than twice the carrier amplitude (i.e. |x(t)|max > A). However, the message signal gets distorted at some time intervals as shown in the figure below. So, we can not perform modulation greater than 100% for distortion less communication.

Fig: Over Modulation


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WHCSE BLEX V

Let us see the modulated output under all these three cases with the modulating signal as a sinusoidal and a square wave.

Fig(a :)Different Cases of Amplitude Modulation with Sine Wave as a Carrier

Fig(b)Different Cases of Amplitude Modulation With Square Wave as a Carrier


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WHCSE BLEX V

Spectrum Analysis

As we have already derived the output equation for modulated signal, which was found to be as follows: 𝐒(𝐭) = 𝐀𝐜 [𝟏 + 𝐦. 𝐜𝐨𝐬(𝟐𝛑𝐟𝐦 𝐭)]𝐜𝐨𝐬(𝟐𝛑𝐟𝐜 𝐭) 𝐀 = 𝐀𝐜 𝐜𝐨𝐬(𝟐𝛑𝐟𝐜 𝐭) + 𝐦 𝐜 𝟐𝐜𝐨𝐬(𝟐𝛑𝐟𝐦 𝐭)𝐜𝐨𝐬(𝟐𝛑𝐟𝐜 𝐭) 𝟐 𝐀

𝐀

𝐒(𝐭) = 𝐀𝐜 𝐜𝐨𝐬(𝟐𝛑𝐟𝐜 𝐭) + 𝐦 𝐜 𝐜𝐨𝐬[𝟐𝛑(𝐟𝐜 + 𝐟𝐦 )𝐭] + 𝐦 𝐜 𝐜𝐨𝐬[𝟐𝛑(𝐟𝐜 − 𝐟𝐦 )𝐭] 𝟐 𝟐 = 𝐂𝐚𝐫𝐫𝐢𝐞𝐫 𝐒𝐢𝐠𝐧𝐚𝐥 𝐜(𝐭) + 𝐔𝐩𝐩𝐞𝐫 𝐒𝐢𝐝𝐞𝐛𝐚𝐧𝐝 (𝐔𝐒𝐁) + 𝐋𝐨𝐰𝐞𝐫 𝐒𝐢𝐝𝐞𝐛𝐚𝐧𝐝 (𝐋𝐒𝐁)

The amplitude modulation process can be analyzed with following characteristics wave form & frequency spectrum. m(t)

Am

t

-fm Ac

Message Signal

c(t)

t

-fc

f in KHz

fc A

Carrier Signal

s(t)

f in KHz

fm

t

-fc+fm

Fig: Amplitude Modulated Signal

-fc -fc+fm

fc-fm

fc

f in KHz

fc+fm

Fig: Frequency Spectrum

Power & Efficiency

The total transmitted power is given by: PT = PC+PUSB+PLSB Where,

PC PUSB PLSB

= Power of Carrier =

𝐀𝐜 𝟐 𝟐

= Power of Upper Sideband = = Power of Lower Sideband =

 PT =

𝐀𝐜 𝟐

𝟐

+

𝐦𝟐 𝐀𝐜 𝟐 𝟖

+

𝐦𝟐 𝐀𝐜 𝟐

Hence, the efficiency is given by:  =

𝟖

=

𝐀𝐜

𝐏𝐔𝐒𝐁 +𝐏𝐋𝐒𝐁 𝐏𝐓

𝐦𝟐

𝟐

𝟐

=

𝐦𝐀𝐜 𝟐 )⁄ 𝟐


𝐦𝐀 ( 𝐜 )𝟐⁄ 𝟐


(

(𝟏 +

𝟐= 𝟐=

𝐦𝟐 𝟐

𝟖

𝟖

)

𝐦𝟐 𝐀𝐜 𝟐 𝐦𝟐 𝐀𝐜 𝟐 + 𝟖 ) 𝟖 𝟐 𝐀𝐜 𝐦𝟐 (𝟏+ 𝟐 ) 𝟐

(

=

𝐦𝟐 𝟐+𝐦𝟐

𝟏

For m = 1 (i.e. 100% modulation), 𝐦𝐚𝐱 = 𝟐+𝐦𝟐 = 𝟑 = 𝟑𝟑. 𝟑𝟑%


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WHCSE BLEX V

Frequency Modulation Frequency modulation is a technique, in which the instantaneous frequency fi is varied linearly with a message or base-band signal m(t) about an unmodulated carrier frequency fc. But the amplitude of the carrier is kept constant. Mathematically, Instantaneous frequency, (fi) = fc + kf.m(t) …(i) Where, kf is proportionality constant and is known as the frequency sensitivity of the modulator. This is expressed in Hz/Volt. After frequency modulation, the frequency of carrier is deviated from fc and can be described with equation (i). As we have, Message Signal 𝐦(𝐭) = 𝐀 𝐦 𝐜𝐨𝐬(𝟐𝛑𝐟𝐦 𝐭) Carrier Wave, 𝐂(𝐭) = 𝐀 𝐜 𝐜𝐨𝐬(𝟐𝛑𝐟𝐜 𝐭 + 𝛉𝟎 ) = 𝐀 𝐜 𝐜𝐨𝐬∅ … (ii) Where, ∅ = 𝟐𝛑𝐟𝐜 𝐭 + 𝛉𝟎 (The total phase angle of the unmodulated carrier.) Let ∅𝐢 be the instantaneous phase angle of the modulated signal. Then on frequency modulation amplitude Ac must remain constant and only angle ∅ will change. Hence the expression for frequency modulated wave will be: 𝐒(𝐭) = 𝐀𝐜𝐨𝐬∅𝐢 …(iii) As, ∅ = 𝟐𝛑𝐟𝐜 𝐭 + 𝛉𝟎 𝐝 or, 𝐂 = 𝟐𝛑𝐟𝐜 𝐝𝐭 or, ∅ = ∫ 𝟐𝛑𝐟𝐜 dt …(iv) Based on equation (iv), we may write the expression for instantaneous phase angle, ∅𝐢 . i.e.∅i = ∫ 𝟐𝛑𝐟𝐢 dt or, ∅i = ∫ 𝟐𝛑[(fc + k f m(t)] dt or, ∅i = 𝟐𝛑fc t + 𝟐𝛑k f ∫ m(t) dt …(v) Now, putting the value from equation (v) into equation (iii), we get: 𝐒(𝐭) = 𝐀𝐜𝐨𝐬[𝟐𝛑fc t + 𝟐𝛑k f ∫ m(t) dt] … (vi) Where, ∅i = 𝟐𝛑fc t + 𝟐𝛑k f ∫ m(t) dt = 𝟐𝛑fc t + 𝟐𝛑k f ∫ 𝐀 𝐦 𝐜𝐨𝐬(𝟐𝛑𝐟𝐦 𝐭) dt 𝐬𝐢𝐧(𝟐𝛑𝐟𝐦 𝐭) = 𝟐𝛑fc t + 𝟐𝛑k f 𝐀 𝐦 = 𝟐𝛑fc t + 𝟐𝛑k f 𝐀 𝐦 = 𝟐𝛑fc t + k f 𝐀 𝐦

𝟐𝛑𝐟𝐦 𝐭 𝐬𝐢𝐧(𝟐𝛑𝐟𝐦 𝐭)

𝟐𝛑𝐟𝐦 𝐭 𝐬𝐢𝐧(𝟐𝛑𝐟𝐦 𝐭) 𝐟𝐦

∅i = 𝟐𝛑fc t + β𝐬𝐢𝐧(𝟐𝛑𝐟𝐦 𝐭)

… (vii)

Here, β = k f 𝐀 𝐦 /𝐟𝐦 represents the modulation index of frequency modulated signal. It is the ratio of the frequency deviation to the modulation frequency. Finally, we get: 𝐒(𝐭) = 𝐀𝐜𝐨𝐬[𝟐𝛑fc t + β𝐬𝐢𝐧(𝟐𝛑𝐟𝐦 𝐭) ]


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WHCSE BLEX V

The frequency modulation process can be analyzed with following characteristics wave form. Rate of variations in frequency is determined by the frequency of modulation signal. The total variation in frequency is called carrier swing.

m(t)

m(t)

t

c(t)

t

Message Signal (Sinusoidal Wave)

Message Signal (Rectangular Pulse)

c(t)

t

s(t)

t

s(t)

Carrier Signal

Carrier Signal

t

Frequency Modulated Signal Fig: Frequency Modulation with Sinusoidal Wave as a Modulating Signal

t

Frequency Modulated Signal Fig: Frequency Modulation with Rectangular Pulse as a Modulating Signal

In frequency modulation, the phase angle varies linearly with the integral of base-band signal or modulating signal m(t) as described by the following equation. 𝐒(𝐭) = 𝐀𝐜𝐨𝐬[𝟐𝛑fc t + 𝟐𝛑k f ∫ m(t) dt] Hence, frequency modulation can be obtained by a phase modulator. To get frequency modulation, we first integrate the base-band signal and then apply it to the phase modulator circuit. This process is illustrated with the help of a block diagram shown below.

Base-band Signal m(t)

Integrator ò m(t)

Phase Modulator

FM

A.cosct Carrier Generator

Fig: Generation of FM using Phase Modulator


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Numerical Examples Amplitude Modulation Que 1: A 500 W carrier is to be modulated to a 90% level. Determine the total transmitted power. Solution:

As we know, PT

= PC(1+m2/2)

= 500 (1+0.92/2) = 702.5 W

Que 4: If a 1000 KHz carrier wave is modulated by audio signals varying between 100 Hz and 5000 Hz, what is a) the frequency span of the side bands. b) the maximum upper side frequency. c) the minimum lower side frequency. d) the frequency range of the channel. Solution:

Lets have a look to the figure below.

Que 2: An AM broadcast station operates at its maximum allowed total output of 50 KW and at 95% modulation. How much of its transmitted power is intelligence (sidebands) ? Solution:

or, or,

= PC(1+m2/2)

2

50000 = PC(1+0.95 /2) PC = 50000/{(1+0.952/2)} = 34.5 KW

 The power of intelligence signal is given by Pi = PT - PC = 50 KW – 34.5 KW = 15.5 KW Que 3: A transmitter with a 10 KW carrier transmits 11.2 KW when modulated with a single sine wave. Calculate the modulation index. If the carrier is simultaneously modulated with another sine wave at 50% modulation, calculate the total transmitted power. Solution:

or, or, or, or,

= PC(1+m2/2) = 10000(1 + m2/2) = 1 + m2/2 = m2 = 0.49

For next signal, m’ = 0.5  meff = (0.492+0.52) Finally, PT

999.9

fc

1000.1

1005

f-KHz

1000

a) b) c) d)

Span of LSB = USB = 4.9 KHz Maximum USF = 1005 KHz. Minimum LSF = 995 KHz. Frequency Range = (995-1005)KHz.

Que 5: How many AM stations can be accommodated in a 100 KHz band width, if the highest frequency of the message signal is 5 KHz. Solution

BW of message signal = 5+5 = 10 KHz.  Total AM stations = 100/10 = 10. Que 6: An amplitude modulated signal is given by: s(t) = 10(1+0.2 cos2π×103t) cos2π×106t. Find MI, modulating & carrier frequency, BW required and total power & efficiency. Solution:

As we have, PT 11200 1.12 0.24 m

995

Upper Side Band

Hence, from figure, we conclude that:

As we know, PT

Lower Side Band

= 0.7 = PC(1+m2/2) = 10000(1+0.72/2) = 12.45 KW

On comparison with standard equation of amplitude modulated signal we get:    

Modulating Index, m = 0.2 fm = 10KHz and fc = 1MHz. BW = 2×fm = 2×10KHz = 20 KHz. PT = PC + PLSB + PUSB = (Ac2)/2+ (m2Ac2)/8+ (m2Ac2)/8 = (Ac2)/2+ (m2Ac2)/4 = (102)/2+(0.22.102)/4 = 51 Watt.


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Que 7: An audio 60.sin2π(100000t).

a) b) c) d)

signal

15.sin2π(1500t)

WHCSE BLEX V

amplitude

modulates

a

carrier

Construct all the signals. Determine modulation factor and percentage modulation. What are the frequencies of audio signal and the carrier ? What frequencies would show up in the spectrum analysis modulated wave?

Solution:

a) The construction of message and carrier signal takes place as follows with their spectrum. m(t)=15.sin(2p1500t)

Am

15

t

-1.5

f in KHz

1.5 Ac

c(t)60.sin(2p100000t) 60

t

-100

100

f in KHz

A

s(t)

t

-101.5 -100 -98.5

Fig: Amplitude Modulated Signal

98.5

f in KHz 100 101.5

Fig: Frequency Spectrum

b) The modulation factor, m = Am/AC = 15/60 = 0.25 Therefore, % modulation, m% = m×100% = 0.25×100% = 25% c) As, m(t) = Am.sin(2πfmt) and c(t) = Ac.sin(2πfct). So comparing these standard equation with given equation of message and carrier signal, we get: fm = 1.5KHz & fc = 100KHz. d) The frequency spectrum analysis is shown in above figure with the modulated frequencies as the side bands frequencies. Que 8: An amplitude modulated signal has percentage modulation of 85% and contains 1000 watts total power. Calculate the power content of each of the side band.

Solution:

Given, PT and, m

= 1000 watts = 85% = 0.85

As we know: Efficiency,  i.e. PUSB + PLSB i.e. 2PUSB i.e. PUSB

= m2/(2+m2) = {m2/(2+m2)}PT = {0.852/(2+0.852)}1000 = 265.4/2 = 132.69 watts

Hence, PUSB = PLSB = 132.69 watts.


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WHCSE BLEX V

Frequency Modulation Que 1: A 25 mV sinusoid at a frequency of 400 Hz is applied to a capacitor microphone FM generator. If the deviation constant for the generator is 750 Hz/10mV, determine:

a) The frequency deviation generated

by an input level of 25 mV. b) The rate at which the carrier frequency is being deviated. Solution:

a) Positive frequency deviation: 25mV×(750Hz/10mV) =2.25 KHz. Negative frequency deviation: -25mV×(750Hz/10mV) = -2.25 KHz So, the deviation for the given input signal level is  2.25 KHz. b) The carrier frequency deviates at a rate of 400 Hz. Que 2: An frequency modulated signal has a center frequency of 100MHz but is swinging between 100.001 MHz and 99.999 MHz at a rate of 100 times per second. Determine:

a) The intelligence frequency. b) What happens to the intelligence

amplitude if the frequency deviation changes to 100.002 & 99.998 MHz. Solution:

a) fi = (100.001-100) = (100-99.999) = 1000 Hz = 1 KHz. b) The frequency deviation has been doubled and it indicates that the intelligence amplitude is now doubles. Que 3: Determine the modulation index of an FM signal with modulating frequency of 15 KHz and frequency deviation of 75 KHz, when it is being broadcasted for general reception in commercial FM broadcast band.

Solution

Modulating Frequency, fm = 15 KHz. Frequency Deviation, Df = 75 KHz. Modulation Index, β = Df/ fm = 75/15 = 5.

Que 4: An audio signal of 1000Hz frequency modulates a carrier of 100 MHz. Frequency deviation is 10 KHz. a) Calculate modulation index. b) What would be modulation index

if amplitude is doubled frequency is halved.

and

Solution

Given, Frequency Deviation, Df = 10 KHz. Modulating Frequency, fm = 1KHz Carrier Frequency, fc = 100 MHz a) Modulation Index, β = Df/ fm = 10 b) Since, Df = KfAc, If amplitude is double then, Df’ = 2Df = 20KHz and fm’ = fm/2 = 500 Hz. Therefore, β’ = Df’/ fm’ = 40 Que 5: An angle modulated signal is represented by, Emod = Ec.cos{(2π×103t + 4.sin(2π×103t)}. Find

a) b) c) d) e)

Maximum frequency deviation. Maximum phase deviation. Modulating frequency. Bandwidth required. Power to transmit the signal.

Solution

Given, Emod = Ec.cos(2π×103t + 4.sin2π×103t) Where, (t) = 2π×103t + 4.sin2π×103t 1 𝑑

f(t) = (t) 2𝜋 𝑑𝑡 = 103 + 4.103.cos2π×103t

a)

Dfmax = 4.103 = 4KHz b)

(t)|max = 4 radian

c)

fm = 2π×103 radian/sec = 1000 Hz

d)

BW = 2(Df+fm) = 2(4+1) = 10 KHz

e)

Power, P = Ec2/2 46

Prepared By: SriKisna Khadka BLEX 2006 Batch: WHCSE

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WHCSE BLEX V

Modulation Circuits The device which is used to generate a modulated wave is known as modulator and the corresponding circuit is referred as the modulation circuits. Amplitude Modulator

The modulating signal about which the amplitude of carrier signal has to be varied linearly in case of amplitude modulation is coupled with carrier signal itself to a modulating amplifier to have a modulated output. The general block diagram representation of amplitude modulation can be viewed as shown below.

Carrier Signal Modulated Output

Modulating Amplifier Modulating Signal

Fig: General Block Diagram of Modulator

To fulfill the characteristics of above block diagram and to analyze the basic principle of AM generation technique, let us have an example of simple amplitude modulator circuit as shown in below. +Vcc

T2 C4 R1 m(t)

s(t)

c(t)

C1 T1 R2

C2

R3

C3

Fig: AM Generating Circuit

The above figure shows an amplitude modulated transistor amplifier with base injection in the common emitter configuration. The transistor is powered by Vcc through the voltage divider bias network. The carrier signal is coupled to the base of transistor by transformer T1 and modulating signal is coupled through capacitor C1. The modulating signal causes the base bias to increase or decrease. Transformer T2 couples the modulated signal to the load on the amplifier. 47 Prepared By: SriKisna Khadka BLEX 2006 Batch: WHCSE

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BJT Collector Amplitude Modulator

It is a kind of amplitude modulator with following circuit configuration. +Vcc T1 Power Amplifier

m(t)

T2 C1

s(t)

RF Drive Bias

Fig: BJT Collector Modulator

In this AM modulator, thee tuned circuit in the collector is tuned to resonate at the carrier frequency. The modulating voltage is applied in series with Vcc through the low frequency transformer. This signal changes the amplitude of the collector current thus producing modulated output. Frequency Modulator -Vcc Oscillator Tank Circuit FM Out

C1

C

L1

Q1

Cc D1

Ei V

Fig 1: FM Generation Circuit

Fig 2: Characteristics Curve of Varactor Diode

A varactor diode may be used to generate FM directly. The junction capacitance of a varactor diode varies inversely with the amount of reverse bias so this modulator can be regarded as the varactor diode modulator. With no intelligence signal, Ei applied, the parallel combination of C1, L1 and D1 forms the resonant carrier frequency. The diode D1 is effectively in parallel with L1 and C1 since the –Vcc supply appears as a short circuit to the ac signal. The coupling capacitor, Cc, isolates the dc levels and intelligence signal. When the intelligence signal, Ei is applied to the varactor diode, its reverse bias is varied, which causes the diode’s junction capacitance to vary in step with Ei. the oscillator frequency is subsequently varied as required for FM and the FM signal is available at Q1’s collector. 48 Prepared By: SriKisna Khadka BLEX 2006 Batch: WHCSE

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WHCSE BLEX V

Reactance Frequency Modulator

The reactance modulator is the commonly used frequency modulator. In such modulator, the voltage changes of the modulating signal causes changes in the output capacitance (Cce) of the transistor Q2 thereby varying the reactance of its output circuit.

L3

Modulated Signal

L4

T1 L2

L1 Q1

C1

Vcc Q2 Cce

Modulating Signal T2

Fig: Reactance Frequency Modulator

Here, Q1 acts as an oscillator and Q2 as a reactance modulator. The biasing resistors and bypass capacitors have been omitted to simplify the circuit. The oscillator transistor Q1 receives its positive feedback from the secondary winding L3 of the transformer T1. The frequency of the carrier wave is established by the primary winding L1, L2 of T1 and capacitor C1. The output of Q2 is coupled to a portion of the primary winding L2 of T1. Any changes in the input signal voltage at T2 will be accompanied by changes at Q2 in the forward bias, collector current, collector voltage and collector to emitter capacitance. As the collector voltage increases, the collector to emitter capacitance decreases and vice versa. When Cce decreases, the resonant frequency of the tuned circuit (determined by L1L2C1Cce) increases and vice versa. Consequently, the output signal at the secondary winding L4 of T1 will be frequency modulated in accordance with the voltage variations of the input signal at T2.


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WHCSE BLEX V

Frequency Conversion It is a process of converting one frequency component to another. It is needed because high gain amplification ca be best obtained when an amplifier circuit is designed to amplify only a narrow band of frequencies. Also at radio frequency (which is high frequency) amplification and other processing is somewhat difficult, so it is a good idea to reduce the radio frequency (carrier) wave modulated signal to an intermediate frequency (which is comparatively low frequency) modulated signal that contains the same modulating signal characteristics as the original radio frequency carrier wave. This function can be performed in an electronic circuit by heterodyne action. Basic Principle

A high frequency modulated signal can be converted to a lower frequency signal containing the original modulation characteristics by combining the high frequency modulated signal with a new unmodulated signal. This operation can be performed with one or two transistor. When the process is performed in a single active device, the circuit is called a converter. Separate active devices can be used to:  produce a new unmodulated signal and  combine the original modulated signal with the new unmodulated signal. With this system, the circuit producing the new unmodulated signal is called the local oscillator, and the circuit in which the modulated and unmodulated signals are combined is called the mixer. The process of combining two alternating voltages of different frequency in order to obtain a new value of frequency is called heterodyne action. Principle of Heterodyne Action

Heterodyne action is the result of combining two alternating voltages at different frequencies in a common active device in order to obtain a signal of new frequency value. Heterodyne action produces two additional signal (of a new frequency) whose frequencies are:  the sum of two original frequencies and  the difference of two original frequencies. Generally, only the difference value is used. When the signal waves of two frequencies are combined by heterodyne action, the envelope of the resultant wave will vary its amplitude at the new frequency rate. The range of the amplitude swing of its new voltage is determined by the sum and difference of the two voltages being combined.


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WHCSE BLEX V

Frequency Conversion Using Two Transistors +Vcc

RF Input C4 R1

C5

IF Output L7 Signal

L6

L5

T3

T2

Q2 L4

R2

C2

L2

L3 L1

T1

R3

C3

C1 Q1

Fig: Frequency Conversion Using Two Transistors.

This figure consists of a local oscillator and a mixer to achieve frequency conversion. The local oscillator circuit uses transistor Q1, transformer T1 and capacitor C1. Bias resistor and bypass capacitors have been omitted for clarity. Capacitor C1 and primary winding L1 form a parallel tuned circuit to establish the oscillator frequency. The secondary winding L2 provides the positive feedback voltage required to sustain the oscillations. The secondary winding L3 is used to inject the oscillator signal into the emitter circuit of the mixer transistor Q2. In the mixer circuit R1, R2 and Vcc provides a fixed bias, emitter swapping is provided by R3 and capacitors C2 and C3 bypass the alternating currents around R2 and R3 respectively. The parallel resonant circuit formed by C4 and L4 is tuned to the frequency of RF input signal and the parallel resonant circuit formed by the C5 and L6 is tuned to the intermediate frequency (IF), which the circuit intended to produce. The emitter base voltage of Q2 consists of three components:   

the fixed voltage produced across R2. the RF input signal voltage produced across L5 and the local oscillator voltage produced across L3.

Consequently, the signal current in the collector circuit of Q2 contains the combined effect of both RF input signal and the local oscillator signal. Heterodyne action produces four signal frequencies in the output circuit named:    

the RF input signal frequency. the local oscillator signal frequency. a signal frequency equal to the sum of RF input and local oscillator frequencies. a signal frequency equal to the difference of RF input and local oscillator frequency.

The parallel resonant circuit L6C5 selects the desired IF signal frequency (difference frequency) and couples this signal to the load connected across L7. 51 Prepared By: SriKisna Khadka BLEX 2006 Batch: WHCSE

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Frequency Conversion Using Single Transistors +Vcc

T3 R1

C3

T1 RF Input C 1 Signal

L1

L5

L6

IF Output Signal

T2 L3

L2

C4

L4

Q1 R2 R3

C2

Fig: Frequency Conversion Using One Transistor.

This circuit uses one transistor as a frequency converter. In this circuit R1, R2 and Vcc provides a fixed bias for the transistor, and swapping action is produced by R3 and C2. Positive feedback for oscillator action is provided by the secondary winding L3 of T2 and the oscillator frequency is determined by the parallel resonant circuit L4C4. The desired RF input signal is selected by the tuned circuit L1C1 and is coupled to the base of the transistor by the secondary winding L2. As a result of heterodyne action, four signal frequencies are present in the output circuit of the transistor and the tuned circuit C3L5 selects the one signal frequency to be coupled to the load by the secondary winding L6 of T3. Demodulation The modulated wave consists of modulating signal and carrier signal. The modulating signal is embedded in the carrier wave. The envelope of the modulated wave resembles the modulating signal in case of amplitude modulation. The process of separating the signal and carrier components of a modulated carrier wave is called demodulation or detection. Demodulation of an amplitude modulated wave generally involves two operations.  Rectification of the modulated wave and  Elimination of the RF component of the modulated wave. Demodulation of an FM wave involves three operations.  Converting the frequency changes corresponding to the modulating signal into corresponding amplitude changes.  Rectification of the modulated wave and  Elimination of the RF component of the modulated wave. 52 Prepared By: SriKisna Khadka BLEX 2006 Batch: WHCSE

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AM Detector Detector Action

The average value of a modulated radio wave for one cycle of alternating frequency (AF) wave is zero since, there are equal intensities on both sides (+Ve & -Ve) and therefore the average change of current during the same period is zero. Also, the average change of current of a modulated RF wave will always zero. If the average value is zero then how we obtain the necessary signal? So, if we could eliminate the signal from one of the axis then our problem will be solved. This elimination could be done by the rectification process. After rectifying the modulated signal, only the upper portion of RF wave is passed. The average change in current for each cycle of each wave train will no longer be zero. The changes in current will be similar to the AF signal that modulates the RF carrier wave at transmitter. After rectification, there is still one major problem. The problem is that, the elector mechanical devices used to produce audile sound waves can not respond to the rapid variations in current of an RF wave. It is necessary to remove the RF component of the demodulated AF wave. The modulation envelope formed by joining the peaks of each of the RF cycles, varies in the same manners as the signal impressed upon the RF carrier wave. Envelope Detector

Amplitude Modulated Signla

L1

L2

C2

C1

R

Demodulated Output Signal

Fig: Envelope Detector

When the tuning circuit L2C2 is in resonance with a desired input signal, an RF voltage is developed across the tuned circuit. When the anode of diode is positive, current flows through diode. No current flows through the circuit during the time that the signal voltage makes the anode negative with respect to the cathode and thus the current in R1, will flow only in one direction. During the initial half of the first positive half cycle of the applied RF voltage, C1 charges to the peak value. The applied RF voltage continuing its cycle, then rapidly diminishes to zero. As the RF voltage starts decreasing from its first positive peak value, C1 starts to discharge through R1 but at a very slow rate. The time constant of this RC circuit is very long compared to the short interval required for the RF voltage to change from the first positive peak to the next positive peak. The voltage on the capacitor, therefore will decrease only slightly during this interval. Because of this capacitor action, the voltage on the cathode will be kept more positive than the voltage applied to the anode. When the signal voltage is lower than the voltage charge on C1, no current will flow through the diode. 53 Prepared By: SriKisna Khadka BLEX 2006 Batch: WHCSE

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WHCSE BLEX V

During the positive half of the second RF cycle, current will again flow in the diode when the signal voltage exceeds the voltage at which the charge on the capacitor holds the cathode. The capacitor will then be charged to the peak value of the second positive half cycle this action will be repeated for each succeeding RF cycle, thus causing the voltage across the capacitor to follow the peak values of the applied RF voltage. In this way, the modulating wave is reproduced at the capacitor. SAM (t)

t

t

Amplitude Modulated Wave RAM (t)

t

On Rectification VAM (t)

t

Voltage across R1 and C1 Fig: Envelope Detection of an AM Wave

The voltage across R4 and C1 will be pulsating voltage representing the positive half of the modulated RF voltage. The combination of the diode, C1 and R1 changes the RF signal input voltage to a pulsating voltage. FM Detector Detector Action

A simple method of converting frequency variations to voltage variations makes use of the principle that reactance varies with the frequency. An alternating current, such as an RF or IF signal, flowing through an inductor will remain at a constant value if neither the voltage nor the frequency is varied. The current flowing through an inductor will vary in amplitude when the frequency of the applied signal varies even though the amplitude of the voltage remains constant. The amount of change in the amplitude of the current is dependent upon the amount of shift in frequency. Since, an FM signal varies in frequency above and below the center frequency by an amount depending upon the amplitude of the modulating signal, applying a FM signal to an inductor will convert the frequency deviations to amplitude change in current. These amplitude changes in current when make to flow through a resistor will produce corresponding voltage changes across the terminals of the resistor. The same principle can be illustrated when a capacitor is substituted for an inductor. 54 Prepared By: SriKisna Khadka BLEX 2006 Batch: WHCSE

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WHCSE BLEX V

Voltage

time

Response Curve Low Frequency

High Frequency

Fig: Ideal Response Curve for Frequency Variation

This ideal response curve shows that each frequency variation produces a definite value of voltage and also that a linear relationship exists between the frequency and the voltage. This linear relationship is essential in order to produce distortion less conversion. Foster-Seely Discriminator e4

Cc D1

FM In

L2 C1

e2

L1

C3

R1

e6 e8

L4 L3

C5

C2

e3 e5

e1

C4

R2

Audio Output

e7

D2

e5 Fig: Foster – Seely Discriminator

The two tank circuits [L1C1 and (L2+L3)C2] are tuned exactly to the carrier frequency. The following analysis applies to an unmodulated carrier input:  The carrier voltage e1 appears directly across L4 because Cc and C4 are shorts to the

carrier frequency.  The voltage es across the transformer secondary (L2 in series with L3) is 180o out of

phase with e1 by transformer action. The circulating L2L3C2 tank current, is - is in phase with es since, the tank is resonant.  The current is, flowing through inductance L2L3, produces a voltage drop that is 90o out

of phase with is. The individual components of this voltage, e2 and e3 are thus displaced by 90o from is and are 180o out of phase with each other because they are the voltage from the ends of a center-tapped winding.


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WHCSE BLEX V

 The voltage e4 applied to the diode D1, C3 and R1 network will be the vector sum of e1

and e2. Similarly, the voltage e5 is the sum of e1 and e3. The magnitude of e6 is proportional to e4 while e7 is proportional to e5.  The output voltage, e8 is equal to the sum of e6 and e7 and is zero since, the diodes D1

and D2 will be conducting current equally (since, e4 = e5) but in opposite directions through the R1C3 and R2C4 networks. The discriminator output is zero with no modulation (zero frequency deviation). When the input signal e1 is above the carrier frequency,  Voltages e1 and e5 are as before, but e5 now sees an inductive reactance, because the

tank circuit is above resonance. Therefore, the circulating tank current is lags e5.  The voltages e2 and e3 must remain 90o out of phase with is. The new vector sums of e2+e1 and e3+e1 are no longer equal, so e4 causes a heavier conduction of D1 than exists for D2.  The output, e8, which is the sum of e6 and e7, will go positive since, the current down through R1C3 is greater than the current up through R2C4 (e4 is greater than e5). The

output for frequencies above resonance (fc) is therefore positive. e4

e1

e5

e4

e5 e2

e3

e2

is es

is

es

e3

e4 e2

Fig 1: For f > fc

Fig 1: For f = fc

e5

e1

e1

is

e3

es Fig 1: For f < fc

Fig: Discriminator Phase Relations

When the input signal e1 is below the carrier frequency, the e5 sees a capacitive reactance and therefore is leads e5. Then e5 is greater than e4 and the output e8 is negative. So, the output of frequencies below resonance is negative. Phase Locked Loop (PLL) The PLL is an electronic feedback control system. It consists of phase comparator, lowpass filter and voltage controlled oscillator (VCO). A simple block diagram of PLL control action is shown below. The comparator compares the input signal and the output of the VCO and develops an error signal proportional to the difference between the two. This error signal drives the VCO to change frequency so that the error is reduced to zero. If the VCO frequency equals the input frequency, the PLL achieves lock and the control voltage will be constant for as long as the PLL input frequency remains constant. 56 Prepared By: SriKisna Khadka BLEX 2006 Batch: WHCSE

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Input Frequency (fin)

Phase Comparator or Detector

Output Frequency (fVCO)

Error Signal

VCO Output

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Low Pass FIlter

Voltage Controlled Oscillator (VCO)

Error Voltage

VCO Input

Fig: Phase Locked Loop (PLL) Block Diagram

If the VCO starts to chance frequency, it is in the capture state. It then continues to change frequency until its output is the same frequency as the input. At that point, the PLL is locked; the VCO frequency now equals that of the input signal. The PLL has three possible states operation. 1. Free Running State 2. Capture State and 3. Locked or Tracking State If the input and VCO frequency are two far apart, the PLL free runs at the nominal VCO frequency, which is determined by an external timing capacitor. This is not a normally used mode of operation. If the VCO and input frequency are close enough, the capture process begins and continues until the locked condition is reached. Once tracking (lock) begins, the VCO can remain locked over a wider input-frequency-range variation that was necessary to achieve capture. PLL as FM Demodulator

If the PLL input is an FM signal, the low-pass filter output (error voltage) is the demodulated signal. The modulated FM carrier changes frequency according to the modulating signal. The function of PLL is to hold the VCO frequency in step with this changing carrier. If the carrier frequency increases, for example, the error voltage developed by the phase comparator and the low-pass filter rises to make the VCO frequency rise. Let the carrier frequency fall and the error voltage output drops to decrease the VCO frequency. Thus, we see that the error voltage matches the modulating signal back at the transmitter, the error signal is the demodulated output. The VCO input control signal (demodulated FM) causes the VCO output to match the FM signal applied to the PLL (comparator input).


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Data Conversion Contents: o o o o

Data Conversion: Introduction Digital to Analog Conversion (DAC) Analog to Digital Conversion (ADC) Characteristics of Data Converters


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Data Conversion Introduction The signal generated by natural phenomena re analog in nature. These signals are then processed to extract useful information after which the outputs we get are also analog in nature, then why do we need a signal in digital form ? The reasons are:  The reduction in uncertainty in digitally encoded information. The signal is transmitted either high or low. So, we have to just decide whether the signal is high or low at receiving side. The exact replica of signal is not required. In analog system, great care must be taken to account for electrical noise, influence and drift of amplifier gains, loading effect.  Use of digital computers in the industrial process. They require digitally encoded information. Signal & Its Types

The variation of the dependent parameter with respect to the independent parameter constitute a signal carrying an information. The information carried depends upon the relationship between the parameters. f(t)

t Fig: A Signal with ‘t’ as a Independent Parameter

Above figure show a kind of signal that is varying its magnitude f(t) along Y - direction as a function of (t) which is along X-direction. Here the parameter (t) is considered as independent whereas the f(t) is depends upon the parameter (t). The variation of Current/Voltage against time or Displacement against force etc can be considered for example of such type of signal variation. The concept regarding the process of conversion of an analog signal into digital one and vice versa, the signal can be categorized into following types: 1. 2. 3. 4.

Continuous Time Signal (Analog Signal) Continuous Time Quantized Signal Sampled Data Signal Digital Signal


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1. Continuous Time Signal (Analog Signal)

Analog signals are continuous function of time i.e. they are continuous both in time and value. They may have any value and they may exist at any instant of time i.e. defined over a continuous range of time. Hence, it is a continuous function. In this type of signal the amplitude may be assumed to have a continuous value with time. 2. Continuous Time Quantized Signal

The continuous time signal being represented by a distinct set of value i.e. quantized value is referred as continuous time quantized signal. In this type of signal the amplitude is quantized with discrete value but the time is not being quantized. The range of magnitude is divided into a finite number of intervals which are not necessarily to be equal. f(t)

f(t)

hi

t

t

Fig: Continuous Time Signal (Analog Signal)

Fig: Continuous Time Quantized Signal

f(t)

f(t)

t Fig: Sampled Data Signal (Discrete Time Signal)

t Fig: Digital Signal

3. Sampled Data Signal (Discrete Time Signal)

The signal which is defined at discrete interval of time is known as discrete time signal i.e. one in which independent variable ‘t’ is quantized but magnitude is not. If the amplitude can take a continuous range of value then the signal is called sampled data signal. It can be generated by sampling an analog signal at discrete interval of time. 4. Digital Signal It is the discrete time signal with quantized magnitude. It is the signal quantized in both magnitude and time. The digital signal consists of number of discrete and discontinuous pulses whose time relationship contains information regarding magnitude or the nature of the quantity 60 Prepared By: SriKisna Khadka BLEX 2006 Batch: WHCSE

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Signal Processing

An analog signal may be processed directly by appropriate analog systems such as filters, frequency analyzer or frequency multiplier for the purpose of changing their characteristics or extracting some desired information from them. In such a case we say that the signal is being processed directly in its analog form. Both the input and output are in analog form. Analog Input Signal

Analog Output Signal

Analog Signal Processor

Fig: Analog to Analog Conversion

However, if this analog signal is to be processed digitally, digital signal processing system is employed. This calls for the need of interface between an analog input signal and digital processor. Analog to Digital Converter (ADC) serves the purpose by converting analog signal to digital. The output of ADC is a digital signal that is appropriate for and input to the digital processor. This signal is then processed digitally by the digital processor that is configured to perform a specific set of tasks on input (digital) signal. The output for he digital processor is a digital signal that might require to be provide to the user in analog form. Thus we have to provide an interface between output and analog user, which we say Digital to Analog Converter (DAC). Analog Input Signal

ADC Digital Signal Processor

Analog Output Signal

DAC

Fig: Analog to Analog Conversion

A DAC consists of:  a circuit that generates a reference current.  a circuit that assigns binary weights to the value of the reference current. The circuit can be implemented by either a binary-weighted resistive network or an R-2R ladder.  switches that, under the control of the bits of the input digital word, direct the proper combination of binary-weighted currents to an output summing node, and  an op amp that converts the current sum to an output voltage.


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Resistive Summing Network

Voltage Switches

Registers

Digital Inputs

Digital to Analog Converter (DAC)

Convert Signal

Amp

Analog Ouput

Reference Voltage Source Fig: Block Diagram of Digital to Analog Converter

Register

It is a simple PIPO (Parallel Input Parallel Output) type register. On receiving the external convert signal, the digital number to be converted is fed into the input register of DAC. This input word is latched or stored and remains in the register until another convert command is initiated. Voltage Switches

The output of the register is fed to the voltage switches and depending on the input logic level (0 or 1), voltage switches provide zero volt (ground) or the precision reference voltage (Vref) respectively. Different types of digital controlled SPDT (Single Pole Double Throw) electronic switches are available. One of which is TOTEM POLE MOSFET SWITCH as shown in figure below. Vref

Bit Line

S

Q

R

Q

Q1

Op-amp I/P Line R1

Q2

Fig: TOTEM POLE MOSFET SWITCH

When bit line = ‘1’ (logic high), then S = 1 and R = 0. So that Q = 1 and QC = 0. This drives the transistor Q1 ‘ON’ thus connecting the resister R1 to the reference voltage, Vref. Whereas the transistor Q2 remains off. Similarly a ‘0’(logic low) at the bit line connects the R1 to the ground terminal. 62 Prepared By: SriKisna Khadka BLEX 2006 Batch: WHCSE

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Resistive Summing Network

In resistor summing network, transistors act as switches as shown in figure below. B3(MSB)

B2

B1

B0(LSB)

Vref 21R

2 0R

22R

23R

R1 I3

I2

I1

I0

Itot -

Fig: Resistive Summing Network

+

From above summing network, we can calculate the total output current. Where, 𝐢𝐭𝐨𝐭 = 𝐢𝟎 + 𝐢𝟏 + 𝐢𝟐 + 𝐢𝟑 i.e.

𝐢𝐭𝐨𝐭 =

𝐕𝐫𝐞𝐟 𝐁𝟎 𝐑

(

𝟐𝟑

+

𝐁𝟏 𝟐𝟐

+

𝐁𝟐 𝟐𝟏

+

𝐁𝟑 𝟐𝟎

)

(Where, Bi, i = 0,1,2,3; are the position of switches i.e. 1 for ‘ON’ and 0 for ‘OFF’ condition.)



𝐕𝐨 = −𝐢𝐭𝐨𝐭 × 𝐑 𝟏

To make Vo positive Vref should be taken as negative. Thus voltage switches feed to the summing network that converts each bit into its weighted current value and then sums them for total current. Amplifier

Now, the total current is fed to the amplifier to performs mainly two functions.  Current to voltage conversion.  Output scaling or amplification to desired value by changing the value of R.  NOTE

In practical DAC circuits, the resistive network, called DAC module is connected to a flip flop register which holds the digital number. As the divider is simply a passive network, the digital input voltage (the on and off levels) determines the output voltage. Because digital voltage levels are usually not as precise as required in an analog system, level amplifiers may be placed between the flip flop register and the divider network. This amplifiers switch the inputs to the divider network between ground and a reference voltage supplied by a precision reference source. The analog output voltage then falls between these two levels. 63 Prepared By: SriKisna Khadka BLEX 2006 Batch: WHCSE

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DAC with Binary Weighted Resistor Network In practice, the analog to digital conversion techniques use DAC for functioning. Therefore, we start with discussion on DAC first. It is used as the basis of some A/D converters but they have a large important uses in their own right. They are used in computer driven CRT displays, digital generation of analog waveforms and digital control of automatic process control system. The voltage output of an n-bit DAC is: 𝐕𝐎 = (𝐁𝐧−𝟏 𝟐𝐧−𝟏 + 𝐁𝐧−𝟐 𝟐𝐧−𝟐 + ⋯ + 𝐁𝟏 𝟐𝟏 + 𝐁𝟎 𝟐𝟎 )𝐕𝐫𝐞𝐟 Where, 𝐃 = (𝐁𝐧−𝟏 𝟐𝐧−𝟏 + 𝐁𝐧−𝟐 𝟐𝐧−𝟐 + ⋯ + 𝐁𝟏 𝟐𝟏 + 𝐁𝟎 𝟐𝟎 ), Bn−1 = MSB & B0 = LSB For n=3, 𝐃 = 𝐁𝟐 𝟐𝟐 + 𝐁𝟏 𝟐𝟏 + 𝐁𝟎 𝟐𝟎

(MSB) Bn-1 L O G I C I N P U T S

Bn-2

20R

Sn-1

Precision Reference Supply (-Vref) I3=I/20

Rf

1

2R

Sn-2

I2=I/21

Itot

-

Itot Vout

+ B1

(LSB) B0

S1 S0

2

n-2

R

2n-1R

Analog O/P

I2=I/2n-2 I2=I/2n-1

Fig: Binary Weighted Resistor Network DAC

For n-bit, the circuit consists of n number of binary weighted resistors such as R, 2R, 4R… 2n-1R and n number of SPDT switches Sn-1, Sn-2 … S1, S0 and an op-amp together with a feedback resistor Rf, which acts as current to voltage converter or summing amplifier. For the sake of simplicity, we have just taken a 3-bit converter. When 1 is present on MSB line, switch S3 connects Vref to resistor R and conversely when 0 is present on MSB line, switch S3 connects R to ground. It is also known as unipolar DAC because it always produces positive output voltage for any bit combination. Expression for Output Voltage

Let Bn-1(MSB) is at logic_1 and all other bits are at logic_0. Since Sn-1 connects -Vref to R, so current flowing through R is (-Vref/R) whereas no current flows through other resistors as they are connected to ground directly and virtually through op-amp. VO(MSB) = -(-Vref/R)Rf If NMSB is at logic_1 and all other bits are at logic_0, then VO(NMSB) = -(-Vref/2R)Rf 64 Prepared By: SriKisna Khadka BLEX 2006 Batch: WHCSE

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Similarly, when B0(LSB) is at logic_1 and all other bits are at logic_0. VO(LSB) = -(-Vref/2n-1R)Rf Finally, the output voltage is given by: 𝐕𝐨 = −𝐢𝐭𝐨𝐭 × 𝐑 𝐟 𝐕 𝐕 = ( 𝐫𝐞𝐟 𝐑 𝐟 𝐒𝐧−𝟏 + 𝐫𝐞𝐟 𝐑 𝐟 𝐒𝐧−𝟐 + ⋯ + 𝐑

= = VO =

𝐕𝐫𝐞𝐟 𝐑 𝐕𝐫𝐞𝐟

𝟐𝐑

𝟏

𝐑 𝐟 ( 𝟎 𝐒𝐧−𝟏 + 𝟐 𝟏

𝐑 𝐟 𝐧−𝟏 (𝟐 𝐑 𝟐 𝐕𝐫𝐞𝐟 𝐑 𝐟 𝐃 𝟐𝐧−𝟏 𝐑

𝟏

𝟐𝟏

𝐧−𝟏

𝐒𝐧−𝟐 + ⋯ +

𝐕𝐫𝐞𝐟 𝐑𝐧−𝟐 𝟏

𝟐𝐧−𝟐

𝐑 𝐟 𝐒𝟏 +

𝐒𝟏 +

𝟏 𝟐𝐧−𝟏 𝟏

𝐕𝐫𝐞𝐟 𝐑𝐧−𝟏

𝐑 𝐟 𝐒𝟎

𝐒𝟎 )

𝐒𝐧−𝟏 + 𝟐𝐧−𝟐 𝐒𝐧−𝟐 + ⋯ + 𝟐 𝐒𝟏 + 𝟐𝟎 𝐒𝟎 )

Where, D = Decimal equivalent of input bits, e.g. for 0110, D = 0+4+2+0 = 6. Resolution of DAC

It is the weight o LSB. It is also an increment in each step of bit combination. 𝐕𝐫𝐞𝐟 𝐑 𝐟  Resolution = 𝐧−𝟏 𝟐 𝐑 Hence, we have, 𝐕𝐫𝐞𝐟 𝐑 𝐟 Vo(LSB) = 𝐧−𝟏 and 𝟐

Vo(MSB) = 𝐕𝐫𝐞𝐟

𝐑 𝐑𝐟 𝐑

 Vo(MSB) = 𝟐𝐧−𝟏 Vo(LSB) Full Scale Voltage (VFS)

This is the output voltage when all input bits are at high logic level (1). This is the maximum output voltage. 𝐕 𝟏  VFS = Vo(max) = 𝐫𝐞𝐟 𝐑 𝐟 𝐧−𝟏 (𝟐𝐧−𝟏 + 𝟐𝐧−𝟐 + ⋯ + 𝟐𝟏 + 𝟐𝟎 ) 𝐑 𝟐 i.e. VFS = Vo(LSB)(2n-1) Output Waveform

Let input digital word length, n = 3, Vref = 5V and let R = 2Rf, then 𝐕𝐫𝐞𝐟 𝐑 𝐟 𝟓 VO = 𝐧−𝟏 𝐃 = 𝐃 = (𝐁𝟐 𝟐𝟐 + 𝐁𝟏 𝟐𝟏 + 𝐁𝟎 𝟐𝟎 ) 𝟐 𝐑 𝟖 Now, the output voltage for different bit combinations will result the following waveform. Analog Output 35/8 30/8 25/8 20/8 15/8 10/8 5/8 000

001

010

011

100

101

110

Digital Input 111

Fig: Output Waveform


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Disadvantages & Limitation

 Requirement of wide range of resistors.  If n > 4, exactly twice the value of resistor can not be obtained.  For better resolution, n has to be increased. But, as n increases the range of resistance values also increases.  Vref should be stable and constant.  The switches are in series with resistor and therefore their resistance must be vary small which can be achieved by using MOSFET switch. Conclusion

Thus depending whether switches are open or closed, the binary weighted current will set up in the input resistance, the sum of these currents is equal to current that is flowing through Rf which is converted to proportional output voltage. Bipolar Digital to Analog Converter Since, the uni-polar DAC always produces positive output voltage for any bit combination, so to overcome this problem a bi-polar DAC is introduced that produces positive as well as negative voltage for given bit combination. Sn-1

(MSB) Bn-1 L O G I C I N P U T S

Sn-2

Bn-2

20R

Precision Reference Supply (-Vref) I3=I/2

0

Rf

1

2R

I2=I/21

Itot

-

Itot

Vo + S1

B1

S0

(LSB) B0

+vref

2n-2R 2n-1R

I2=I/2

n-2

I2=I/2n-1

R

S Fig: Bipolar Digital to Analog Converter

When switch S is at low, the circuit is exactly the binary weighted resister network DAC. If the switch S is at high, the output voltage ranges from -Vref to +Vref(approx) and hence the circuit is called bi-polar digital to analog converter.


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Expression for output voltage

𝐕𝐎 = 𝐕𝐎 = 𝐕𝐎 =

𝐕𝐫𝐞𝐟

𝟏 𝟏 𝟏 { 𝐒 + 𝟏 𝐒𝐧−𝟐 + ⋯ + 𝐧−𝟐 𝐒𝟏 𝐑 𝟐𝟎 𝐧−𝟏 𝟐 𝟐 𝐕𝐫𝐞𝐟 𝐑 𝐟 (𝟐𝐧−𝟏 𝐒𝐧−𝟏 + 𝟐𝐧−𝟐 𝐒𝐧−𝟐 + ⋯ + 𝟐𝐧−𝟏 𝐑 𝐕𝐫𝐞𝐟 𝐑 𝐟 𝐕𝐫𝐞𝐟 𝐑 𝐟 𝟐𝐧−𝟏 𝐑

𝐃−

𝟏 𝐕 𝐒 )𝐑 𝐟 + (− 𝐫𝐞𝐟 𝐑 𝐟 )} 𝟐𝐧−𝟏 𝟎 𝐑 𝐕𝐫𝐞𝐟 𝐑 𝐟 𝟏 𝟎 𝟐 𝐒 𝟏 + 𝟐 𝐒𝟎 ) − 𝐑

+

𝐑

Where, D = Decimal equivalent of input bits. Cases 1. When all the input bits are @ logic_0 i.e. D=0 Then, Vo = 0 – Vref × (Rf/R) = - Vref × (Rf/R) 2. When MSB is @ logic_1 and all other input bits are @ logic_0 i.e. D=2n-1 Then, Vo = (Vref/2n-1) × (Rf/R).2n-1 - Vref × (Rf/R) = Vref × (Rf/R) - Vref × (Rf/R) = 0 3. When all the input bits are @ logic_1 i.e. D=2n-1 Then, Vo = Vref/2n-1 × (Rf/R)(2n-1) - Vref × (Rf/R) = Vref/(2n-1) × (Rf/R)2n - Vref/(2n-1) × (Rf/R) - Vref × (Rf/R) = 2Vref × (Rf/R) – Vo(LSB) - Vref × (Rf/R) = Vref × (Rf/R) – Vo(LSB)  Vo ≈ Vref × (Rf/R) Conclusion

The bit combination:

000…0 represents 100…0 represents 111…1 represents

-Vref 0V +Vref (approx.)

So, the output voltage ranges from –Vref to +Vref.


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R-2R Ladder Network DAC (Voltage Mode) A DAC using R-2R ladder network with 4-input voltages, representing 4-bits of digital data and dc voltage output is illustrated in the figure below. 2R

R VO

R

2R

R

2R

R

2R

Va

2R

2R

+ 2R

Vref

(LSB) B0

B1

B2

B3 (MSB)

Fig: R-2R Ladder Network DAC (Voltage Mode)

 This circuit used only two values of resistors.  The ladder in this circuit is current splitting device.  Resistance looking to the left or to the right from only of the ladder nodes is 2R. Hence, current will split equally towards the left and right and this happens at every node. This gives rise to binary weighted sequence of current. Cases 1. B3(MSB) @ logic_1 and all other bits @ logic_0.

Now the circuit arrangement for this case is illustrated and analyzed as follows. 2R

R

VO

R

2R

R

2R

R

2R

Va

2R

2R

+

2R

Vref

2R

R

VO

2R

I/2 I/2

Va

+

I

2R

2R

Vref Fig: R-2R Ladder Network DAC, When MSB(B3) is @ logic_1 & All Other Bits are @ Logic_0.


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From above circuit analysis, we get, I = Vref/3R and Va = (I/2).2R = Vref/3. As, Vo = (1+R/2R)Va = (3R/2R).(Vref/3) = Vref/2 Hence, Weight of MSB = Vref/2 2. B2(NMSB) @ logic_1 and all other bits @ logic_0. 2R

R

R

2R

R

2R

R

2R

Va

2R

2R

VO

+

2R

Vref

2R

R

2R

I/2 I/2

2R

Va I/4

I

2R

I/4

2R

VO

+

2R

Vref Fig: R-2R Ladder Network DAC, When NMSB(B2) is @ logic_1 & All Other Bits are @ Logic_0.

From the circuit analysis as depicted in above, we get, I = Vref/3R and Va = (I/4).2R = Vref/6. As, Vo = (1+R/2R)Va = (3R/2R).(Vref/6) = Vref/4 Hence, Weight of NMSB = Vref/4 Similarly, Vo(LSB) = Vref/2n Finally, the output voltage can be expressed as: VO = = VO =

𝐕𝐫𝐞𝐟 𝐒𝐧−𝟏 𝟐 𝐕𝐫𝐞𝐟 𝟐𝐧 𝐕𝐫𝐞𝐟 𝟐𝐧

+

𝐕𝐫𝐞𝐟 𝟐

𝟐

𝐒𝐧−𝟐 + ⋯ +

𝐕𝐫𝐞𝐟 𝟐

𝐧−𝟏

𝐒𝟏 +

𝐕𝐫𝐞𝐟 𝐒 ) 𝟐𝐧 𝟎

(𝟐𝐧−𝟏 𝐒𝐧−𝟏 + 𝟐𝐧−𝟐 𝐒𝐧−𝟐 + ⋯ + 𝟐𝟏 𝐒𝟏 + 𝟐𝟎 𝐒𝟎 ) 𝐃

Hence we found that, Vo(LSB) = Vref/2n and Vo(MSB = Vref/2n-1 Therefore, Vo(MSB) = 2n-1Vo(LSB) Advantage & Disadvantages

 It uses only two values of resistors i.e. R and 2R.  But, it requires more resistors and it is difficult to analyze than binary weighted resistor network, and  For n > 4, the circuit becomes more complex and can result more error.


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R-2R Ladder Network DAC (Current Mode) It is also known as inverted R-2R ladder type DAC. Let us consider 4-bit DAC. In this type, the current flowing through the resistors is constant for any input data. Here, the switches do not change the amount of current flowing through the resistors but direct the current to the inverting input terminal of the op-amp (which is virtually grounded) or to the ground directly. When input bit is zero, the corresponding switch directs the current directly to the ground and for input bit of 1, the switch directs the current to the inverting terminal. The summation of currents directed by switches to the inverting terminal occurs and the total current flows through the feedback resistor to provide the corresponding analog voltage. Vref

I

R

R

R

I/2

I/4

I/8

2R I/2

2R

2R I/4

I/16

I/8

I/16

2R

2R

Rf VO (MSB) S3

S2

S1

S0 (LSB)

+

Fig: R-2R Ladder Network DAC (Current Mode)

Calculating the equivalent resistance of the network, it is found to be R. So, the current provided by the reference voltage is: I = Vref/R. The equivalent resistance right to each node is 2R. So, the current flowing through 2R ladder of node 1 is: I1 = Vref/2R = I/2. Similarly, for node 2, 3 & 4, the respective currents are: I2 = I/4, I3 = I/8 and I4 = I/16. Since, the current flowing though the resistances are constant and independent of switch position, the ladder node voltage remain constant at Vref, Vref/2, Vref/4 and Vref/8 for 4-bit DAC and Vref, Vref/2, Vref/22 … Vref/2n-1 for n-bit DAC. Cases 1. When MSB is @ logic_1 and all other bits are @ logic_0. Then, Itot = I/2 = Vref/2R 2. When NMSB is @ logic_1 and all other bits are @ logic_0. Then, Itot = I/4 = Vref/4R 3. Similarly, when LSB is @ logic_1 and all other bits are @ logic_0 Then, Itot = I/2n = Vref/2nR


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WHCSE BLEX V

In General 𝐕𝐫𝐞𝐟

Itot = i.e. Itot =

𝐕 𝐕𝐫𝐞𝐟 𝐕 𝐒 + 𝐫𝐞𝐟 𝐒 + ⋯ + 𝐧−𝟏 𝐒 + 𝐫𝐞𝐟 𝐒 𝟐𝐑 𝐧−𝟏 𝟐𝟐 𝐑 𝐧−𝟐 𝟐 𝐑 𝟏 𝟐𝐧 𝐑 𝟎 𝐕𝐫𝐞𝐟 (𝟐𝐧−𝟏 𝐒𝐧−𝟏 + 𝟐𝐧−𝟐 𝐒𝐧−𝟐 + ⋯ + 𝟐𝟏 𝐒𝟏 + 𝟐𝟎 𝐒𝟎 ) 𝟐𝐧 𝐑

And, finally the output voltage is thus given as: 𝐕𝐎 = −𝐈𝐭𝐨𝐭 × 𝐑 𝐟 𝐕𝐫𝐞𝐟 (𝟐𝐧−𝟏 𝐒𝐧−𝟏 𝟐𝐧 𝐑 𝐕 − 𝐧𝐫𝐞𝐟 𝐑 𝐟 𝐃 𝟐 𝐑

𝐕𝐎 = − 𝐕𝐎 =

+ 𝟐𝐧−𝟐 𝐒𝐧−𝟐 + ⋯ + 𝟐𝟏 𝐒𝟏 + 𝟐𝟎 𝐒𝟎 ) × 𝐑 𝐟

Where, D = Decimal equivalent of input bits. Advantages

 In binary weighted resistor network DAC and R-2R ladder network DAC (Voltage Mode), the current flowing in the resistor changes as the input data changes, therefore more power dissipation causes heating that in turn creates non linearity in DAC. This problem is solved by the R-2R ladder network DAC in current mode because of the constant current.  Because of the constant voltages at nodes even in the change in the input binary code, the stray capacitances are not involved to produce slow down effects on the performance of the circuit. Analog to Digital Converter (ADC) The process of changing an analog signal to an equivalent digital signal is accomplished with the help of an analog-to-digital converter (ADC). It is used to convert an analog signal from a transducer into an equivalent digital signal. Measuring some physical quantity such as temperature, pressure, position, rotational speed, or flow rate etc are usually found in analog form and they need to convert in digital form for the sake of simplicity. ADC is often referred to as an encoding device, as it is employed for encoding signals for entry into a digital system. The A/D conversion is a process of converting an analog input voltage into an equivalent digital signal. Hence the maximum permissible rate of change of analog voltage and maximum permissible frequency of analog voltage should be fed to ADC. Let we have: 𝐕 = 𝐕𝐦 𝐬𝐢𝐧(𝛚𝐭) 𝐝 Then: 𝐕 = 𝛚𝐕𝐦 𝐜𝐨𝐬(𝛚𝐭) 𝐝𝐭

So, for t→ 𝟎,

𝐝 𝐝𝐭

𝐕|𝐦𝐚𝐱 = 𝛚𝐕𝐦 = 𝟐𝛑𝐟𝐕𝐦

If Vmax is full scale range of converter and Tcon be the conversion time of ADC then for the error, we have no more than one LSB. 𝐝 𝐕 Then: 𝐕|𝐦𝐚𝐱 ≤ 𝐧𝐦𝐚𝐱 𝐝𝐭

i.e. 𝟐𝛑𝐟𝐕𝐦 ≤

𝟐 𝐓𝐜𝐨𝐧 𝐕𝐦𝐚𝐱

𝟐𝐧 𝐓𝐜𝐨𝐧

Now, For 𝐕𝐦 = 𝐕𝐦𝐚𝐱 , 𝐟 ≤ F

𝟏 𝟐𝐧+𝟏 𝛑𝐓𝐜𝐨𝐧


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Sampling

The operation that transforms continuous time signal into discrete time signal is known as the sampling process. The main purpose of signal sampling is efficient use of data processing and data transmission unit. In sampling process, the continuous time signal is multiplied by a train of pulse of unit magnitude. Once the continuous time signal is converted into discrete time signal, there is no record of what the signal was doing in between the sample points. For sufficiently low frequency, signal can be assumed that missing data falls on straight lines between two known sample points.

Analog Signal

Unit Train Pulse

Discrete Signal

Fig: Sampling of Analog Signal with Unit Train Pulse

In order not to lose the identity of the continuous time signal, when it is sampled, the sampling theorem states that, “If the highest frequency content in the input signal is fn in Hz, then the input signal can be recovered without distortion, if it is sampled at the rate of 2fn sample per second.” This rate is known as Nyquiest Rate, i.e.; fs ≥ 2fn. If the sampling

frequency is smaller compared to frequency of input signal then the reconstructed signal wave form is different than the original signal. Sample & Hold Circuit

Vin

-

-

Amp 2

Amp 1

+

+

CH Sampler

Vout Analog Input

Input & Output SIgnal

A sampler is a digital system which converts a continuous time signal into a discrete time signal. The hold circuit holds the value of sampled pulse over a specified period of time. Sample and hold circuit is necessary in ADC to produce a number that accurately represents the input signal at the sampling instant.

Input Signal

Hold Drop Sample & Hold Offset

Output Signal

Aperture Time Time

Sample & Hold Command

Tracking Mode

Hold Mode

Hold Command is Given Here

Fig: Sample & Hold Circuit

Fig: Tracking & Holding Mode

Above figure shows the simplified diagram of the S/H circuit. The S/H circuit is analog circuit in which an input voltage is acquired and then stored on a high quality capacitor with low leakage and low dielectric absorption characteristics. An electronic switch is connected to the hold capacitor. Operational amplifier 1 is an input buffer amplifier with a high input impedance. Operational amplifier 2 is the output amplifier, which buffers the voltage on the hold capacitor. 72 Prepared By: SriKisna Khadka BLEX 2006 Batch: WHCSE

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When the switch is closed, the capacitor charges up to the average level of the input signal that means the charge on the capacitor in the circuit tracks the input voltage. This mode of operation is known as Tracking Mode. When the switch is open, the capacitor starts to discharge very slowly through the stray leakage, hence the capacitor voltage holds constant for a specified time period and this operation mode is known as Hold Mode. In fact, the switching from the tracking mode to the hold mode is not instantaneous. When the hold command is given while the circuit is in the tracking mode, then the circuit will stay in tracking mode for a short while before reacting to the hold command. The time interval during which the switching takes place is called the Aperture Time. The output voltage during the hold mode may decrease slightly. The hold mode droop may be reduced by using a high-input-impedance output buffer amplifier. Such an output buffer amplifier must have very low bias current. The S/H operation is controlled by a periodic clock. Quantization

The main functions involved in ADC are sampling, holding, quantizing and coding. When the value of any sampled signals falls between two permitted output states, it must be road on the permitted state nearest the actual value of the input signal. The process of representing a continuous or analog signal by finite number of discrete state is called quantization. The standard number system used for processing the digital signal is binary number system. In this system, the code group consists of n-pulses, each indicating 0 or 1. The quantization level (Q) is the range between adjacent decision points 𝐅𝐮𝐥𝐥 𝐒𝐜𝐚𝐥𝐞 𝐑𝐚𝐧𝐠𝐞 and is given by: 𝐐 = , Where LSB of digital signal is quantization level. 𝐧 𝟐

v +Q/2

0 Q t Fig: Quantization Level

-Q/2 Fig: Quantization Error

Quantization Error:

When the input to the quanitzer is moved through its full scale range and subtracted from the discrete output levels, the error signal is obtained as shown in figure known as quantization error. The rms value of quantization error is given by: Eq = Q/2√3. Quantization error is due to the fact that bits in the digital world are finite. ADC results in finite resolution the analog signal must be rounded off to a quantization level. The error varies from 0 to ±Q/2; no matter how many bits are used there is always some quantization error in ADC. Aperture Time:

In order to perform the operation of quantizing and coding a signal, and A/D converter requires an aperture time. The use of a sample and hold circuit provides a very small time for taking a very rapid sample of signal and then holding its value till it is converted. 73 Prepared By: SriKisna Khadka BLEX 2006 Batch: WHCSE

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The device that converts the analog signal into digital form is called analog to digital converter (ADC). The functional block diagram of ADC is given below. Vref

Analog Input Voltage

ADC

START

EOC

Fig: Functional Block Diagram of Analog to Digital Converter (ADC)

It converts an analog signal (Va) into digital output (Sn-1, Sn-2, … S1, S0). ADC has two additional control lines: the ‘START’ input signal tells the ADC when to start the conversion and ‘EOC’ (End of Conversion) output signal tells when the conversion is complete. Count-Up Type ADC/Stair Case Ramp Type ADC The count up type ADC consists of binary up counter, DAC, comparator and control gates which are depicted in following diagram. EOC2 EOC 1

G2

S0

EOC 2

EOC

Sn-1 Reset Va Binary Up Counter

G1

START

S0(LSB) S0

Analog I/P

Comparator

+ -

Vmax

Sn-2 Sn-1(MSB)

EOC1

O/P of DAC, Vd

Digital O/P

CLOCK

Vmin VO

n-bit DAC

Fig: Count Up Type ADC/Stair Case Ramp Type ADC

Let Vmax= 7V & n = 3 for DAC. Then maximum output t voltage for bit combination 111 is +7V

t Fig: Counting Up To Analog Input

At the start of conversion, the reset signal resets the counter to zero. The ‘START’ signal is also enabled. The gate (G2) gives out the high signal and the comparator produces logic_1 when Va > Vd. So, the clock pulses pass through the gate (G1) and they are counted by the counter. For each count, the binary word produced by the counter is converted into the corresponding analog voltage (Vd) by DAC and is compared with the analog input voltage. If Va is still greater than Vd, then the counter continues to count the clock pulse. When VaVd, the output of comparator is low and ‘AND’ gate is disabled. So, the clock pulses stop to reach the counter. The output binary word (digital output) of the counter at this stage approximate digital output of analog input signal. The ‘EOC’ signal indicates the end of conversion for a particular value of Va. For a new value of analog input Va, a second reset pulse or ‘START’ pulse is applied and counting then begins again.


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If the analog input varies with time, the input signal must be sampled using a sample and hold circuit before it is applied to the comparator. For n-bit converter the number of clock pulses required to represent the maximum value of analog voltage is (2n-1). If the clock period is ‘T’ seconds, the maximum delay in this type of ADC is (2n-1)T. Also, the frequency (or clock frequency) must be low enough to give sufficient time for DAC to settle and for the comparator to respond. This limits the speed of operation of ADC. Advantage & Disadvantages

   

It is simple in operation and circuitry, But: Its conversion speed is very low. It can not convert continuously varying input voltage. It can have an error of one LSB

Tracking/Servo Type ADC It is an improved version of count up type ADC. The circuit consists of up-down counter with the comparator controlling the direction of the count. The analog output of DAC is Vd and compared with analog input Va. If Va > Vd, the output of comparator goes high and the counter is caused to count up. The DAC output increases with each incoming clock pulse and when it becomes more than Va, the counter reverses the direction and count down (but only by one count LSB). But if Vd becomes less than Va, it causes to count up by 1 LSB. Reset CLOCK

Comparator

S0(LSB) S0 Sn-2 Sn-1(MSB)

+

VO

Digital O/P

Analog I/P, Va

UP Binary Down Counter

-

O/P of DAC, Vd

n-bit DAC

t Fig: Tracking The Analog Input

Fig: Count Up Type ADC/Stair Case Ramp Type ADC

Advantage & Disadvantages

 It tracks the output value and the up-down counter continues from the last stopped value, so it is faster. But  There can be various types of error as: o Start Up Error: At the time when ADC is operated, there is certain analog input value so, there is incorrect output for certain time until DAC output reaches close to the value of input. Such error, which exists at the start up is termed as start up error. o Granular Error: When input voltage is nearly constant. (i.e. when slope is small) then there exists a fluctuation in binary output. This shows that there is an error, which lies between 0 to 1 LSB. Such error is termed as granular error. o Over Slope Error: If the input voltage exhibits high slope, then the binary output can not track the input voltage, resulting an error called over slope error.


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Successive Approximation Type ADC This is one of the most widely used methods of A/D conversion. Though it has complex circuitry, it has much shorter conversion time. This type of ADC makes direct comparison between an unknown input signal and a reference signal. The basic arrangement of a successive approximation ADC is shown in figure below. It can be employed at conversion speeds of up to about 1,00,000 samples per second at resolution of up to 16-bits. Start Clear All Bits Start at MSB

Clock

Set Bit = 1

Analog I/P, Va

Comparator

O/P of DAC, Vd

EOC

S0 S0 Sn-2 Sn-1(MSB)

+ -

START

Digital O/P

Control Logic & Control Register

If Vb > Va

Go to Next Bit

Yes

Clear Bit to 0

No

MSB n-bit LSB DAC

No

Fig: Successive Approximation Type ADC

Have All Bits Been Checked Yes Conversion Finished, Number in Register

Fig: Flow Diagram

STOP

Working Principle

A generalized block diagram and flow chart of successive approximation ADC are shown in above figure.  First of all, both the control and the distribution register are set with 1 in the MSB and 0 in all bits.  Distribution register indicates the starting of a cycle in first stage.  The control register shows 1000, which causes an output voltage at the DAC one half of the reference supply.  At the same time, a pulse enters the time delay circuitry.  By the time that the DAC and Comparator have settled, this delayed pulse is gated with the comparator output.  When the next MSB is set in control register, the MSB remains in 1 state or it is reset to 0 depending upon the comparator output.  The procedure repeats itself until the final approximation has been corrected and the distribution register indicates the end of the conversion. 76 Prepared By: SriKisna Khadka BLEX 2006 Batch: WHCSE

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Example Let us consider an example with following parameters of successive approximation type ADC. DAC: n = 4-bit, Vref = 16V, Step Size = 1V, Va = 10.4V

Steps: At the start of conversion, the register output is 0000. So, Vd = 0V and Va > Vd. The comparator output is high. Step 1: The control sets MSB(S3) high. The register output is now 1000. i.e. Vd = Vref/2 = 8V. Since, Va > Vd, the control keeps S3 = 1. Step 2: On next clock cycle, control sets NMSB(S2) high and the resulting register output is 1100, i.e. Vd = Vref/2 + Vref/4 = 8 + 4 = 12V. Since, Va < Vd, the control resets S2 low and the register output is again 1000. Step 3: On next clock cycle, the control sets S1 high and the register output is 1010. i.e. Vd = Vref/2 + 0 + Vref/8 = 8 + 0 + 2 = 10V. Since, Va > Vd, the control keeps S1 high and the register output is 1010. Step 3: The control sets LSB(S0) high and the register output becomes 1011. i.e. Vd = Vref/2 + 0 + Vref/8 + Vref/16 = 8 + 0 + 2 + 1 = 11V. Since, Va < Vd, the control makes S0 = 0 and the resulting register output is again 1010. Hence, the final digital output for analog input voltage Va is 1010. This example clearly illustrates the conversion process of Successive Approximation Type ADC. In this process, the control logic goes to each register bit, sets it to 1 and decides whether to keep it at 1 or reset it to 0 and then goes to the next bit. The processing of each bit takes just one cycle. Therefore, the total conversion time foe n-bit converter is only ‘n’ clock cycles. The conversion time is the same irrespective of the analog input value since the control logic has to test each bit to see if logic ‘1’ or ‘0’ is needed. Disadvantages

 It is more complex and hence expensive.  The input voltage must remain constant during the conversion time. So, it requires sample and hold circuit prior to conversion.


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Flash Type ADC (Simultaneous ADC) The flash type ADC is the fastest ADC that utilizes comparators to compare input analog voltage with the reference voltage. An encoder is used to convert the output of comparators into the digital output. For ‘n-bit’ ADC, 2n-1 comparators are required. So this is very expensive. 8v=Vref

Va Thermometric Code

R 7v=V7 R 6v=V6 R 5v=V5 R 4v=V4 R 3v=V3 R 2v=V2 R 1v=V1 R

+ + + + +

E N C O D E R L O G I C

S0

S1

Digital Output

S2

+ +

Fig: Flash Type ADC

If Vref = 8V, then V1 = 1V, V2 = 2V, V3 = 3V, V4 = 4V, V5 = 5V, V6 = 6V & V7 = 7V. For 0 < Va < 1, output is 000, for 1 < Va < 2, output is 001 and Similarly, for 7 < Va, output is 111. The resistor net and comparators provide an input to the combinational logic circuit, so the conversion time is just the propagation delay through the network. It is not limited by the clock rate or some convergence sequence. Though, it is the fastest type of ADC available but requires a comparator for each value of output (63 for 6-bit, 255 for 8-bit etc). Such ADCs are available in IC form up to 8-bit and 10-bit flash ADCs. The encoder logic executes a truth table to convert the ladder of inputs to the binary number output. Advantages & Disadvantages

   

It is very fast. No clocks are required. Complexity of logic doubles for each additional bit. For large number of comparators, the heat generated would be excessive to hold all of them in a single chip.  For higher ‘n’, large number of comparators and logic elements (encoders) are required.  It is very expensive. 78 Prepared By: SriKisna Khadka BLEX 2006 Batch: WHCSE

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Dual Slope ADC The analog voltage to be converted into a digital signal is applied through an electronic switch to an integrator or ramp generator circuit, which essentially provides a constant current for charging a capacitor to give a linear-ramp voltage. The counter operated during both positive and negative slope intervals to the integrator gives the digital output Switch Control Va

V1

C

Fixed Interval T1

Control Logic

R

0

Comparator

-

V1

+

-Vref

Variable Interval (T2)

Binary Counter

+

Variable Slope = Va/RC

Integrator

t Fixed Slope = Vref/RC Phase I

Phase II

Clock Sn-1 Sn-2 S0 Fig I : Dual Slop ADC

Fig II : Characteristics Curve

The conversion cycle begins with connecting the integrator input through switch to the analog input signal. A current I = Va/R will flow through R and charges the capacitor for a 𝟏 𝐓 𝟏 𝐓 𝐕 𝐕 fixed time interval T1. Since, 𝐕𝟏 = − ∫𝟎 𝟏 𝐈𝐝𝐭 = − ∫𝟎 𝟏 𝐚 𝐝𝐭 = − 𝐚 𝐓𝟏 . Thus, V1 rises 𝐂 𝐂 𝐑 𝐑𝐂 (downward) linearly with a slope of –Va/RC as shown in the figure. Simultaneously, the counter is enabled and it counts the pulses from a fixed frequency clock. This phase of conversion process continues for a fixed duration T1. It ends when the counter has accumulated a fixed count 2n for n-bit converter. At the end of this phase, the counter is reset to zero. Phase II of the conversion begins at t = T1 by connecting the integrator input through

switch to the negative reference voltage -Vref. The current reverses the direction and is equal to –Vref/R. It discharges the capacitor and V1 (magnitude) decreases linearly with a slope of Vref/RC. Simultaneously, the counter is enabled and it counts the pulses from the fixed frequency clock. When V1 reaches zero volt, the comparator signals the control logic to stop the counter. Thus the content of the counter at the end of the conversion process is the digital equivalent of Va. Charge stored on capacitor during period T1 = Charge removed from capacitor during period T2

i.e. 𝐐𝐓𝟏 = 𝐐𝐓𝟐 i.e. 𝐈𝟏 𝐓𝟏 = 𝐈𝟐 𝐓𝟐 𝐕 𝐕 i.e. 𝐚 𝐓𝟏 = 𝐫𝐞𝐟 𝐓𝟐 𝐑

i.e. 𝐓𝟐 =

𝐕𝐚 𝐕𝐫𝐞𝐟

𝐑

𝐓𝟏

Let the number of clock pulses counted by the counter during T2 be N and T1 ∝ 2n. 𝐕 Then, 𝐍 = 𝐚 𝟐𝐧 𝐕𝐫𝐞𝐟

The accuracy of dual slope ADC is high since, its performance is independent of the exact values of R and C. However, its conversion speed is slow. 79 Prepared By: SriKisna Khadka BLEX 2006 Batch: WHCSE

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Sigma-Delta Converter The input signal comes into the modulator via a summing junction. It then passes through the integrator, which feeds a comparator that turns on and off the switch. They both act as a one-bit quantizer. The switch turns on/off a reference voltage (i.e. connect to +Vref or –Vref). As the input voltage increases or decreases, comparator turns on and off the reference voltage that is subtracted from the input signal, aiming to maintain zero on the output of the integrator. The comparator output is fed back to the input summing junction via one-bit DAC and the feedback loop forces the average of the signal ‘W’ to be equal to the input signal ‘X’. Delta (the difference) refers to delta modulation, that voltage at D is coded by one bit (bit value is either 1 or 0). Here, whole signal is not converter into digital code, but only the difference of current signal value and feedback signal, corresponding to the previous sample. Sigma (the sum) is because the sum of deltas is counted during the measured interval. The output of comparator gives a bit stream (1 or 0), its average level represent the average input signal level. If bit stream contains more number of 1, average value of signal will be high. C

X

R

+ W

Comparator

-

-

-

+

D

+

Integrator

+Vref

Fig: Sigma Delta Converter

-Vref DAC

The input voltage drives an integrator whose output is compared with any fixed voltage, such as ground. Depending on the comparator output, pulses of current of fixed length (i.e. fixed increments of charge) are switched into the summing junction or to the ground at each clock transition, with the effect of maintaining zero average current into the summing junction. This is the balancing concept. A counter keeps track of the number of charge pulses switched into the summing junction for a given number of clock pulses, say 4096. That count is proportional to the average input level during the 4096 clock pulses i.e. it is the output . Sigma-Delta ADC Sigma-Delta is a widely used method of analog to digital conversion, particularly in telecommunications using audio signals. This method id based on delta modulation, where the difference between two successive sample is quantized. Delta modulation is a 1-bit quantization method. The output of a delta modulator is a single bit data stream where the relative numbers of 1s and 0s indicate thee level or amplitude of the input signal. 80 Prepared By: SriKisna Khadka BLEX 2006 Batch: WHCSE

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In the sigma delta ADC, the analog input signal and the analog signal from the converted quantized bit stream from the DAC in the feedback loop are applied to the summation point. Integrator Analog Input +

Comparator Latch

D

D

Q

Bit Stream Out

-

Analog Signal Vmax = +Vref Vmin = - Vref

+Vref

Clock Fig: Block Diagram of First Order Sigma Delta ADC

-Vref 1-Bit DAC

The difference (D) signal out of the summation is integrated and the 1-bit ADC increases the number of 1s and 0s depending on the difference signal. This action attempts to keep the quantized signal that is fed back equal to the incoming analog signal. Characteristics of Data Converters Charactics Analog Output Static

Dynamic

Integral Linearity

Best Straight Line

7

Full Scale Error

6 Integral Linearity

Absolute Linearity

Differential Linearity

Best Straight Line Linearity

Monotonocity

D

Ideal Line ()

5

Gain Error = VA-VI (For I/P Code 111 With Offset Removed

4

End Point Linearity

d

3 Observed Values 2

Best St.Line Linearity Error

1 Zero Error Zero Error

Full Scale Error

Gain Error

Fig: Characteristics of ADC/DAC

Digital Input 000 001 010 011 100 101 110 111 Fig: Static Error Analysis

Static Characteristics  Integral Linearity It is the maximum deviation of the output of DAC (for any given input code) from the ideal straight line. At a particular input code it is given by: Integral Linearity = (Vobserved – Vreal)


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Integral Linearity is divide into following three categories. o Absolute Linearity: It is measured by assuming that the output of DAC will begin at zero and end at ideal full scale. It is further categorized as:  Zero Error: It is also called offset error. For input code 000 it is given by: Zero Error = (Vobserved – Videal)

 Full Scale Error: For input code 111, it is given by: Full Scale Error = (Vobserved – Videal)

 Gain Error: It is the difference between the gain of the actual and ideal static input-output characteristics. Gain error exists when the slope of the actual characteristics is not parallel to the slope of the ideal characteristics. Practically, for input code 111 with offset removed, gain error is given by: Gain Error = (Vobserved – Videal)

o Best Straight Line Linearity: The deviation of the observed values from the best straight line is termed as the best straight line linearity error. o End Point Linearity: It uses a straight line through the actual end points instead of ideal points. The deviation of the output observed values from this line is termed as the end point linearity error.

 Differential Linearity: For a particular input code, differential linearity error is given as: Differential Linearity Error = Dobserved - Dideal Digital Input 000 001 010

Analog Output Ideal Observed 0 0 0.5 0.6 1 1.2

Dideal

Dobserved

0 0.5 0.5

0 0.6 0.6

Differential Linearity 0 0.1 0.1

If Vactual is the actual change and Videal is the ideal change, then Differential linearity =

𝐕𝐚𝐜𝐭𝐮𝐚𝐥 −𝐕𝐢𝐝𝐞𝐚𝐥 𝐕𝐢𝐝𝐞𝐚𝐥

× 𝟏𝟎𝟎%

 Monotonocity: We say a DAC is non-monotonic when the sign of the slope of the input-output characteristic is not constant, i.e. an increase in the input code at some point causes the output voltage or current to decrease when it should be increasing (or to increase when it should be decreasing). Missing codes in an ADC is analogous to non-monotonic behavior in a DAC. Dynamic Characteristics From the moment that the digital word is applied on the input the presence of analog output voltage is called the conversion time. Settling time is the time it takes for the output 𝟏 to settle within a specified band ( 𝐋𝐒𝐁) of its final value. The output fluctuation is due to 𝟐 the switching effects, which produce transients for certain time.


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Examples 1. For an 8-bit D/A converter the Vref = 5V. If there is the fluctuation in reference voltage of about 10%. What will be the deviation in the LSB and MSB ?

Solution: Case I: When there is no fluctuation in Vref, MSB = 11111111 = 256 LSB = 00000000 = 0 Case II: After fluctuation, Vref = 5.5V, then Vo(LSB)|5V = Vref/28 = 5/28 = 0.0195V Vo(LSB)|5.5V = Vref/28 = 5.5/28 = 0.0215V  DVo in LSB = 0.0215 – 0.0195 = 2 mV Similarly, Vo(MSB)|5V = Vref/2 = 5/2 = 2.5V Vo(MSB)|5.5V = Vref/2 = 5.5/2 = 2.75V  DVo in MSB = 2.75 – 2.5 = 0.25 V 2. The Vref used in 8-bit R-2R ladder DAC is 5V. Find the output voltage for input values 00100000 and 10100100

Solution: For n-bits R-2R ladder network (Voltage Mode) Output Voltage (Vo) = {Vref/2n}D Case I: For input value: 00100000, D = 32  Vo = (5/28)×32 = 0.625V Case II: For input value: 10100100, D = 164  Vo = (5/28)×164 = 3.203V 3. What is the binary input of 6-bit DAC with Vref = 5V when its analog output is 3.28125V ?

Solution: As we have, Vo = {Vref/2n}D i.e. 3.28125 = (5/26)D i.e. D = 42 Since, D = 26-1S6-1 + 26-2S6-2 + 26-3S6-3 + 26-4S6-4 + 26-5S6-5 + 26-6S6-6 i.e. 42 = 25S5 + 24S4 + 23S3 + 22S2 + 21S1 + 20S0 i.e. 42 = 32 S5 + 16S4 + 8S3 + 4S2 + 2S1 + S0 Hence, For D to be 42: S5, S3 and S1 = 1 and S4, S2 and S0 = 0.  The digital input is 101010 4. Determine how many bits a D/A converter must have to provide the increment of 0.04V or less. The reference voltage is 10V.

Solution: For R-2R ladder network, Resolution = Vo(LSB) = Vref/2n i.e. 0.04 = 10/2n i.e. n = 7.96≈8 For weighted summer DAC, Resolution = Vo(LSB) = {Vref/2n-1}{Rf/R} So, for Rf = R i.e. 0.04 = 10/2n-1 i.e. 2n-1 = 250 i.e. n = 9


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5. Design a 5-bit binary weighted resistor DAC whose full scale output voltage is15V. What is the output voltage when the input is 01010 ?

Solution: Case I The full scale voltage is the output voltage, when all the inputs are high, i.e. 11111. So, Vo = - (1 + 2-1 + 2-2 + 2-3 + 2-4) × Vref × (Rf/R) Let, Rf/R = 1, then Vref = 7.7V (Note: Referring the figure with above circuit parameters as depicted in theory) Case II For input code: 01010, VO = - (2-1 + 2-3) × Vref = (0.5 + 0.125) × 7.7 = 4.8125V 6. In a 4-bit R-2R ladder network DAC operated in the current mode. R=10K and Vref = 20V. Find the current in each 20K resistor.

Solution: (Note: Referring the R-2R ladder network DAC in current mode) I = Vref/R = 20/10K = 2mA The current following through the 20K ladder of node 1 is, I1 = I/2 = 2/2 = 1mA Similarly, At different nodes current distribution is given as I2 = I/4 = 2/4 = 0.5 mA I3 = I/8 = 2/8 = 0.25 mA I4 = I/16 = 2/16 = 0.125 mA I5 = I4 = I/16 = 2/16 = 0.125 mA 7. A 5-bit flash-type A/D converter has a reference voltage of 10V. a) How many voltage comparators does it have ? b) What is the increment between the fixed voltage applied to its successive comparators ?

Solution: a) Number of comparators = 2n - 1 = 25 – 1 = 31 b) The increment between fixed voltage is: DV = Vref/2n = 10/2n = 0.3125V 8. The largest fixed voltage applied to a comparator in a flash type A/D converter is 14.8828125V when the reference voltage is 15V. What is the number of bits in the digital output ?

Solution: Drop in single resistor, VO(LSB) = DV = 15-14.8828125 = 0.1171875V As, VO(LSB) = DV = Vref/2n i.e. 0.1171875V = 15/2n i.e. n = 7 (i.e. number of bits in the digital output)


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9. List the sequence of binary numbers that would appear in the output register of 4-bit SAR A/D converter when the analog input has the value that is finally converted to 1011.

Solution: Analog Voltage (Va) = 11V = (1011)2 Step 1: MSB(B3) = 1, Let Vref = 16V, then Vd = Vref/2 = 16/2 = 8V Since, Va > Vd, MSB = 1 is set, then the register content is 1000 Step 2: NMSB(B2) = 1, then Vd = Vref/2 + Vref/4 = 16/2 + 16/4 = 12 Since, Va < Vd, B2 is set to 0, then the register content is 1000 again. Step 3: NSB(B1) = 1, then Vd = Vref/2 + Vref/8 = 8 + 2 = 10 Since, Va > Vd, B1 is set to 1, then register content is now 1010 Step 4: LSB(B0) = 1, then Vd = Vref/2 + Vref/8 + Vref/16 = 8 + 2 + 1 = 11V Since, Va = Vd, B0 is set to 1, then the register content becomes 1011. 10. In an 8-bit dual slope A/D converter, R1 = 20K and C = 0.001F. An analog input of value -0.25V is integrated for T1 = 160s. a) What is the maximum voltage reached in the integration ? b) If the integrator is switched to +5V, how long does it take to reach 0V. c) If the counter is clocked at 3.125MHz, what is the digital output after the conversion ?

Solution: Case I 𝐕 The maximum value reached in integration, VM = | − 𝐚 𝐓𝟏 | = | − 𝐑𝐜

𝟎.𝟐𝟓 ∗ 𝟏𝟔𝟎𝐬 𝟐𝟎𝐊 ∗ 𝟎.𝟎𝟎𝟏

| = 𝟐𝐕

Case II When the integrator is switched to 5V, let it takes t2 time to reach 0V by following a negative 𝐕 𝟎.𝟐𝟓 slope, then t2 is given by, t2 = 𝐚 𝐭 𝟏 = 𝟏𝟔𝟎𝐬 = 𝟖𝐬 𝐕𝐫𝐞𝐟

𝟓

Case III For f = 3.125 MHz, T2 = N/f i.e. n = 8𝐬 ∗ 𝟑. 𝟏𝟐𝟓𝐌𝐇𝐳 = 𝟐𝟓

Hence, the number of clock pulses counted by counter is 25. The digital output corresponding to 25 is 00011001. 11. An 8-bit dual slope A/D converter integrates analog input for T1 = 50s. What should be the magnitude of the reference voltage if an input of 25V produces the binary output 11111111 when the clock frequency is 1MHz ?

Solution: The binary output is 11111111 The number of clock pulses corresponding to the digital output is given by 27 + 26 + 25 + 24 + 23 + 22 + 21 + 20 = 255 Now, T2 = N/f = 255/1MHz = 255𝐬 𝐕 Also, T2 = 𝐚 𝐓𝟏 𝐕𝐫𝐞𝐟 𝟐𝟓

i.e. 255𝐬 =

𝐕𝐫𝐞𝐟 𝟐𝟓 ∗ 𝟓𝟎

50𝐬

i.e. Vref = = 𝟒. 𝟗𝐕 𝟐𝟓𝟓 Hence, the reference voltage is 4.9V


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12. For a given circuit: Fig(a) verify that: a. If a strength binary 8-bit converter is needed, we need r = 8R. b. If arrangement is intended as to decimal digit BCD converter, we need r = 4.8R.

VO

Fig: (a)

VO

Fig: (b)

(8/7)R//r

R

VO

Fig: (c)

VO

Rea Fig: (d)

Because of wide spread in resistance values for large N, the weighted resister DAC is not suitable. However, the weighted resistor network can be modified to accommodate a large number of bits without consequent spread in resistor values. One such circuit is shown in above figure. For this type of network, it is known that: 𝐒𝟑 𝐒𝟕

=

𝐒𝟐 𝐒𝟔

=

𝐒𝟏 𝐒𝟓

=

𝐒𝟎 𝐒𝟒

=

𝟏 𝟏𝟔

… (i)

Let the S3-bit be 1 and S2, S1 and S0 bits be all 0. Also assume that there is a virtual short circuit at the input of an op-amp. {Referring Fig: (b)} Now, 8R//4R//2R = 8/7R, which is again parallel with r, i.e. (8/7R)//r. {Referring Fig: (c)} Finally, Req = R + (8/7R)//r. {Referring Fig: (d)} 86 Prepared By: SriKisna Khadka BLEX 2006 Batch: WHCSE

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𝐕𝐑 𝟖 𝐑+(𝟕𝐑//𝐫)

Thus, 𝐈 = ∴ 𝐈𝐢𝐧 = {

(𝟖/𝟕)𝐑

=

𝐕𝐑 𝐫(𝟖/𝟕)𝐑 𝐑+{ } 𝐫+(𝟖/𝟕)𝐑

WHCSE BLEX V

… (ii)

}𝐈 … (iii)

𝐫+(𝟖/𝟕)𝐑

From equation (ii), putting value of I in equation (iii), we get: (𝟖/𝟕)𝐑

𝐈𝐢𝐧 = {

𝐫+(𝟖/𝟕)𝐑

𝐕𝐑 𝐫(𝟖/𝟕)𝐑 𝐑+{𝐫+(𝟖/𝟕)𝐑}

}[

]=

(𝟖/𝟕)𝐑𝐕𝐑 𝐑{𝐫+(𝟖/𝟕)𝐑}+𝐫(𝟖/𝟕)𝐑

=

𝐕𝐑

[

(𝟑/𝟕)𝐑

𝐑 {𝐫+(𝟖/𝟕)𝐑}+𝐫(𝟖/𝟕)

… (iv)

The current due to S7 can be easily calculated as follows: {Referring Fig: (d)}, but from the equation (i), it is already clear that the current Iin of equation (iv) must be 1/16th of the current of equation (v). Then from equation (i), (iv) and (v) we can write: 𝐈𝐢𝐧 = 𝐕𝐑

𝟏 𝟏𝟔

𝐈′𝐢𝐧 (𝟑/𝟕)𝐑

[

𝐑 {𝐫+(𝟖/𝟕)𝐑}+𝐫(𝟖/𝟕)

]=

𝐕𝐑 𝟏𝟔𝐑

(8/7)R× 𝟏𝟔 = {𝐫 + (𝟖/𝟕)𝐑. 𝐫(𝟖/𝟕)} 𝟏𝟐𝟖 𝟕 𝟏𝟐𝟎 𝟕

𝟖

𝟖

𝟕

𝟕

𝐑− 𝐑=𝐫+ 𝐫 𝐑=

𝟏𝟓 𝟕

𝐫

𝟏𝟓𝐫 = 𝟏𝟐𝟎𝐑 𝐫 = 𝟖𝐑 … (v) The circuit of fig (a) can be also used for decimal digit BCD converter. In this case, the value of ‘r’ is chosen so as to make the input current of op-amp corresponding to LSD and 1/10th of that of current due to MSD, this means, in this case: 𝐈𝐢𝐧 = i.e.

𝐕𝐑

i.e.

𝟖𝟎

𝟏 𝟏𝟎

[

𝐈′𝐢𝐧 (𝟖/𝟕)𝐑

𝐑 {𝐫+(𝟖/𝟕)𝐑}+𝐫(𝟖/𝟕)

𝟕

𝐑=

𝟏𝟓 𝟕

=

𝐕𝐑 𝟏𝟎𝐑

𝟖

𝐫+ 𝐑 𝟕

i.e. 𝟕𝟐𝐑 = 𝟏𝟓𝐫 i.e. 𝐫 = 𝟒. 𝟖𝐑 … (vi)


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Switched Power Supply Circuit Contents: o Switched Power Supply: Introduction o Switched Mode Power Supply (SMPS) o Switching Regulator


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Switched Power Supply Circuits

Introduction Voltage regulator

A voltage regulator is a circuit that supplies a constant voltage regardless of changes in load currents. The function of voltage regulator is to provide a stable dc voltage for powering other electronic circuits. A voltage regulator should be capable of providing substantial output current. Voltage regulator are classified as Series/Linear Regulator and Switching Regulator. o Series/Linear Regulator Series regulator use a power transistor connected in series between the unregulated dc input and the load. The output voltage is controlled by the continuous voltage drop taking place across the series pass resistor. Since, the transistor conducts in the active or linear region, these regulator are also called linear regulators. They may have fixed or variable output voltage and could be negative or positive. The impedance of linear regulator’s active element may be continuously varied to supply a desired current to the load. o Switching Regulator In switching regulator a switch is turned ON and OFF at a rate such that the regulators deliver the desired average current in periodic pulses to the load. Because the switching element dissipates negligible power in either ON or OFF state, the switching regulator is more efficient than the linear regulator. Linear Vs. Switching Regulators

 Linear regulators are best when low output noise (and low RFI radiated noise) is required.  Linear regulators are best when a fast response to input and output disturbances is required.  At low levels of power, linear regulators are cheaper and occupy less printed circuit board space.  Switching regulators are best when power efficiency is critical (such as in portable computers), except linear regulators are more efficient in a small number of cases (such as a 5V micro-processor often in “sleep” mode fed from a 6V battery, if the complexity of the switching circuit and the junction capacitance charging current means a high quiescent current in the switching regulator).  Switching regulators are required when the only power supply is a DC voltage, and a higher output voltage is required.  At high levels of power (above a few watts), switching regulators are cheaper (for example, the cost of removing heat generated is less).


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Switched Mode Power Supply (SMPS)

A Switched Mode Power Supply (SMPS/Switcher) is an electronic power supply unit (PSU) that incorporates a switching regulator in order to provide the required output voltage. An SMPS is a power converter that transmits power from a source (e.g., a battery or the electrical power grid) to a load (e.g., a personal computer). The function of the converter is to provide a regulated output voltage usually at a different level from the input voltage. Unlike a linear power supply, the pass transistor of a switching mode supply switches very quickly between full-on and full-off states, which minimizes wasted energy. Voltage regulation is provided by varying the ratio of on to off time. In contrast, a linear power supply must dissipate the excess voltage to regulate the output. This higher efficiency is the chief advantage of a switch-mode power supply. Switching regulators are used as replacements for the linear regulators when higher efficiency, smaller size or lighter weight are required. They are, however, more complicated, their switching currents can cause electrical noise problems if not carefully suppressed, and simple designs may have a poor power factor. Characteristics & Features of Switched Power Supply

 The series regulator , the pass transistor is operated in its linear region to provide a controlled voltage drop across it with a steady dc current flows , where as in case of switched mode regulator , the pass transistor is used as a “Controlled Switch” and is operated at either cutoff or saturation state. Hence, the power transmitted across the pass device is in discrete pulses rather then as a steady current flow.  Greater efficiency is achieved in switched mode regulator since the pass device is operated as a low impedance switch. The efficiency in SMPS is in the range of 70 - 90%.  Switched mode power supply dissipates only small amount of average power. When the pass device is in saturation and thus provides a maximum current to the load.  When the pass device is at cutoff, there is no current and dissipates no power.  Switched mode regulators rely on Pulse Width Modulation (PWM) to control the average value of the output voltage.  The switching power supply allows a decrease in size and cost.  Switched mode regulator basically operate at 20KHz or faster.

 Operating at this frequency allows the use of smaller transformer, capacitor, and inductors.  Switched mode power supply is slow in responding to transient load changes compared to the conventional series regulator.  The switching regulators are quite complex and one should be careful about the electromagnetic and radio frequency interference while using switched mode power supply.


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Switching Regulator

Switching regulators rapidly switch a series device on and off. The duty cycle of the switch sets how much charge is transferred to the load. This is controlled by a similar feedback mechanism as in a linear regulator. Because the series element is either fully conducting or switched off, it dissipates almost no power, this is what gives the switching design its efficiency. Switching regulators are also able to generate output voltages which are higher than the input or of opposite polarity – something not possible with a linear design. Basically, Switching Regulators are of three types. 1. Step- down regulator. 2. Step- up regulator. 3. Inverting regulator.

Step Down Regulator

In this type of regulator Vout is always less than Vin . An unregulated positive dc voltage is applied to the collector of the NPN transistor. A series of pulses from an oscillator is sent to the base of the transistor, which gets saturated (close) on each of the positive pulses. Vin

RL

Fig: Step Down Regulator

It is so because NPN transistor needs a positive voltage pulse on its base in order to turn on. A saturated transistor acts as a closed switch. Hence, it allows Vin to send current through inductor (L) and charges capacitor (C) to the value of the output voltage during the on-time (Ton) of the pulse. The diode D1 is reverse biased at this point and hence does not conduct. Eventually, when positive pulse turn to zero, transistor is cutoff and acts like an open switch during the ‘off’ period (Toff) of the pulse. The collapsing magnetic field of the coil produces self induced voltage and keeps the current flowing by returning energy to the circuit. The value of output voltage depends on the input voltage and pulse width, i.e. on-time of the transistor when on time is increased relative to off time, capacitor charges more thus increasing Vout. When Ton is decreased, capacitor discharges more thus decreasing Vout. By adjusting the duty cycle (Ton/T) of the transistor Vout can be varied as: Vout = Vin×(Ton/T) 91 Prepared By: SriKisna Khadka BLEX 2006 Batch: WHCSE

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WHCSE BLEX V

t

Step Up Regulator

When the transistor is turn on, the arrival of the positive pulse at its base and voltage across inductor increases quickly to Vin-Vce(sat) and magnetic field of inductor expands quickly. During on-time of the transistor, UL keeps decreasing from its initial maximum value. Longer the transistor is on, shorter the VL becomes . When transistor turn off, magnetic field of inductor collapse and its polarity reverse so that its voltage adds to the input voltage thus producing an output voltage greater than the input voltage. During off-time of the transistor, D2 is forward biased and allows capacitor to charge. The variations in Vout due to charging and discharging action are sufficiently smoothed by filtering action of inductor (L) and capacitor (C). It may be noted that shorter the on-time of the transistor, greater is the inductor voltage and hence greater the output voltage. On the other hand, longer is the on-time, smaller the inductor voltage and hence, lower the output voltage as: Vout = Vin×(T/Ton)

Fig: Step Up Regulator

Inverting Switching Regulator

This regulator provides an output voltage that is opposite in polarity to the input voltage. When the transistor is turn on by the positive pulses, the inductor voltage VL jumps to Vin – Vce(sat) and the magnetic field of the inductor expands rapidly. When the transistor is on, the diode D1 is reverse biased and VL decreases from its initial maximum value. When transistor goes turn off, the magnetic field collapses and inductor polarity reverses . This forward biases D1, charges capacitor and produces a negative output voltage. This repetitive on and off action of the transistor produces a repetitive charging and discharging that is smoothed by LC filter action.

Fig: Inverting Regulator


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IC Switched Voltage Regulator IC 723/723C is a general purpose adjustable output voltage regulator designed primarily

for series positive voltage regular applications but it is capable of operation in positive or negative power supplies as a series, shunt, switching or floating regulator. The IC switched voltage regulator 723C has the following features.   

Extremely low stand by drain current. Provision for liner as well as feedback current limiting. Wide adjustable o/ p voltage range. (2v to 37v)

Fig: IC Switched Voltage Regulator

Low Voltage Regulator

The low voltage regulators is also known as the step down voltage regulators. The operating range of this type of regulator is 2V to 7V . The o/p voltage in this case is always less than the input voltage. The general IC circuit diagram for this type of regulator is shown.

Fig: Low Voltage Regulator

The output voltage for this type of regulator is given by the equation: Vout = Vref ×/R2/(R1 +R2) and R3 = R1×R2/(R1+R2) for minimum temperature difference.


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High Voltage Regulator

The high voltage regulator generally operate at the range of 7V to 37V. The general IC circuit diagram for this type for this regulator is shown in figure. The output voltage for this type of regulator is given by the equation, Vout = Vref×(R1+R2)/R1 and R3 = R1×R2/(R1+R2) for minimum temperature difference.

Fig: IC Switched Voltage Regulator

Control Circuits (IC LM117/217/317)

The voltage control circuit by using IC LM117 is a three terminal adjustable positive voltage regulators and are available in the current rating of 0.1A to 1.5A. The output voltage is controlled by adjusting the variable resister R2 as shown in fig below. The voltage is adjustable from 1.2V to 37V. The high voltage versions are LM117 HV/LM217 HV/LM317 HV. These type of control circuit is in-built with current limit and thermal overload protection. Their performance specifications are much better than those of fixed voltage regulators.

Fig: Control Circuits (IC LM117/217/317)


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WHCSE BLEX V

Power Conversion Circuits Contents: o Power Conversion Circuits: Introduction o Power Semiconductor Devices o Controlled Rectifier Circuits


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Power Conversion Circuits Introduction Power Supply: Power supply is a supply of power i.e. electrical power. A device or

system that supplies electrical or other types of energy to an output (load) or group of loads is called a power supply unit or PSU. The term is most commonly applied to electrical energy supplies, less often to mechanical ones, and rarely to others. Power Conversion: Power conversion has a more specific meaning, namely

converting electrical power from one form to another. This could be as simple as a transformer to change the voltage of AC power, but also includes far more complex systems. The term can also refer to a class of electrical machinery that is used to convert one frequency of electrical power into another frequency. Power conversion systems often incorporate redundancy and voltage regulation. One way of classifying power conversion systems is according to whether the input and output are alternating current (AC) or direct current (DC). AC to DC

AC to AC

DC to DC DC to AC

 Rectifier  Main Power Supply Unit (PSU)  Switched Mode Power Supply (SMPS)  Transformer/Autotransformer  Voltage Converter  Voltage Regulator  Cycloconverter  Variable Frequency Transformer  DC to DC Converter  Voltage Stabilizer  Linear Regulator  Inverter

There are also devices and methods to convert between power systems designed for single and three-phase operation. Conversion of one form of electrical power to another desired form and voltage, typically involving converting AC line voltage to a wellregulated lower-voltage (DC) for electronic devices. Low voltage, low power DC power supply units are commonly integrated with the devices they supply, such as computers and household electronics. Power Semiconductor Devices Semiconductor devices are electronic components that exploit the electronic properties of semiconductor materials, principally silicon, germanium and gallium arsenide. Semiconductor devices have replaced thermo ionic devices (vacuum tubes) in most applications. They use electronic conduction in the solid state as opposed to the gaseous state or thermo ionic emission in a high vacuum. Semiconductor devices are manufactured both as single discrete devices and as integrated circuits (ICs), which consist of a number from a few (as low as two) to billions of devices manufactured and interconnected on a single semiconductor substrate. 96 Prepared By: SriKisna Khadka BLEX 2006 Batch: WHCSE

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Power Diodes A diode is a two-terminal electronic component. The most common function of a diode is to allow an electric current in one direction (called the diode's forward direction) while blocking current in the opposite direction (the reverse direction). Thus, the diode can be thought of as an electronic version of a check valve. This unidirectional behavior is called rectification and is used to convert alternating current to direct current and extract modulation from radio signals in radio receivers.

i

Anode

Cathode

P

N

i

i

Cathode

Anode

VBR

V

V

Fig I: PN - Junction Diode A Schematic Diagram

Fig II: PN - Junction Diode A Symbolic Diagram

Reverse Biasing

i ID

Forward Biasing

V

Reverse Leakage Current

Fig III: V-I Characteristics of a Practical Diode

VD

Forward Biasing

V

Reverse Biasing

Fig IV: V-I Characteristics of a Ideal Diode

Case 1: When an anode potential is positive with respect to the cathode, the diode is said to be forward biased and the diode conducts. A conducting diode has a relatively small forward voltage drop across it and the magnitude of this drop depends on the manufacturing process and junction temperature. Case 2: When the cathode potential is positive with respect to the anode, the diode is said to be reverse biased. Under reverse biased conditions a small reverse current (leakage current) in the range of A or mA flows and this leakage current increases slowly in magnitude with the reverse voltage until the zero voltage is reached. The v-i characteristics of a diode either in forward or reverse bias can be expressed by an equation known as Shockley Diode Equation as: 𝐕𝐃 ⁄𝐕 𝐓

𝐈𝐃 = 𝐈𝐒 (𝐞

− 𝟏) … (𝐢) Where, ID – Current through the diode. VD – Diode voltage with anode positive w.r.t. cathode. IS – Leakage current (10-6 – 10-15A)  - Empirical constant/Emission co-efficient/ideality factor (1 or 2). It depends on the material and the physical construction of the diode. For germanium diode,  = 1 and for silicon diode,  = 2. But for the most practical silicon diode,  falls in the range 1.1 to 1.8. VT = (KT/q) – Thermal voltage, where q – charge of electron (1.6 × 10-19 C), T – absolute temperature (273K), K – Boltzmann’s constant (1.3806 × 10-23 J/C). At a junction temperature of 25oC, VT = (1.3806 × 10-23 J/C)(273+25)/(1.6 × 10-19 C) = 25.7 mV. At a specified temperature, the leakage current IS is constant for a given diode. The diode characteristics can be divided into three regions namely:   

Forward-Biased Region, Where VD > 0 Reverse-Biased Region, Where VD < 0 Breakdown Region, Where VD = -VBR 97 Prepared By: SriKisna Khadka BLEX 2006 Batch: WHCSE

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Forward Biased Region:

 The diode current, ID is very small if VD < VTD (typically 0.7V for silicon diode).  The diode conducts fully, if VD > VTD, which is referred to as the threshold or cut-in or turn-on voltage.  Let, VD = 0.1V,  = 1, VT = 25.7 mV, then 𝐕𝐃 ⁄𝐕 𝐓

𝐈𝐃 = 𝐈𝐒 (𝐞

− 𝟏)

𝟎.𝟏 𝐈𝐒 (𝐞 ⁄𝟎.𝟎𝟐𝟓𝟕

= 𝐈𝐃 = 𝟒𝟕. 𝟗𝟔𝐈𝐒

− 𝟏) 𝐕𝐃 ⁄𝐕 𝐓)

 The Shockley equation can be approximated to 𝐈𝐃 = 𝐈𝐒 (𝐞 2.1%. As VD increases then error decreases rapidly. 𝐕𝐃 ⁄𝐕 𝐓

Hence, for VD > 0.1V and ID >> IS, 𝐈𝐃 = 𝐈𝐒 (𝐞

with an error of

𝐕𝐃 ⁄𝐕 𝐓)

− 𝟏) = 𝐈𝐒 (𝐞

Reverse Biased Region:

 In reverse biased region, VD < 0.  If VD < 0 and |VD| >> VT, which occurs for VD < -0.1V, then the exponential term of Shockley equation becomes negligibly small compared with unity and the diode current 𝐕𝐃 ⁄

ID becomes, 𝐈𝐃 = 𝐈𝐒 (𝐞 𝐕𝐓 − 𝟏) ≈ −𝐈𝐒 , which indicated that the diode current ID in the reverse direction is constant and is equal to IS. Breakdown Region:

 In this region, the reverse voltage is very high.  The magnitude of the reverse voltage may exceed a specified voltage known as the breakdown voltage, VBR with a small change in reverse voltage beyond VBR.  The reverse current increases rapidly.  The breakdown is reversible provided that the power dissipation is within safe level. Application of Diodes:  Radio Demodulation

The first use for the diode was the demodulation of amplitude modulated (AM) radio broadcasts. The history of this discovery is treated in depth in the radio article. In summary, an AM signal consists of alternating positive and negative peaks of voltage, whose amplitude or “envelope” is proportional to the original audio signal. The diode (originally a crystal diode) rectifies the AM radio frequency signal, leaving an audio signal which is the original audio signal, minus atmospheric noise. The audio is extracted using a simple filter and fed into an audio amplifier or transducer, which generates sound waves.  Power Conversion

Rectifiers are constructed from diodes, where they are used to convert alternating current (AC) electricity into direct current (DC). Automotive alternators are a common example, where the diode, which rectifies the AC into DC, provides better performance than the commutator of earlier dynamo. Similarly, diodes are also used in Cockcroft-Walton voltage multipliers to convert AC into higher DC voltages.


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 Over-Voltage Protection Diodes are frequently used to conduct damaging high voltages away from sensitive electronic devices. They are usually reverse-biased (non-conducting) under normal circumstances. When the voltage rises above the normal range, the diodes become forward-biased (conducting). For example, diodes are used in (stepper motor and Hbridge) motor controller and relay circuits to de-energize coils rapidly without the damaging voltage spikes that would otherwise occur. (Any diode used in such an application is called a fly-back diode). Many integrated circuits also incorporate diodes on the connection pins to prevent external voltages from damaging their sensitive transistors. Specialized diodes are used to protect from over-voltages at higher power.  Logic Gates Diodes can be combined with other components to construct AND & OR logic gates. This is referred to as diode logic.  Ionizing Radiation Detectors Semiconductor diodes are sensitive to more energetic radiation. In electronics, cosmic rays and other sources of ionizing radiation cause noise pulses and single and multiple bit errors. This effect is sometimes exploited by particle detectors to detect radiation. A single particle of radiation, with thousands or millions of electron volts of energy, generates many charge carrier pairs, as its energy is deposited in the semiconductor material. If the depletion layer is large enough to catch the whole shower or to stop a heavy particle, a fairly accurate measurement of the particle’s energy can be made, simply by measuring the charge conducted and without the complexity of a magnetic spectrometer or etc. These semiconductor radiation detectors need efficient and uniform charge collection and low leakage current. They are often cooled by liquid nitrogen. For longer range (about a centi-meter) particles they need a very large depletion depth and large area. For short range particles, they need any contact or un-depleted semiconductor on at least one surface to be very thin. The back-bias voltages are near breakdown (around a thousand volts per centi-meter). Germanium and silicon are common materials. Some of these detectors sense position as well as energy. They have a finite life, especially when detecting heavy particles, because of radiation damage. Silicon and germanium are quite different in their ability to convert gamma rays to electron showers. Semiconductor detectors for high energy particles are used in large numbers. Because of energy loss fluctuations, accurate measurement of the energy deposited is of less use.  Temperature Measurements A diode can be used as a temperature measuring device, since the forward voltage drop across the diode depends on temperature, as in a silicon band gap temperature sensor. From the Shockley ideal diode equation given above, it appears the voltage has a positive temperature coefficient (at a constant current) but depends on doping concentration and operating temperature (Sze 2007). The temperature coefficient can be negative as in typical thermistors or positive for temperature sense diodes down to about 20 Kelvin. Typically, silicon diodes have approximately −2 mV/˚C temperature coefficient at room temperature.


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 Current Steering Diodes will prevent currents in unintended directions. To supply power to an electrical circuit during a power failure, the circuit can draw current from a battery. An Uninterruptible power supply may use diodes in this way to ensure that current is only drawn from the battery when necessary. Similarly, small boats typically have two circuits each with their own battery/batteries: one used for engine starting; one used for domestics. Normally both are charged from a single alternator, and a heavy duty split charge diode is used to prevent the higher charge battery (typically the engine battery) from discharging through the lower charged battery when the alternator is not running. Diodes are also used in electronic musical keyboards. To reduce the amount of wiring needed in electronic musical keyboards, these instruments often use keyboard matrix circuits. The keyboard controller scans the rows and columns to determine which note the player has pressed. The problem with matrix circuits is that when several notes are pressed at once, the current can flow backwards through the circuit and trigger "phantom keys" that cause “ghost” notes to play. To avoid triggering unwanted notes, most keyboard matrix circuits have diodes soldered with the switch under each key of the musical keyboard. The same principle is also used for the switch matrix in solid state pinball machines. Power Transistors A transistor is a semiconductor device used to amplify and switch electronic signals. It is made of a solid piece of semiconductor material, with at least three terminals for connection to an external circuit. A voltage or current applied to one pair of the transistor's terminals changes the current flowing through another pair of terminals. Because the controlled (output) power can be much more than the controlling (input) power, the transistor provides amplification of a signal. Some transistors are packaged individually but many more are found embedded in integrated circuits. Transistor as a Switch

Transistors are commonly used as electronic switches, for both high power applications including switched mode power supplies and low power applications such as logic gates. In a grounded-emitter transistor circuit, such as the light-switch circuit shown, as the base voltage rises the base and collector current rise exponentially, and the collector voltage drops because of the collector load resistor. The relevant equations are: VRC = ICE × RC, the voltage across the load (the lamp with resistance RC) VRC + VCE = VCC, the supply voltage shown as 6V. If VCE could fall to 0 (perfect closed switch) then Ic could go no higher than VCC / RC, even with higher base voltage and current. The transistor is then said to be saturated.

Fig: Transistor as a Switch

Hence, values of input voltage can be chosen such that the output is either completely off, or completely on. The transistor is acting as a switch, and this type of operation is common in digital circuits where only "on" and "off" values are relevant. 100 Prepared By: SriKisna Khadka BLEX 2006 Batch: WHCSE

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Transistor as an Amplifier

The common emitter amplifier is designed so that a small change in voltage in (Vin) changes the small current through the base of the transistor and the transistor's current amplification combined with the properties of the circuit mean that small swings in Vin produce large changes in Vout. Various configurations of single transistor amplifier are possible, with some providing current gain, some voltage gain and some both.

Fig: Transistor as an Amplifier

From mobile phones to televisions, vast numbers of products include amplifiers for sound reproduction, radio transmission and signal processing. The first discrete transistor audio amplifiers barely supplied a few hundred milli-watts, but power and audio fidelity gradually increased as better transistors became available and amplifier architecture evolved. Modern transistor audio amplifiers of up to a few hundred watts are common and relatively inexpensive. Power BJT (Bipolar Junction Transistor)

A bipolar junction transistor (BJT) is a three-terminal electronic device constructed of doped semiconductor material and may be used in amplifying or switching applications. Bipolar transistors are so named because their operation involves both electrons and holes. Charge flow in BJT is due to bidirectional diffusion of charge carriers across a junction between two regions of different charge concentrations.

Fig: Cross Sectional Structure of Bipolar Junction Transistor (NPN Type)

This mode of operation is contrasted with uni-polar transistors, such as field-effect transistors, in which only one carrier type is involved in charge flow due to drift. By design, most of the BJT collector current is due to the flow of charges injected from a high concentration emitter into the base where they are minority carriers that diffuse toward the collector, and so BJTs are classified as minority-carrier devices. Region of Operation

Bipolar transistors have five distinct regions of operation, defined mostly by applied bias:  Forward-Active Region

The base–emitter junction is forward biased and the base–collector junction is reverse biased. Most bipolar transistors are designed to afford the greatest common-emitter current gain βF, in forward-active mode. If this is the case, the collector–emitter current is approximately proportional to the base current, but many times larger, for small base current variations.


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 Reverse-Active Region

By reversing the biasing conditions of the forward-active region, a bipolar transistor goes into reverse-active mode. In this mode, the emitter and collector regions switch roles. Because most BJTs are designed to maximize current gain in forward-active mode, the βF in inverted mode is several (2–3 for the ordinary germanium transistor) times smaller. This transistor mode is seldom used, usually being considered only for failsafe conditions and some types of bipolar logic. The reverse bias breakdown voltage to the base may be an order of magnitude lower in this region.  Saturation Region

With both junctions forward-biased, a BJT is in saturation mode and facilitates high current conduction from the emitter to the collector. This mode corresponds to a logical "on", or a closed switch.  Cut-Off Region

In cutoff, biasing conditions opposite of saturation (both junctions reverse biased) are present. There is very little current flow, which corresponds to a logical "off", or an open switch.  Avalanche Breakdown Region

Note: Although these regions are well defined for sufficiently large applied voltage, they overlap somewhat for small (less than a few hundred milli-volts) biases. For example, in the typical grounded-emitter configuration of an NPN BJT used as a pull-down switch in digital logic, the "off" state never involves a reverse-biased junction because the base voltage never goes below ground; nevertheless the forward bias is close enough to zero that essentially no current flows, so this end of the forward active region can be regarded as the cutoff region. Active Mode NPN Transistors in Circuit

An NPN transistor connected to two voltage sources. To make the transistor conduct appreciable current (on the order of 1 mA) from C to E, VBE must be above a minimum value sometimes referred to as the cut-in voltage. The cut-in voltage is usually about 600 mV for silicon BJTs at room temperature but can be different depending on the type of transistor and its biasing. This applied voltage causes the lower PN junction to 'turn-on' allowing a flow of electrons from the emitter into the base.

Fig: Active Mode NPN Transistor in Circuit

In active mode, the electric field existing between base and collector (caused by VCE) will cause the majority of these electrons to cross the upper PN junction into the collector to form the collector current IC. The remainder of the electrons recombine with holes, the majority carriers in the base, making a current through the base connection to form the base current, IB. As shown in the diagram, the emitter current, IE, is the total transistor current, which is the sum of the other terminal currents (i.e. IE = IB + IC).


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In the diagram, the arrows representing current point in the direction of conventional current – the flow of electrons is in the opposite direction of the arrows because electrons carry negative electric charge. In active mode, the ratio of the collector current to the base current is called the DC current gain. This gain is usually 100 or more, but robust circuit designs do not depend on the exact value. The value of this gain for DC signals is referred to as hFE, and the value of this gain for AC signals is referred to as hfe. However, when there is no particular frequency range of interest, the symbol β is used. It should also be noted that the emitter current is related to VBE exponentially. At room temperature, an increase in VBE by approximately 60 mV increases the emitter current by a factor of 10. Because the base current is approximately proportional to the collector and emitter currents, they vary in the same way. Applications

The BJT remains a device that excels in some applications, such as discrete circuit design, due to the very wide selection of BJT types available, and because of its high transconductance and output resistance compared to MOSFETs. The BJT is also the choice for demanding analog circuits, especially for very high frequency applications, such as radio frequency circuits for wireless systems. Temperature Sensors Because of the known temperature and current dependence of the forward-biased base– emitter junction voltage, the BJT can be used to measure temperature by subtracting two voltages at two different bias currents in a known ratio. Logarithmic Converters Because base–emitter voltage varies as the log of the base–emitter and collector–emitter currents, a BJT can also be used to compute logarithms and anti-logarithms. A diode can also perform these nonlinear functions, but the transistor provides more circuit flexibility. Vulnerabilities Exposure of the transistor to ionizing radiation causes radiation damage. Radiation causes a buildup of 'defects' in the base region that act as recombination center. The resulting reduction in minority carrier lifetime causes gradual loss of gain of the transistor. Power BJTs are subject to a failure mode called secondary breakdown, in which excessive current and normal imperfections in the silicon die cause portions of the silicon inside the device become disproportionately hotter than the others. The doped silicon has a negative temperature coefficient, meaning that it conducts more current at higher temperatures. Thus, the hottest part of the die conducts the most current, causing its conductivity to increase, which then causes it to become progressively hotter again, until the device fails internally. The thermal runaway process associated with secondary breakdown, once triggered, occurs almost instantly and may catastrophically damage the transistor package. 103 Prepared By: SriKisna Khadka BLEX 2006 Batch: WHCSE

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Thyristor (Silicon Controlled Rectifier) The thyristor is a solid state semiconductor device with four layers of alternating N and P-type material. They act as bi-stable switches, conducting when their gate receives a current pulse, and continue to conduct for as long as they are forward biased (that is, as long as the voltage across the device has not reversed). Some sources define silicon controlled rectifiers and thyristors as synonymous.

Fig: Thyristor Configurations & Its Circuit Symbol

Thyristors have three states of operation: 1. Reverse Blocking Mode Voltage is applied in the direction that would be blocked by a diode. 2. Forward Blocking Mode: Voltage is applied in the direction that would cause a diode to conduct, but the thyristor has not yet been triggered into conduction. 3. Forward conducting mode The thyristor has been triggered into conduction and will remain conducting until the forward current drops below a threshold value known as the "holding current". The thyristor has three p-n junctions (serially named J1, J2, J3 from the anode). When the anode is at a positive potential VAK with respect to the cathode with no voltage applied at the gate, junctions J1 and J3 are forward biased, while junction J2 is reverse biased. As J2 is reverse biased, no conduction takes place (Off state). Now if VAK is increased beyond the breakdown voltage VBO of the thyristor, avalanche breakdown of J2 takes Fig: Layer Diagram of Thyristor place and the thyristor starts conducting (On state). If a positive potential VG is applied at the gate terminal with respect to the cathode, the breakdown of the junction J2 occurs at a lower value of VAK. By selecting an appropriate value of VG, the thyristor can be switched into the on state suddenly. It should be noted that once avalanche breakdown has occurred, the thyristor continues to conduct, irrespective of the gate voltage, until both: (a) the potential VG is removed and (b) the current through the device (anode-cathode) is less than the holding current specified by the manufacturer. These gate pulses are characterized in terms of gate trigger voltage (VGT) and gate trigger current (IGT). Gate trigger current varies inversely with gate pulse width in such a way that it is evident that there is a minimum gate char required to trigger the thyristor.


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Switching Characteristics In a conventional thyristor, once it has been switched on by the gate terminal, the device remains latched in the on-state (i.e. does not need a continuous supply of gate current to conduct), providing the anode current has exceeded the latching current (IL). As long as the anode remains positively biased, it cannot be switched off until the anode current falls below the holding current (IH). A thyristor can be switched off if the external circuit causes the anode to become negatively biased. In some applications this is done by switching a second thyristor to discharge a capacitor into the cathode of the first thyristor. This method is called forced commutation. After a thyristor has been switched off by forced commutation, a finite time delay must have elapsed before the anode can again be positively biased and retain the thyristor in the offstate. This minimum delay is called the circuit commutated turn off time (tQ).

IT

IL

VBO

IH

VT Fig: V-I Characteristics

Attempting to positively bias the anode within this time causes the thyristor to be selftriggered by the remaining charge carriers (holes and electrons) that have not yet recombined. For applications with frequencies higher than the domestic AC mains supply (e.g. 50 Hz or 60 Hz), thyristors with lower values of tQ are required. Such fast thyristors are made by diffusing into the silicon heavy metals ions such as gold or platinum which act as charge combination centers. Two Transistor Model of Thyristor A thyristor can be considered as two complementary transistors, one pnp-transistor, Q1 and other npn-transistor, Q2 as shown in the figure below. A IA=IT

IT

 1

J1

G

A

IG

Q2

J2

Q1

IB1 = IC2

Q1 J2

IG

J3

G

0.8 0.6

IB2

Q2

0.4 0.2

IK

K

FigI : Basic Structure

IK K FigII : Equivalent Circuit

10-4

10-3

1 -2 10

10-1

IE

1

FigIII :Variation of Current Gain with IE

The collector current is related to emitter current by: 𝐈𝐂 = 𝛂𝐈𝐄 + 𝐈𝐂𝐁𝐎 … (𝐢) , where: IC = Collector Current IE = Emitter Current ICBO = Leakage Current of Collector Base Junction and  = Common Base Current Gain = β/(β+1)


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Hence, from equation … (i) For Transistor, Q1: 𝐈𝐂𝟏 = 𝛂𝟏 𝐈𝐄𝟏 + 𝐈𝐂𝐁𝐎𝟏 = 𝛂𝟏 𝐈𝐀 + 𝐈𝐂𝐁𝐎𝟏 and For Transistor, Q2: 𝐈𝐂𝟐 = 𝛂𝟐 𝐈𝐄𝟐 + 𝐈𝐂𝐁𝐎𝟐 = 𝛂𝟐 𝐈𝐊 + 𝐈𝐂𝐁𝐎𝟐 Now, by combining IC1 and IC2, we get IA i.e. 𝐈𝐀 = 𝐈𝐂𝟏 + 𝐈𝐂𝟐 = 𝛂𝟏 𝐈𝐀 + 𝐈𝐂𝐁𝐎𝟏 + 𝛂𝟐 𝐈𝐊 + 𝐈𝐂𝐁𝐎𝟐 = 𝛂𝟏 𝐈𝐀 + 𝛂𝟐 (𝐈𝐀 + 𝐈𝐆 ) + (𝐈𝐂𝐁𝐎𝟏 + 𝐈𝐂𝐁𝐎𝟐 ) i.e. 𝐈𝐀 =

𝛂𝟐 𝐈𝐆 +(𝐈𝐂𝐁𝐎𝟏 +𝐈𝐂𝐁𝐎𝟐 ) [𝟏−(𝛂𝟏 +𝛂𝟐 )]

[𝐈𝐊 = 𝐈𝐀 + 𝐈𝐆 ]

…(ii) [(𝛂𝟏 + 𝛂𝟐 ) < 1]

 The current gain 𝛂𝟏 varies with IA=IE and 𝛂𝟐 varies with IK = IA + IG. A typical variation of current gain with emitter current, IE is shown in figure III above. The device is in “OFF” state when (𝛂𝟏 + 𝛂𝟐 )

A Notebook on Electronic Circuits II

A Notebook on Electronic Circuits II

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