PROC. 25th INTERNATIONAL CONFERENCE ON MICROELECTRONICS (MIEL 2006), BELGRADE, SERBIA AND MONTENEGRO, 14-17 MAY, 2006
A Novel 3D Embedded Gate Field Effect Transistor: Device Concept and Modelling K. Fobelets, MIEEE, P.W. Ding, and J.E. Velazquez-Perez
I. INTRODUCTION One of the objectives in semiconductor industry is higher operation speed and lower power consumption of the devices used in circuits and systems. To that aim, in field effect transistor (FET) technology, gate lengths are aggressively scaled to nanometer dimensions and gate oxide’s thickness are currently no thicker than 2 nm. One of the problems associated with this downscaling is the increased leakage current which has a detrimental impact on power consumption for ULSI circuits. From the point of view of the analog circuit designer two main problems arise: poor output conductance and increased matching difficulties. In order to solve the different problems occurring with downscaling, the next generation of FETs will use heterostructures [1] and/or different gate topologies [2,3]. These new approaches, based on progress in nano-technology, introduce 2D/3D gating configurations, which require in general difficult or labour intensive processing. The proposed embedded-gate screen grid FET (SGFET) in this manuscript is based on similar principles as the permeable base transistor (PBT) [4], but with drastically reduced processing complexity, compatible with current SOI technology and shows excellent improvements in DC behaviour compared to the other FET structures.
K.Fobelets, and P.W. Ding are with the Department of Electrical and Electronic Engineering, Imperial College London, Exhibition Road, London SW7 2BT, UK, E-mail:
[email protected]. J.E. Velázquez-Pérez, is with the Department of Applied Physics, Universidad de Salamanca, Pza. de la Merced, s/n, E37008 Salamanca, Spain, E-mail:
[email protected].
1-4244-0117-8/06/$20.00 © 2006 IEEE
II. DEVICE STRUCTURE LAYOUT AND FUNCTIONING A schematic drawing of a proposed SGFET is given in Fig.1. The SGFET depicted has two rows consisting each of three gate cylinders, this distribution is by no means exclusive. G Deposited SiO2
Buried SiO2 D
S Thermal SiO2
Abstract - A novel 3D Field Effect Transistor on SOI – the screen grid FET (SGFET) – for ultra-low power applications is proposed and TCAD analysis of the device is presented. The device is designed with the aim of decoupling the need for aggressive scaling of the gate oxide thickness when reducing the channel length. Other scaling objectives are: retaining low doping in the channel, maintaining the drain conductance and optimizing the low power/low voltage device behaviour. The simulation results show that these objectives are fulfilled: oxide thickness and channel doping have a reduced influence on the threshold voltage and do not need to be scaled aggressively to reduce the short channel effects. Finally, we show that the device performance for low-power/low-voltage applications is excellent.
Inside channel S
D SiO2 Gating cylinders
G row 1
row 2
Fig. 1. Schematic configuration of a screen-grid FET with two gating rows, each consisting of 3 gate cylinders. Top: 3D side view. Bottom: channel region only. S, D indicate the start of the of the source and drain region resp., G is the gate.
The SGFET is fabricated in Silicon-on-insulator (SOI) and can be equally fabricated in the more advanced SSOI (strained-Si on insulator) technology [1] to benefit from the improved characteristics of the strained-Si channel. In the SGFET the deposited top oxide inhibits top surface gating and thus the source-drain conduction is only controlled by the gate cylinders inside the channel region. The gating action for a unipolar SGFET is schematically illustrated in Fig.2 in 2D, the rectangle represents the Si channel, the dotted region the gate metal, the grey area the gate oxide and the shaded region the depletion region. The source and drain regions (not drawn) are heavily doped and, in the simulations, have the same width as the channel. The gating occurring between two gate cylinders in the same row is consistent with a double gating action. At VGS=0V, the depletion width extending from the gate into
the channel is determined by the workfunction difference between the gate metal and the channel. In Fig.2 top, this is insufficient to deplete the channel region between the two gate cylinders and a current determined by the distance “a” will flow. Increasing the depletion widths by the gate potential pinches off the channel – a=0nm – and switches the current off (Fig.2 bottom). The choice of the gate metal allows the control of the absolute value and the sign of the threshold voltage (Vth).
conductance gd when the channel length is shortened – control drain induced barrier lowering (DIBL), and to optimize the device behaviour for low power/low voltage applications – thus minimizing the subthreshold slope, S. Bearing the above in mind, the most suitable method to study the electrical behaviour of the device is the driftdiffusion one (we used the Taurus/Medici 2D simulator from Synopsys [5]). It is well known that this method fails to correctly describe the electron transport in deep submicron devices since the carriers are intensely heated in the channel. However, in this paper we will limit ourselves to the study of relatively long channels (source to drain distances of about 0.8Pm). Moreover, as the carriers are not confined in a quantum well (and therefore subject to the action of the perpendicular component of the electric field) their mobility becomes less dependent on the local value of the electrical field. As the device is 3D, we assume that the channel thickness, doping and electrostatic effects in the third dimension (from top surface to BOX) are uniform, deviations will require 3D simulations to study their impact.
Linter Fig. 2. Illustration of gating action between gate cylinders. Top: when VGS=0V, bottom: when VGS §Vth. Dotted region gate contact, grey region: gate oxide, shaded region: space charge region., white region: channel (Si).
Introducing the SGFET gate topology as shown in Figs.1 and 2 implies that the control of the gate and the source-to-drain (SD) distance is decoupled. In a conventional MOSFET both are related because when the SD distance is reduced (in order to decrease the transit time, or to increase its inverse, the cut-off frequency fT) the gate length has to shorten. This scaling leads to a poorer control of the channel by the gate (the channel conductance gd increases) and whilst increasing fT the low-frequency voltage-gain unfortunately decreases (in spite of the every effort made in the scaling: particularly the reduction of the gate oxide thickness). This is a trivial result: unless one changes the topology of the gate, one cannot change the low-frequency gain-bandwidth product. The SGFET can vary this product due to the novel gate topology of which we can also change the distribution in order to optimize its operation.
II. PHYSICS BASED STUDY OF THE DEVICE In this work we present a preliminary study of the device operation. Our main goal here is to understand the operation principles of the transistor and to verify that the aims in the design are fulfilled. These objectives are: to decouple the need for aggressive scaling of the gate oxide thickness, tox when reducing the channel length Lg – this will prevent current leakage, to maintain a low value of the doping in the channel, ND when scaling – this will prevent mobility degradation, to avoid the degradation of the drain
G
G ND
S G
D Lg G
G S
D G
Fig. 3. Top view of a SGFET’s section. Top: Section of a 2row configuration. Bottom: Section of a 1-row configuration. The S and D regions are not shown. Grey ring-shaped regions: gate oxide. Grey dotted regions: Al. The total width of the device is NLg, N being the total number of sections.
For normalization we assume the Si channel thickness to be 1Pm. We will only consider here the nchannel case, but p-channel and complementary channels can be, in principle, built. Unless otherwise indicated, the parameters for the simulations are ND=1015cm-3 (active region doping), tox=2nm (gate oxide thickness), LSD=800nm (source to drain distance), the finger’s diameter is 120nm (for tox=2nm), Lg=280nm and Linter=240nm (in the 2-row structure, see Fig. 3 top), The gate metal is chosen to be Al (workfunction I=4.1 eV). Fig. 3 shows a schematic drawing of a unit section of the SGFET. Dependent on the needed current drive unit
Drain Current (A/micron)
sections can be attached. Simulations have shown that the current Itot through N unit sections is equal to N x IN, with IN the current through 1 unit section.
1e-4 1e-5 1e-6 1e-7 1e-8 1e-9 1e-10 1e-11 1e-12 1e-13 1e-14 1e-15 1e-16 1e-17 -1.0
1 row 2 rows
limit ourselves to the qualitative study of the influence of the most significant parameters. Fig. 4 plots the transfer characteristics for the 1 and 2 row configurations. In this figure we can confirm that by adding the second row the device’s ability for lowpower/low-voltage applications is improved: S is lowered from 71 to 66 mV/decade, and the current range in which the subthreshold current is exponential extended. TABLE I INFLUENCE OF THE GATE OXIDE THICKNESS FOR Lg=294nm
tox (nm) S (mV/dec.) Vth (mV) -0.8
-0.6
-0.4
-0.2
0.0
0.2
0.4
VGS (V)
Fig. 4. Transfer characteristics of the devices in Fig. 3. VDS=100mV.
The height of the source to channel barrier (SCB) controls the injection of carriers into the channel. In short channels the drain potential influences the SCB height. SCB lowering via the drain increases the current and is also responsible for the increase of the output conductance (gd) as the gate length is shortened (DIBL).
2 63.0 -250
4 63.0 -250
6 64.2 -259
8 64.9 -268
10 65.6 -277
In Fig. 5 the efficiency of the transconductance given by the ratio gm/IDS as a function of the gate voltage is plotted. This figure of merit measures the ability of a transistor to deliver a high gain independent of drain current sourcing. The 1-row structure exhibits a plateau value greater than 40S/A, whereas the 2-rows one is close to 60S/A. These results clearly show that the second row suppresses the parasitic drain control on the channel and helps to recover gate control.
70
-1
Efficiency of Transconductance (V )
70 60
1 row 2 rows
gm/IDS (S/A)
50 40 30 20 10 0
-1.0
-0.8
-0.6
-0.4
-0.2
0.0
0.2
0.4
VGS (V)
Lg1 = 170nm Lg1 = 240nm Lg1 = 340nm Lg1 = 440nm Lg1 = 540nm Lg1 = 640nm
60 50 40 30 20 10 0
-1,0
-0,8
-0,6
-0,4
-0,2
0,0
0,2
0,4
VGS (V)
Fig. 5. Efficiency ratio (gm/IDS) of the devices in Fig. 3. VDS=100mV.
Fig. 6. Efficiency of the transconductance (gm/IDS). VDS=100mV for different values of the gate length (Lg).
The way to mitigate DIBL is to improve screening of the drain potential. This task can be effectively accomplished in the SGFET by using two rows of gate electrodes: 2-row configuration given in Fig.3 top rather than the 1-row configuration as given in Fig.3 bottom. The role of this second row is to screen the drain potential in order to keep the SCB height independent of VDS. In principle, it is possible to work in a multigate configuration by applying different voltages to each row. For instance, the second row can be kept at as constant bias such as in a cascode gain stage. Of course, the position of the two rows modifies the device’s performance. In this work we will
In agreement with the above, from the calculations of the output characteristics, we obtain at VGS=0V and VDS=2.5V a value of gd=2.24PS/Pm for the 1-row configuration and gd=1.42PS/Pm for the 2-rows one. In Table I the influence of the oxide thickness on S and Vth is studied in the 2-row configuration. The data shows that the oxide thickness plays a marginal role in determining the value of Vth and S. This removes the need for aggressive oxide scaling as discussed above. Moreover, as the influence of this parameter on S and Vth is slight, it could at least partially lift the stringent control of tox needed in order to improve the matching. The simulations also
show that ND does not modify Vth noticeably as far as it is kept below 5.1017cm-3. This alleviates the problem of the control of the channel doping to adjust Vth, and allows the use of undoped channels in order to improve the mobility. For a given value of the finger’s diameter (this diameter will be essentially limited by the processing), the threshold voltage will be essentially determined by Lg and the gate metal. Lg will become the key parameter of the device operation as it will strongly influence the performance of the transistor. Fig. 6 plots the efficiency of the transconductance in the 2-row configuration with Lg as a parameter. The shift to the negative values of VGS as the channel opening increases clearly shows the great influence of Lg on Vth. It is also noticeable that as Lg decreases the performance is improved – in contrast to traditional short channel effects. In contrast to the huge impact of Lg scaling on threshold voltage and efficiency of transconductance, the inter-gate row distance Linter proves to have a minor influence on the performance of the device. This has important consequences for the reduction of the source-drain distance: When reducing the SD distance from 825nm to 425nm while keeping the Linter value, the DIBL is reduced from 20.5mV/V to 6.4mV/V.
III. CONCLUSIONS A novel 3D Field Effect Transistor on SOI – the screen grid FET (SGFET) – for ultra-low power applications is proposed and TCAD analysis of the device is presented. The simulations show that the definition of the gate cylinders inside the channel allow 3D-gating for excellent carrier control and creates sufficient flexibility to control short channel effects without the need for aggressive gate-oxide and doping scaling. The introduction
of a second row of gate cylinders near the drain contact controls the influence of DIBL and this double gating row configuration leads to near-ideal values for subthreshold slope, and improves overall characteristics with gate length reduction: improved transconduction efficiency without increased leakage currents due to DIBL.
ACKNOWLEDGEMENTS J.E. Velázquez thanks for financial support to Junta de Castilla y León (SA072A05) and MEC-FEDER (TEC200502719/MIC).
REFERENCES [1] T.A. Langdo, M.T. Currie MT, Z.Y.Cheng, J.G. Fiorenza, M. Erdtmann, G. Braithwaite, C.W. Leitz, C. Vineis, J.A. Carlin , A. Lochtefeld, M.T. Bulsara, I. Lauer, D.A. Antoniadis, M. Somerville, “Strained Si on insulator technology: from materials to devices”, Solid State Electron., vol. 48 (8), pp.1357 (2004). [2] K. De Meyer, M. Caymax, N. Collaert, R. Loo, P. Verheyen, “The vertical heterojunction MOSFET”, Thin Solid Films, vol. 336 (1-2), pp. 299-305, 1998. [3] D. Hisamoto, W.C. Lee, J. Kedzierski, H. Takeuchi, K. Asano, C. Kuo, E. Anderson, T.J. King, J. Bokor, C.M. Hu, “FinFET - A self-aligned double-gate MOSFET scalable to 20 nm”, IEEE Trans. Electron. Devices, vol. TED-47, pp. 2320-2325, 2000. [4] A. Schuppen, L. Vescan, M. Marso, A. v.d. Hart, H. Luth and H. Beneking, “Submicrometer silicon permeable base transistors with buried CoSi2 gates”, Electon.Lett. vol. 29(2), pp. 215-17. 1993. [5] Taurus Medici User Guide, Synopsys, Mountain View, CA, USA, 2005.
