A Novel Accumulation Mode GAAC FinFET Transistor

ECS Transactions, 18 (1) 83-88 (2009) 10.1149/1.3096432 © The Electrochemical Society

A Novel Accumulation Mode GAAC FinFET Transistor: Device Analysis, 3D TCAD Simulation and Fabrication Deyuan Xiaoa b, MinHwa Chib, David Yuanc, Xi Wanga, Yuehui Yua, Hanming Wub, Joseph Xieb a

Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences, Shanghai 200050 b Semiconductor Manufacturing International Corporation, Shanghai 201203 c Synopsys Inc., Shanghai 200050 We report the analysis and TCAD results on gate-all-around cylindrical (GAAC) FinFETs with operation based on channel accumulation. GAAC FinFETs operating in accumulation mode in which the current in accumulation is flowing across the whole cylinder-shaped Si body, have high mobility, reduced lowfrequency noise and short-channel effects, increased the threshold voltage and avoid effects due to depletion of poly-Si gates. The Ion/Ioff ratio of the device can be larger than 106, a key parameter for device operation. Introduction

The continuously scaled gate length in conventional planar CMOS transistor is increasingly difficult in maintaining high drive currents with low off-current leakage as well as stability of threshold voltage. The short-channel effect is known degrading device performance and sets a limit for further scaling down conventional planar CMOS devices. One key development for further scaled down CMOS transistors is a stronger control of the channel conductance by the gate electrode instead if influence of the fringe field from the drain electrode. For SOI devices, from partial depletion mode to full depletion mode, this is achieved by reducing the silicon body thickness. Double gate transistor1 and trigate transistor2 are alternative device structures with stronger gate control over channel area (than planar CMOS) and lead to excellent scalability into short channel beyond the 32nm node. Gate-All-Around FinFET is one of the most promising structures to extend the scaling of the CMOS devices as it provides the best channel electrostatic control, which improves further with the shrinking of channel thickness.3-5 Recently, there are numerous interests in SOI MOSFETs working in accumulation mode.6-8 Similar to thinbody SOI MOSFETs in volume inversion mode, thin-body SOI can also operate in accumulation mode. The current in accumulation is flowing across the whole Si body, which is beneficial to increase the mobility, reduce the low-frequency noise and the short-channel effects as compared to FD SOI MOSFETs, increase the threshold voltage and avoid effects due to depletion of poly-Si gates. In this work, we propose a novel GAAC FinFET device with operation in accumulation mode, where the analytically calculated I-V characteristics agreed well with 3D TCAD simulation. Device Architecture Figure 1 illustrates a simplified perspective and cross-sectional view of a GAAC FinFET device structure. The source, drain and the channel regions are doped with the

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ECS Transactions, 18 (1) 83-88 (2009)

same type of dopant. Thus, there is no pn junction along with the channel length and reduce the leakage current. The device cross-sectional views along and perpendicular to the channel directions are shown in Figure 2. The ultimate GAAC FinFET device implements a physical oxide with a large bandgap to isolate the gate from the conducting channel area. By applying gate voltage to accumulate or deplete majority carriers in the channel, we can modulate the channel conductance for controlling the channel current as a switch between the source and drain.

Figure 1 Simplified perspective (left) and cross-sectional (right) view of a GAAC FinFET device architecture direction

Figure 2 GAAC FinFET cross-sectional views: (a) along the channel direction; (b) perpendicular to the channel Device Analysis According to the symmetry aspect of the cylindrical device structure, we choose the cylindrical coordinate as described in Figure 2b for analysis. The surface potential and electric field distribution can be derived by solving the Poisson's equation in the silicon pillar. The electric field at a radial of r can be expressed by, eN 1 E (r ) = − A [r − (a − w) 2 ] , (0