We analyze an existing AGC algorithm that uses slicer input for deriving the gain error signal and show that it suffers from am- biguity in the control direction of ...
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IEEE TRANSACTIONS ON MAGNETICS, VOL. 36, NO. 5, SEPTEMBER 2000
A Novel AGC Scheme for DFE Read Channels Qing-Wei Jia, Member, IEEE, and George Mathew
Abstract—The problem of automatic gain control (AGC) for DFE (decision feedback equalization) read channels is addressed. We analyze an existing AGC algorithm that uses slicer input for deriving the gain error signal and show that it suffers from ambiguity in the control direction of AGC loop due to the presence of feedback equalizer. This could result in slow convergence and possible instability problems. A new AGC scheme has been proposed to overcome this ambiguity and it uses the sign of the forward equalizer output instead of slicer input to control the AGC loop direction. Simulation results show good acquisition and tracking performances of the new scheme under noisy circumstances. Index Terms—Automatic gain control, decision feedback equalization, magnetic recording, multi-level DFE.
I. INTRODUCTION
Fig. 1. Structure of current AGC scheme for MDFE.
A
UTOMATIC gain control (AGC) plays a very important role in read channels used in magnetic recording applications. AGC helps to stabilize the dynamic range of the signal supplied to the filter sections and detector of the read channel. Since the actual gain in the channel output is not known, one needs to devise clever ways to obtain information on the real gain error for driving the AGC loop. The approach used for obtaining the gain error will depend on the type of detection principle used for recovering the data bits (e.g. peak detection, decision feedback equalization (DFE), partial response). In the partial response case, the gain error is derived based on the error obtained from a multi-level slicer at the output of the equalizer [1]. In peak detection schemes, the gain error is derived by comparing the average read-pulse amplitude against a known reference [2]. In this paper, we consider the case of DFE detectors. Derivation of gain error by comparing the forward equalizer input to a desired reference was reported in [3]. However, in DFE schemes, it appears more natural and convenient to use the error at the slicer input (see Fig. 1) for deriving the gain error. Recent publications on multi-level DFE (MDFE) follow this approach [4]–[6]. In this paper, we first show that the sign of the error at the slicer input may not always reflect the sign of the real gain error due to the presence of decision feedback. In [4]–[7], bit decisions are used to correct this sign. However, we show that it still fails to give the correct sign. This could cause ambiguity in the control direction of AGC loop and possible instability problems. In this paper, we propose a new AGC scheme for DFE read channels, which overcomes the above ambiguity. We also prove the stability of this scheme, and present a simple implementation Manuscript received February 14, 2000. This work was supported by M3DFE consortium sponsored by Data Storage Institute, IBM, Fujitsu, Hitachi, Texas Instruments and Tektronix. The authors are with the Coding and Signal Processing Division, Data Storage Institute, DSI Building, 5, Engineering Drive 1, Singapore 117608. Publisher Item Identifier S 0018-9464(00)08390-4.
approach. We use MDFE for our study here. However, the proposed scheme can be easily configured for any DFE channel. II. DIRECTION AMBIGUITY IN CURRENT AGC SCHEME We examine the AGC scheme reported in [4]–[6] where the gain error is derived based on the error at the slicer input. This is a decision directed algorithm. Further, since the ideal slicer input in MDFE has 4 levels, the gain error is derived using samples which correspond to transitions in the data bits [5], [6]. Fig. 1 shows the structure of this AGC scheme. The input of AGC loop filter is given by if and
Using as
(1)
, this can be further expanded
if
(2)
is the real gain error, is the ideal output where is the ideal gain normalized to 1, and of forward equalizer, is the actual gain. For AGC loop to work properly, it is necessary that the sign is same as that of . But, we note from (2) that is of data-pattern dependent, namely, sign
sign
sign
(3)
is different from that Hence, it may happen that the sign of . For example, suppose , of the real gain error . Then, for the AGC loop to resulting in But, it can be easily function properly, we must have shown that for a Lorentzian channel with user density 2.50 and 9 feedback taps, the data pattern results in . That is, even though the gain is smaller than the desired value 1, the AGC
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JIA AND MATHEW: A NOVEL AGC SCHEME FOR DFE READ CHANNELS
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If the loop is stable, then should approach zero in the limit if the channel gain is a constant (or slowly time-varying). and . From (5) and (6) To verify this, let we have (7) Taking the derivative of
with respect to time , we get
(8) Fig. 2. Structure of new AGC scheme.
It can be shown that loop is being driven to decrease it further instead of increasing it. This ambiguity in the control direction will slow down the convergence and may cause possible instability problems in the AGC loop.
(9) with
a positive value. Then it follows from (7) and (9) that
III. NEW AGC SCHEME
(10)
We note from (3) that the ambiguity in the control direction of AGC loop occurs whenever the forward equalizer output and decision are of opposite sign. We recall from [1] that even though an equation similar to (1) is used to derive the gain error in partial response scheme, such an ambiguity does not occur there since the signs of equalizer output and slicer output are always identical. In the DFE case, however, these signs can be different because of the presence of the feedback equalizer. Whenever the data pattern is such that and sign sign , then the forward equalizer output and decision will be of opposite signs, resulting in the control direction ambiguity. Here, denotes the output of feedback equalizer. It follows from (3) and the above discussion that the control direction ambiguity can be resolved if we use the sign of forward equalizer output instead of slicer input to control the AGC loop direction. Thus, we get the new AGC loop input as sign
If the overall gain implies that
, then . In turn, this implies that
. This
(11) will converge to a constant, implying Thus, the overall gain , i.e., that the AGC loop is stable. If , from (4) and (5) we get (12) Hence, it follows from (6) that (13) Equation (9) implies that will increase exponentially. Hence, in finite time the overall gain will satisfy
sign if
(14)
(4)
sign and the ambiguity Clearly, we have sign problem is overcome. Fig. 2 shows the structure of the new AGC scheme, which uses an extra slicer to obtain the sign of forward equalizer output. IV. STABILITY ANALYSIS OF NEW AGC SCHEME We choose a first order loop filter given by (5) is the loop gain. The model for the gain-controlled where amplifier is chosen to be (6) and is the output of the loop filter [7], [8]. It where is well known that VGA amplifiers with exponential characteristics could maintain a more stable AGC loop bandwidth than that with linear type [9].
V. IMPLEMENTATION ISSUES Compared to the earlier AGC scheme given in Fig. 1, the structure of the new AGC scheme given in Fig. 2 requires an extra slicer for correcting the sign of AGC loop input. If the sample and hold in the original detector is at the slicer input, then it is necessary to have another sample and hold for the slicer at the forward equalizer output. We are assuming a fully analog implementation. We now show that a simple digital logic can be designed to replace this extra hardware required. As mentioned already, the sign ambiguity in the AGC control . In other words, direction occurs only when sign ocif we can detect the instances at which sign curs, we can correct the ambiguity problem in the original AGC in (1) by . This can scheme by replacing the decision be done by taking a close look at the outputs of forward and feedback equalizers for different data patterns. For example, for
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IEEE TRANSACTIONS ON MAGNETICS, VOL. 36, NO. 5, SEPTEMBER 2000
a Lorentzian channel at user density 2.5 and 9 feedback taps, will occur if the data pattern the condition sign assumes any of the following:
Then the occurrence of sign using the following logic
can be identified
(15) Though we can simplify the hardware by using the above logic, we have the following remarks on this. First, since the bit decisions tend to be more unreliable at very low signal to noise ratios (SNR), the reliability of the above logic in detecting the will suffer under low SNR’s. occurrences of sign Second, the logic given above is a function of the channel characteristics and the number of feedback taps. VI. SIMULATION RESULTS The dynamic behavior of the proposed AGC scheme for acquisition and tracking has been studied using computer simulations. For the sake of illustration, we present the results for a bad condition where the original gain in the channel is only 20% of the ideal value. The AGC scheme in Fig. 1 failed to work under this situation. Fig. 3 shows the acquisition and tracking performances of the new AGC scheme. Observe that the output of the converges fast to its steady state gain-controlled amplifier value 5. To illustrate the tracking performance, we changed the gain in the channel at instant = 1000 from 0.2 to 0.4. Observe that the new scheme responds fast to reach the new steady state value 2.5. VII. CONCLUSION A new AGC scheme for DFE read channels is proposed and the loop stability analysis is given. Simulation results show that
Fig. 3. Simulation results of new AGC scheme (SNR = 30 dB).
the new scheme has good acquisition and tracking performances under noisy circumstances. REFERENCES [1] R. D. Cideciyan, F. Dolivo, R. Hermann, W. Hirt, and W. Schott, “A PRML system for digital magnetic recording,” IEEE J. Selected Areas Commun., vol. 10, pp. 38–56, Jan. 1992. [2] R. Gomez and A. A. Abidi, “A 50-MHz CMOS variable gain amplifier for magnetic data storage systems,” IEEE J. Solid-State Circuits, vol. 27, pp. 935–939, June 1992. [3] W. L. Abbott and J. M. Cioffi, “Timing recovery for adaptive decision feedback equalization of the magnetic storage channel,” in Proc. GOLBECOM Conf., San Diego, CA, USA, Dec. 1990, pp. 1794–1799. [4] J. G. Kenney, “A system architecture for multi-level decision feedback equalization,” IEEE Trans. Magn., vol. 30, pp. 4218–4220, Nov. 1994. [5] J. G. Kenney and R. W. Wood, “Multi-level decision feedback equalization: An efficient realization of FDTS/DF,” IEEE Trans. Magn., vol. 31, pp. 1115–1120, Mar. 1995. [6] Y. X. Lee, L. K. Ong, J. J. Wang, and R. W. Wood, “Timing acquisition for DFE detection,” IEEE Trans. Magn., vol. 33, pp. 2761–2763, Sept. 1997. [7] D. N. Green, “Global stability analysis of automatic gain control circuits,” IEEE Trans. Circuits Syst., vol. 30, pp. 78–83, 1983. [8] , “Lock-in, tracking and acquisition of AGC-aided phase-locked loops,” IEEE Trans. Circuits Syst., vol. 32, pp. 559–568, 1985. [9] C. K. Wang and P. C. Huang, “An automatic gain control architecture for SONET OC-3 VLSI,” IEEE Trans. Circuits Syst., vol. 31, pp. 24–29, 1996.
