A Novel Approach to Memory Power Estimation Using Machine Learning Mel Stockman#1, Mariette Awad#2, Rahul Khanna*3, Christian Le*4, Howard David*5, Eugene Gorbatov*6, Ulf Hanebutte*7 #
Electrical and Computer Engineering Department, American University of Beirut Beirut, Lebanon 1
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[email protected] [email protected]
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Intel Corporation, 2111 NE 25th Ave., Hillsboro, OR 97124, USA.
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{ rahul.khanna, christian.le, 5howard.david, Abstract— Reducing power consumption has become a priority in microprocessor design as more devices become mobile and as the density and speed of components lead to power dissipation issues. Power allocation strategies for individual components within a chip are being researched to determine optimal configurations to balance power and performance. Modelling and estimation tools are necessary in order to understand the behaviour of energy consumption in a run time environment. This paper discusses a novel approach to power metering by estimating it using a set of observed variables that share a linear or non-linear correlation to the power consumption. The machine learning approaches exploit the statistical relationship among potential variables and power consumption. We show that Support Vector Machine regression (SVR), Genetic Algorithms (GA) and Neural Networks (NN) can all be used to cheaply and easily predict memory power usage based on these observed variables. Keywords— Support Vector Machine, Genetic Algorithm, Neural Network, Power Estimation, Machine Learning
I. INTRODUCTION When attempting to reduce power on a chip, a flexible candidate for selective reduction is memory due to its ability to preserve data even in low-power states and the fact that only small parts of it need to be active simultaneously [1]. In order to design systems and develop algorithms for selectively reducing power, it is necessary to analyse the patterns of usage for individual components such as memory. Power metering can be established using an extensive network of instrumented power sensors but can be expensive to build and requires an extensive network of system interconnects with certain expectation of accuracy, bandwidth and response time. High accuracy translates into high linearity of analog sensors over a large range that can easily become expensive. Since sensors perform linearly only within a limited operating range, it makes them inaccurate in the regions of high or low currents. Further, environmental and electrical variations (temperature, humidity, environmental impurities, electro-migration) and aging can cause inaccuracies over time, which will require a frequent re-calibration of electrical components. At the same time, while meters can easily be built at a physical component level (CPU, Memory, Power Supply), they are rather difficult
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eugene.gorbatov,
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ulf.r.hanebutte}@intel.com
to build at a virtual level. For example, in a multi-partition system, instrumentation is rendered useless if all the partitions are powered by a single power supply-unit with a single instance of power instrumentation. II. PRIOR RESEARCH Various approaches have been applied to estimate power at the circuit as well as the architectural level [2-6]. These approaches work well for offline analysis and simulations, but are extremely slow to be used in real-time power monitoring for systems deployed with large commercial workloads. Earlier works by Bellosa et. al. [7] focused on the relationship between certain parameters such as memory/cache references, instructions per cycle, integer/floating point operations, etc. and total power consumption in the Pentium II. They used embedded counters to collect metrics which were then used to linearly model the energy consumption. Isci, et al [8] used dynamic voltage and frequency scaling (DVFS) as a power management technique on multi cores. They enforced global power constraints by regulating the program execution based on sensor measurements. Contreras et.al [9] also used a linear model on performance counters to predict average power consumption to within 4% of the actual measured CPU power consumption. Singh et. al. [10] used piece-wise linear functions on data from benchmark runs to calculate real time power estimations achieving median errors of 5.8%, 3.9%, and 7.2% for the NAS [11], SPECOMP [12] and SPEC 2006 [13] benchmark suites respectively. Economou et al. [14] predicted power also using benchmarks to profile hardware components (CPU, hard disk, memory). Their estimates had a 10% average error. In [15], Yun et. al. predict power consumption using linear regression modelling based on a number of power and performance measures determined from running benchmark applications. They show an average estimation error of 4% as compared to the actual power usage. Analytical models exist for approximating memory power based on system parameters such as cache hits, misses, reads and writes. However, their accuracy ranges from 2% to 30% [16]. Other estimates such as in [17] calculate the memory power based on general assumptions regarding percentage of output cycles reading/writing data as well as a number of other criteria.
Our work differs from previous works in two ways, first we use a non-linear rather than linear approach and secondly our approach diverges from classical calibration based methods in that we make no assumption of the relative significance of any variable or on the load of the system. Additionally, our results show a high accuracy with mean squared error (MSE) 0.047.
nftool was used. The GA approach used a crossover probability of 60%, a mutation probability of 11%, and a population size of 80. Table 2 shows our results. The NN and SVR approaches showed very high accuracy of MSE 0.047 and 0.063 while the GA model had MSE 1.1. The actual and predicted power for the best predictor, the NN, is shown in Fig. 1.
III. EXPERIMENTS AND RESULTS The data set taken from [18] consists of 17765 samples of the memory activity counters described in Table 1 with the actual corresponding power consumed in watts as measured directly by a memory power riser. For the SVR model we used an rbf kernel performing a grid search to find the best parameters. The data was normalized and cross validation (CV) was performed. The NN model had two hidden layers with 5 nodes per layer. The data was separated into 70% training set, 15% test set, and 15% validation set. MATLAB
IV. CONCLUSION In our work, we have shown that the machine learning techniques SVR, GA and NN are highly accurate for predicting power consumption based on memory activity counters. These approaches are significantly less costly and complex than a hardware solution and can be calculated at program run time. Follow on research may include experimenting with a larger data set and different activity counters.
Figure 2. Power estimates using NN model TABLE I MEMORY POWER MODEL PARAMETERS
Activity Activate(A) Read (R) Write (W) CKE=High CKE=Low
Units nj/Activate nj/Read nj/Write mW mW
TABLE II ACCURACY RESULTS FOR POWER PREDICTION
Model NN SVR GA
MSE 0.047 0.063 1.1
ACKNOWLEDGEMENTS This work is partly supported by MER, a partnership between Intel Corporation and King Abdul-Aziz City for Science and
Technology (KACST) to conduct and promote research in the middle east and the University Research Board at the American University of Beirut. The authors acknowledge the feedback of Prof. H. Hajj on this work.
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