A Novel Autonomous Control Scheme for Parallel

A Novel Autonomous Control Scheme for Parallel, LCL-Based UPS Systems Mohammad Bani Shamseh

Atsuo Kawamura

Teruo Yoshino

Department of Electrical and Computer Engineering Yokohama National University Yokohama, Japan Email: [email protected]

Department of Electrical and Computer Engineering Yokohama National University Yokohama, Japan Email: [email protected]

Power Electronics Systems Division Toshiba Mitsubishi-Electric Industrial Systems Corporation Tokyo, Japan Email: [email protected]

Abstract—This paper proposes a novel autonomous control scheme for equal load current distribution between n parallelconnected, LCL-based, three phase UPS units. The control is based on varying the capacitor reference voltage of each inverter as a function of its own output current, without exchanging information between the inverters. The load voltage is maintained fixed at the specified reference value. The control method is fast, precise and robust against load variations. Capacitor voltage and capacitor current are used in a dual-loop control at each inverter. The validity of the proposed method is verified by simulation and experiments on a system of two 5-kVA parallel inverters.

I. I NTRODUCTION Paralleling of inverters or UPS units is often used to improve thermal management, reliability, redundancy, and size reduction [1]. However, the advantages of paralleling of energy sources comes at the expense of adding additional constraints: all inverters should have the same output voltage amplitude, frequency, and phase. Furthermore, output currents of all inverters must be equal, or distributed proportional to their respective ratings [1], [2]. To achieve equal load distribution, many methods have been proposed in the literature. A well-established control method which mimics the parallel operation of large generators is called the Droop method [3]. Although it does not require interconnecting wires between the inverters, this method has several drawbacks, such as: slow dynamic response, and unequal harmonic current distribution [1]. Some measures have been taken in an attempt to overcome these drawbacks. The reactive power sharing-accuracy has been improved in [4] by means of synchronization signals communicated through a low-bandwidth communication channel. However, this method required extra communication channels. Another method has been proposed in [5] in which information about output reactive power is injected from the central controller. This approach requires additional cost for power line signalling or smart meters. In [6], three regulators are used: voltage, reactive power, and active power regulators. A sparse communication network is used across the network to exchange information. Each controller processes its local and neighbors information to update its voltage magnitude and frequency.

The other method is the instantaneous average currentsharing control, which requires interconnecting wires. This method exhibits superior performance to the former method, especially under non-linear load conditions [2]. Nevertheless, the interconnecting wires put limitations on the maximum distance between the units, and introduces time delays into the system, which affects the dynamic performance of the system and might cause instability problems. To achieve autonomous load-sharing control, each UPS should rely only on locallymeasured variables [7], [8]. Single-loop control of inverters is subject to grid background noise and exhibits a tradeoff between control dynamics and steady-state performance [9]. Multi-loop control is preferred since it provides damping effects and can overcome the limitations of single-loop control. Various implementations of multi-loop control have been proposed in the literature. For example, dual loop control with load voltage and loadside current [10], grid current control of LCL-based three phase inverters [11], double-loop control with grid current and capacitor current feedback loops [12], capacitor voltage can also be used; in this case the load-side inductor is usually treated as part of the feeder line [9]. This paper proposes a novel method for autonomous control of parallel UPSs. The control method depends only on local variables to achieve load current sharing without extra communication links between the parallel units as in the instantaneous average current sharing scheme. Moreover, the load voltage and frequency are not varied as in the Droop method. Each inverter is connected to a LCL filter. The load-sharing control scheme is simple and relies on using the output current of each inverter unit to adjust its own reference capacitor voltage, while maintaining a fixed load voltage. For the control of each inverter, multi-loop control with capacitor voltage loop and capacitor current minor loop are used. II. PARALLEL I NVERTERS AND CURRENT CIRCULATION This section analyses a system of n parallel AC voltage sources connected to a load. Equations for load current and circulating currents between the inverters are derived. Suppose that there are n inverters connected in parallel and connected to a load, as shown in Fig. 1. And suppose that all

Fig. 1. n-parallel power sources connected to a load.

Fig. 2. Two inverters with LCL filters connected in parallel.

inverters have the same output impedance, which is equal to Z. The impedance of the load is ZL , and the output voltages of the inverters are E1 , E2 , ..., En . As shown in Fig. 1, each inverter unit supplies part 0 of the load current (I1 for inverter 1), and circulating current components between this unit and other units (IC12 , IC13 , ..., IC1n ) [13]. The components of output current of inverter 1 are shown in Fig. 1. The following equations show the details of output currents from each inverter:  0 I1 = Ic12 + Ic13 + ... + Ic1n + I1    0 I = −I + I + ... + I 2 c12 c23 c2n + I2 0  I3 = −Ic13 − Ic23 + Ic34 + ... + Ic3n + I3   0  In = −Ic1n − Ic2n − Ic3n − ... − Ic(n−1)n + In

(1)

Notice that the load current (IL ), which is equal to the summation of all individual currents from the parallel units, will include only the summation of the last terms in (2) since the circulating current components will cancel each other out. 0

0

0

Applying KVL to the circuit in Fig.1:  E1 = ZI1 + ZL IL    E = ZI + Z I 2 2 L L  E = ZI + Z 3 3 L IL    En = ZIn + ZL IL , .

I1 =

E1 Z+

Z n−1 //ZL

−

Z n−1 //ZL



Z Z+

Z n−1 //ZL

(3)

 [E2 + ... + En ] .

(5) Similarly, equations of output currents of all other units can be derived in the same manner as in (5). Equation (5) can be simplified and written in a more general form. For n parallel inverters with output voltages E1 , E2 , ..., En , output impedance equals to Z, and a load impedance of ZL , the output current of unit i is: 

where Icij is the circulating current from unit i to unit j, 0 and Ii is the load-current component from unit i. The circulating current components of each unit can be lumped into a single term, and (1) is alternatively written as:  0  I1 = Ic1 + I10  I = I + I 2 c2 2 (2) 0 I3 = Ic3 + I3   0  In = Icn + In .

IL = I1 + I2 + ... + In = I1 + I2 + ... + In .

Using the superposition principle, the current of inverter 1 is:

Ii =

n X



Ei ZL nEi − Ej  . + Z + nZL Z (Z + nZL ) j=1

(6)

The current of unit i can be divided into two components as follows: 0 1) Load current component (Ii ): 0

Ii =

Ei . Z + nZL

2) Circulating current component:   n X ZL nEi − Ici = Ej  . Z (Z + nZL ) j=1

(7)

(8)

The circulating current component depends on the difference between the output voltages of the parallel inverters. If all inverters had the same output voltage, the circulating current will be zero, which is the ideal case. III. M ULTI - LOOP CONTROL OF INVERTERS

(4)

Fig. 2 shows the circuit diagram of two parallel, three-phase inverters connected to a load through LCL filters. Where L0 and L1 are the inverter-side and load-side inductors respectively, R0 and R1 are their series resistances, and C is the

TABLE I R EPRESENTATION OF THREE - PHASE QUANTITIES IN STATIONARY REFERENCE FRAME AND SYNCHRONOUS REFERENCE FRAME .

Stationary reference frame [va , vb , vc ]T √   2V sin θ √ = √2V sin(θ − 120◦ ) 2V sin(θ + 120◦ )

vabc =

Synchronous reference frame

vdq = =

[vd , vq ]T √  √2V cos γ 2V sin γ

TABLE II S PECIFICATIONS OF ONE INVERTER UNIT.

(a)

Specification Vdc VL Switching frequency Output frequency Rated power

Fig. 3. (a) Dual loop control of capacitor voltage and current in synchronous frame, (b) synchronous frame control block diagram.

capacitance. Compared to L filters, high-order passive filters provide a more cost-effective solution to PWM switching harmonics [14]. However, the inherent resonance of LCL has the tendency to destabilize the system [14]. A direct way to damp the LCL resonance is to add a passive resistor. This solution is simple for implementation and reliable, but introduces additional power loss into the system. Another method to damp the resonance of the LCL filter is active damping [9]. In this paper, as shown in Fig. 3a, the control mechanism consists of two loops: • •

Inner capacitor current loop. Outer capacitor voltage loop.

The dual-loop control is performed in the dq-synchronous frame because the PI controller holds an infinite gain for dc signals, forcing the system to track the dc reference without steady-state error [15]. Voltage and current three phase signals are transformed into dc quantities by means of Park transformation [16]:

Component R0 L0 C R1 L1



Value 40 mΩ 0.6 mH 40 µF 55 mΩ 1.2 mH



2 1 −1/2 −1/2 Va  Vb  √ √ 3/2 3 0 − 3/2 Vc

(9)

     Vd sin(θref ) cos(θref ) Vα = Vq cos(θref ) − sin(θref ) Vβ

(10)

  Vα = Vβ

(b)

Value 300 V 100 Vrms 15 kHz 50 Hz 5 kVA

where θref is the reference phase angle of the grid which can be extracted by means of PLL. Table I shows the three phase voltage signals in stationary reference frame (vabc ) and their equivalent dc quantities in the synchronous frame (vdq ). The dc quantities in the synchronous frame have the same amplitude as the three phase signals. In the dq-frame, the phase is γ, where γ = θ − θref . If θ = θref , as in the case of load √ voltage which is synchronized with the grid, then vdq = [ 2V, 0]T . For other voltage/current quantities, their equivalent dc values in the synchronous frame will depend on their phase shift from the reference frame. The block diagram of the closed-loop control of the inverter is shown in Fig. 3b. The inner loop is the capacitor current loop. The open-loop transfer function of the inner control loop with the capacitor current at the output is: GIc = Kpwm

Cs(sL1 + R1 + RL ) as3 + bs2 + es + d

(11)

where a = CL0 L1 , b = L1 R0 + L0 (R1 + RL ), e = L0 + L1 +R0 C(R1 +RL ), d = R0 +R1 +RL , and Kpwm = Vdc /2. RL is the load resistance. The specifications of one inverter unit are shown in Table II. In Fig. 4, the Bode plot of the open-loop transfer function GIc is demonstrated. The figure shows that the inner loop has a phase margin of 90◦ and a theoretical gain margin of infinity. However, to avoid excessive gain and to produce an immune system against switching noise, the gain of the inner current

(a)

(b)

Fig. 6. (a) Representation of two parallel inverters connected to a load, (b) phase diagram of inverter 1 (quantities are not to scale). Fig. 4. Bode plot open-loop transfer function of capacitor current loop.

The voltage loop has a gain margin of 60 dB and a phase margin of 53.3◦ . IV. PROPOSED AUTONOMOUS CONTROL

Fig. 5. Bode plot of open-loop transfer function of capacitor voltage loop with kc = 0.02, and ki = 2000.

loop is chosen as kc = 0.02. The open-loop transfer function of the outer voltage loop with a PI controller is: Gv = GP I .

kc GIc 1 . 1 + kc GIc Cs

(12)

In this section, an autonomous control method for n parallel UPS units will be demonstrated. In Section III, stability of an inverter with dual-loop control with capacitor voltage in the outer loop and capacitor current in the minor loop is discussed. The reference capacitor voltage was assumed to be constant. This section discusses the generation of the reference capacitor voltage based on an autonomous control scheme. The proposed autonomous control scheme is based on varying the voltage of the capacitor of the LCL filter as a function of the output current of the inverter. Fig. 6a shows the representation of two parallel sources connected to a load through an inductor (L1 ) and its series resistance (R1 ). The voltage of the source represents the voltage of the capacitor (E1 and E2 in Fig. 2). Notice that the load voltage (VL ) has a zero phase since it is synchronized with the grid voltage. Fig. 6b shows the phasor diagram of some quantities related to inverter 1. The load voltage (VL ) has a zero phase, and I1 has a phase shift from the zero reference. E1 , which is the output voltage of inverter 1, equals to the summation of load voltage and voltage drop on the inductor and its series resistance:

where GP I is the transfer function of the PI controller: ki GP I = kp + . (13) s Fig. 5 shows the Bode plot of the open-loop transfer function of the capacitor voltage loop, Gv , for kc = 0.02. To increase the stability margin of the system, a lead compensator is added in cascade with the PI controller in the voltage loop (Hd in Fig. 3). The transfer function of the lead compensator is: HT =

1 + τ1 s 1 + τ2 s

(14)

where τ1 > τ2 . In this paper τ1 = 100 × 10−6 , τ2 = 20 × 10−6 .

E 1 = V L + I 1 (R0 + jωL1 ) .

(15)

The vector of E1 is shown in Fig. 6b which has a phase angle of δ1 . The following equations describe the operation of the proposed autonomous control scheme:   Iiref d = Iid (16) Iiref q = 0   E iref = V Lref + Z.Iiref d where Iid is the d-component of the output current of unit i, Iiref d and Iiref q are the dq-components of the reference output current of unit i, E iref is the reference capacitor voltage

V. STABILITY ANALYSIS The time average model of the system of two parallel inverters in Fig. 2 in synchronous dq reference frame is:         1 Uid − Eid d I0id −R0 /L0 ω I0id   + =   U − E −ω −R /L I0iq I  iq iq 0 0 0iq dt L 0                 d Eid = 1 I0id − Iid + 0 ω Eid

dt Eiq

C I0iq − Iiq

−ω

0

           d Iid 1 Eid − VLd  −R1 /L1   + =   E − V −ω I iq Lq iq dt L1   

Eiq

ω −R1 /L1



Iid Iiq



(19) Fig. 7. Block diagram of UPS 1 with proposed autonomous control.

of unit i, VLref is the reference load voltage, and Z is the impedance of the load-side inductor (Z = R1 + jωL1 ). The reference dq components of the capacitor voltage can be represented based on (16) as follows: (

E1ref d = VLref + R1 I1d E1ref q = ωL1 I1d .

(17)

The d-component of the inverter’s output current is used as the d-component of the reference current, the q-component of the reference current is set to zero. Next, the reference capacitor voltage is calculated using the reference current and the reference (fixed) load voltage. As shown in Fig. 6b, I1d is the d-axis component of I1 . This current is used to calculate E1ref , which is then sent to the double loop controller in Fig. 3b. The capacitor voltagee will follow the reference voltage, and as a result the output current of the inverter will change. The new output current is then used to calculate a new reference voltage. The process continues until the system converges to the following equilibrium state:   Iref = I1 = I2 = ... = In = Iload /n (18) E 1 = E 2 = ... = E n = V Lref + Z.I ref   V L = V Lref Fig. 7 shows the block diagram of the autonomous control method for UPS 1. The UPS uses a PLL (phase locked loop) to generate the reference phase of the grid (θref ). The reference phase is used to transform the output current of UPS 1 to the synchronous frame. It is also used to transform the capacitor voltage and capacitor current to the synchronous frame. The d-axis component of the output current (I1d ) is used as the reference current, as described in (17). The output of the autonomous control block (E1ref dq ) is used for the multi-loop control to generate the PWM gate signals.

where Uidq is the dq-axis components of the PWM outputs of the inverters, i = 1, 2 denotes the index of the inverter. The two inverters have the same LCL filter parameters. Other current and voltage variables are as shown in Fig. 2. The PWM output voltage of the inverter, Uidq , is represented as:   Z Uidq = Kpwm kc kp eidq + kc ki eidq − kc Ic (20) where eidq is the voltage error signal (e1dq = E1ref dq − E1dq , e2dq = E2ref dq − E2dq ). Eiref dq is as shown in (17). A complete state space model of two parallel inverters operating under the proposed scheme around the equilibrium point can now be derived based on the time average model . Using (17), (19), and (20), and applying small signal perturbations, the state space model in matrix form can be described as: 1 ∆X˙ = A∆X + ∆U L0

(21)

where ∆X is the state vector, ∆X = [∆i01d ∆i01q ∆E1d R ∆E1q ∆i1d R∆i1q ∆e1d ∆e1q ∆i02d ∆i02q ∆E2d ∆E2q ∆i2d ∆i2q ∆e2d ∆e2q ]T , ∆U is the system input, ∆U = [∆U1d ∆U1q ∆U2d ∆U2q ; ]T , A is the state matrix. The system input, ∆U , can be represented in terms of the state variables. Based on (17), (19), and (20), the system input is represented as: ∆U = B∆X. Matrices A and B are shown in (23) and (24). The closed-loop system can now be represented as:   1 ˙ B ∆X. ∆X = A + L0

(22)

(25)

The stability of the system can be investigated by calculating the eigenvalues of (25). Fig. 8a shows the poles of the system. All poles are in the left hand plane, which proves that the system is stable. The poles are divided into three groups to facilitate the analysis. Fig. 8b shows the effect of increasing the gain of the current loop (kc ) on the low frequency poles (g1 and g2 ). Increasing kc moves the poles further to the left which makes the system more stable.

(a)

(b)

(c)

Fig. 8. (a) Eigenvalues of a system of two parallel UPS units, (b) effect of increasing kc , (c) effect of increasing Kp .

 −R

0

L0



Aii A= Aij

 B1 B= 0

B2 0

0 B1

 −ω   1  C   Aij  0 , Aii =  Aii  0   0   0 0

0 B2

T    B −Kc , 1 = B2 0

ω −R0 L0

−1 L0

1 C

0 0 −ω

0 0 0 0

0 −1 0

0

0 −Kc

1 L1

0 −1 L0

ω 0 0 1 L1

0 −1

−Kc Kp 0

0 0 − C1 0 L − R1L−R 1 −ω R1 ωL1

0 −Kc Kp

0 0 0 − C1 ω L − R1L−R 1 0 0

0 0 0 0 0 0 0 0

 0 0   0    0  , Aij = 0 . 0  0  0 0

Kc (1 + R1 Kp ) 0 Kc Kp ωL1 Kc

Kc Ki 0

(23)

 0 . Kc KI

(24)

Fig. 8c shows the effect of increasing the gain of the voltage loop (kp ). Low frequency poles move towards the origin, which means the stability margin of the system will be decreased and the system becomes slower. VI. S IMULATION Two UPS units are connected in parallel to a 2-kW load under the proposed control scheme. The internal block diagram of each unit is as shown in Fig. 7. The parameters of the LCL filters are shown in Table II. Fig. 9 shows the output currents and their phase. Notice how the currents quickly coalesce to the equilibrium point with equal currents. Since the load is resistive, the phase of the currents in the steady state equals to the phase of VL , which is equal to the reference phase of the grid. At t=1 s, the load is increased to 4 kW. The currents increase at the same rate and converge to a new equilibrium state at which they are equal. The increase in the output currents of the inverter is reflected as increase in the reference capacitor voltages of the two inverters. According to (17), the d-axis component of the reference capacitor voltage of an inverter is proportional to the d-component of its output current and has a slop equals to R1 . On the other hand, the q-component of the reference

Fig. 9. Output currents of two inverters in parallel and their phase, load is increased at t=1 s.

capacitor voltage is also proportional to the d-component of the output current, but has a slope of ωL1 . Generally, R1 is much smaller than ωL1 , which means that the change in Eref q is larger than Eref d . For example, for the inductors used in

Fig. 12. Waveforms of load voltage and load current.

Fig. 10. Output currents and reference voltages in dq synchronous frame.

Fig. 13. Load rms voltage and its phase.

VII. EXPERIMENTS Fig. 11. Output voltages of the inverters and their phase angles.

the experiment, R1 = 40 mΩ and ωL1 = 0.38 Ω. Fig. 10 shows the dq components of the output currents and reference voltages of the two parallel inverters. Notice how the change in the d component of the output currents is quickly reflected onto the reference voltages. Notice also that the change in the d components of the reference voltages of the two inverters due to load increase is smaller than the change in the q components (∆Eref d = 0.3 V, while ∆Eref q = 1.9 V). Fig.11 shows E1 , E2 , δ1 and δ2 . The output follows the reference and the stability of the system is guaranteed even under load variation. The waveforms of the load voltage and load current are shown in Fig. 12. The two waves are in-phase and have low distortion. In Fig. 13 VLrms and the phase of the load voltage are shown. Notice that the load voltage is constant and precisely equals to the reference value. Even when the load is increased at t=1 s the distortion is negligible.

Two 5-kVA inverters are connected in parallel as shown in the configuration in Fig. 2. The experimental setup is shown in Fig. 14. The three phase grid voltage is used as the input to the inverters. Each inverter has a built-in rectifier which generates 290 V dc which is used as the input for the inverters. The control is based on TMSF28335 DSP. The load is 1 kw and the parameters of the filters are as in Table II. Fig. 15 shows E1 , E2 , I1 , and I2 . The system switches to the proposed autonomous control as shown in the figure. Notice that the output voltages and currents are equal; each inverter supplied 2.5 A current. Fig. 16 shows the load voltage. As shown in the figure VL is equal to the reference. VIII. C ONCLUSION A novel autonomous control method for equal load sharing between parallel UPS units has been proposed. The method enables paralleling of UPS systems without the need for interconnecting wires. The validity of the proposed method has been confirmed by simulation and experiments. The proposed method is based on varying the reference of the capacitor

A dual-loop control is used at each inverter. Capacitor voltage is used in the outer loop and capacitor current is used in the minor loop. R EFERENCES

Fig. 14. Experimental setup of two inverters.

Fig. 15. Experimental results of E1 , E2 , I1 , and I2 under the proposed autonomous control (50 v/div, 2 A/div, 50 ms/div).

Fig. 16. Waveform of VL under the proposed autonomous mode control (50 v/div, 10 ms/div).

voltage of each inverter as a function of its output current, while maintaining a constant load voltage and phase.

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