A Novel Design Approach for Multi-input XOR Gate ...

A Novel Design Approach for Multi-input XOR Gate Using Multi-input Majority Function Esam Alkaldy, Keivan Navi & Fazel Sharifi

Arabian Journal for Science and Engineering ISSN 1319-8025 Arab J Sci Eng DOI 10.1007/s13369-014-1387-x

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Author's personal copy Arab J Sci Eng DOI 10.1007/s13369-014-1387-x

RESEARCH ARTICLE - COMPUTER ENGINEERING AND COMPUTER SCIENCE

A Novel Design Approach for Multi-input XOR Gate Using Multi-input Majority Function Esam Alkaldy · Keivan Navi · Fazel Sharifi

Received: 24 February 2014 / Accepted: 30 May 2014 © King Fahd University of Petroleum and Minerals 2014

Abstract Great attention is paid to develop the nanotechnology fabrication techniques, but few attempts were done to develop special design techniques for the emerging nanotechnologies. In this paper, a new design approach for the multiinput XOR suitable for nanotechnologies is presented. This approach uses the multi-input majority function as a building block. The proposed method causes significant improvement in the gate level. The proposed design approach is deployed to CNFET 5-input and 7-input XOR circuit. The results show good improvements in the speed and number of devices. Keywords CNTFETs · Logic design · Majority based design · Multiple input XOR · Nanotechnology · Threshold logic

E. Alkaldy · K. Navi (B) · F. Sharifi Faculty of Electrical and Computer Engineering, Shahid Beheshti University, G.C., Tehran, Iran e-mail: [email protected] E. Alkaldy · K. Navi · F. Sharifi Nanotechnology and Quantum Computing Laboratory, Shahid Beheshti University, G.C., Tehran, Iran F. Sharifi e-mail: [email protected] E. Alkaldy Faculty of Engineering, University of Kufa, An Najaf, Iraq e-mail: [email protected]

1 Introduction The XOR gate with its multi-input form is a very important part in many applications. Therefore, an attempt to improve its design is considered as done in [1]. Another example is in [2] where the multi-input XOR gate was developed for cryptography algorithms. Moreover, the (complementary mattel oxide semiconductor) CMOS technology for fabrication is reaching to the physical limits, and reducing the transistor size to improve the performance becomes a difficult approach. Many technologies were suggested for Nanoscale integration to continue with down-scaling. These new techniques need new design methodologies. In this paper, a new design technique is proposed for the multi-input XOR gate close in nature to the way the nanotechnologies achieve logic functions. This design method depends on the majority function with its multi-input form, since most of the nanotechnologies implement logic and arithmetic circuits with the majority gate more efficiently than other logic gates implementation [3–7]. Another reason to consider the implementation of the multi-input XOR with majority function is that this Boolean symmetric function when implemented with linear threshold gate (LTG) will have the minimum number of gates [8]. And

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Author's personal copy Arab J Sci Eng Table 1 The theoretically required number of gates for N-inputs XOR Implementation method

XOR (x1 , x2 )

XOR (x1 , x2 , x3 )

XOR (x1 , x2 , . . .. . ., xn )

AND, OR, NOT (AON)

3

5

2n−1 + 1

Layered LTG (LTG-L)

3

Non-layered LTG (LTG-NL)

2

4

n+1

2

n2 + 1

Table 2 2-Inputs XOR design table x1 x2 TD1.5 SUM = 2TD1.5 + Xi Xi

TDSUM2.5

0

0

0

1

2

0

0

1

1

1

3

1

1

0

1

1

3

1

1

1

2

0

2

0

Table 3 3-Input XOR gate design table xi TD1.5 SUM = 2TD1.5 + xi x1 x2 x3

SUM TD2.5

0

0

0

0

1

2+0

0

0

0

1

1

1

2+1

1

0

1

0

1

1

2+1

1

0

1

1

2

0

0+2

0

1

0

0

1

1

2+1

1

1

0

1

2

0

0+2

0

1

1

0

2

0

0+2

0

1

1

1

3

0

0+3

1

where f is a multi-input function in which each input, xi ∈ {0, 1}, i ∈ {1, 2, . . ., l}. Now to customize this gate to majority gate, which is a special case of (LTG), we need to make all the weights equal to ‘1’ Eq. (1) will be

the majority function is a special case of the linear threshold function. Table 1 shows theoretically the required number of gates (excluding the inverter) for each implementation of multi-input XOR function [concluded from 8]. Where layered LTG refers to a network that receives its input only through the first layer, while in the non-layered LTG network, the input could be fed to any layer. The rest of this paper is organized as follows: The next section explains the proposed design methodology. The third section explains the implementation of the multi-input XOR with CNFET, and the last section includes the simulation results and conclusions.

2 XOR Function with Multi-input Majority The general form for the linear threshold logic gate (LTG) is described in Eq. (1) f (x1, x2, x3, . . . . . . . . . .xl, ) =

1 if li=1 wi xi ≥ T 0 if li=1 wi xi < T

(1)

MAJ(x1, x2, x3, . . . . . . . . . .xl, ) =

where the value of the threshold (T ) for the majority gate is (l/2 + 0.5). Using the majority function described with Eq. (2), let us construct the design table as shown in Table 2 for the 2-inputs XOR function in which we demonstrate the design procedures. In this table, we have four probable states for the two inputs shown in the first two columns. In the third column, the summation ( X i ) of the inputs for each state is calculated. The fourth column is the output of threshold gate with a threshold value of 1.5 inverted (TD1.5 ), x1 , and x2 are its inputs. The fifth column of the table represents the sum (SUM) of column four multiplied by two and column three. In the last column, the fifth column is used as an input to threshold gate with threshold of 2.5, and this column is the output (TDSUM2.5). It can be seen that two majority gates are needed. The circuit shown in Fig. 1 is the resulting 2-inputs XOR. The power of the proposed procedure is clear for the 3input XOR circuit and higher. Table 3 presents the design procedure for the 3-inputs XOR, and Fig. 2 is the schematic X1

Fig. 1 Schematic diagram for the proposed 2-inputs XOR

X2 0

X1 X2 0

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1 if li=1 xi ≥ T (2) 0 if li=1 xi < T

MAJ 3

MAJ 5

OUT

Author's personal copy Arab J Sci Eng X1

Fig. 2 Schematic diagram for the proposed 3-inputs XOR

X2

MAJ 5

X3

OUT

X1

MAJ 3

X2 X3

Table 4 5-Input XOR gate design table xi TD1.5 TD3.5 SUM = 2TD1.5 + 2TD3.5 + xi SUMTD4.5 0

1

1

4

0

1

1

1

5

1

2

0

1

4

0

3

0

1

5

1

4

0

0

4

0

5

0

0

5

1

diagram of it. This table has the same columns of Table 2 but with 8 rows. We can see from Table 3 that the last column is the XOR of the three inputs. Now to construct this XOR, we only need circuits to perform two different thresholds 1.5 and 2.5, and these circuits are easily the 3-input majority and the 5-input majority. For the 5-input XOR gate, we will start by constructing the design table, and this time to reduce the table size, it will contain only the summation of the inputs since the individual value of each input is not important, and the input order does not matter. The details are given in Table 4. In this table, the first column has the sum of the inputs ( xi ), the second is the output of threshold gate with a threshold of 1.5 inverted (TD1.5 ), the third is the output of LTG with threshold of 3.5 also inverted (TD3.5 ), the fourth column calculates the sum Fig. 3 Schematic diagram for the proposed 5-inputs XOR

X1 X2 X3 X4 X5 0 0

X1 X2 X3 X4 X5 1 1

of the first column with each output of threshold gate (in column two and three) multiplied by two. This sum is used as an input to LTG with threshold of 4.5. The last column is the XOR function for the five inputs whose summation is given in the first columns. To construct this circuit, we will need a five input circuits with a threshold of 1.5 and another five input circuits but with a threshold of 3.5. Both of these can be produced using a modified form of the 7-input majority gate. Also, a LTG with 9 inputs and a threshold of 4.5 is needed, which is simply the 9-input majority gate. The complete circuit block diagram for the 5-input XOR is shown in Fig. 3. In general, to generate an n-input XOR from multi-input majority gate, a two gate-level circuit is needed with 1. n2 Majority function with (2n − 3) inputs in the first level. 2. n2 Inverters connect the output of the majorities in the first level to the input of the second-level majority. 3. One majority with (2n − 1) inputs in the second level. 4. Each output of the first-level majorities should be inverted and inputted twice to the second-level majority. 5. The threshold of the first-level majorities is controlled by setting the rest of the inputs (n − 3 inputs) to 0s or 1s. The number of majority inputs of each level is clear in the proposed 7-inputs XOR shown in Fig. 4.

MAJ 7

X1 X2 X3 X4 X5

MAJ 9

Y

MAJ 7

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Author's personal copy Arab J Sci Eng Fig. 4 Schematic diagram for the proposed 7-inputs XOR

X1 X2 X3 X4 X5 X6 X7 1 1 1 1

MAJ 11

X1 X2 X3 X4 X5 X6 X7 1 1 0 0

MAJ 11

X1 X2 X3 X4 X5 X6 X7 0 0 0 0

X1 X2 X3 X4 X5 X6 X7

MAJ 13

Y

MAJ 11

Table 5 The number of components and the number of levels of multi-input XOR design XOR no. of inputs

2-Inputs

3-Inputs

5-Inputs

7-Inputs

n-Inputs

No. of 3-input majority gate [9]

3

3

6

9

3 n2

No. of inverters [9]

2

3

6

9

3 n2

No. of levels [9]

2

2

4

4

2log3 n

No. of 3-input majority gate in the proposed design

1

1

0

0

0


1

1

0

0

0


0

0

2

0

0


0

0

1

0

0


0

0

0

3

0


0

0

0

1

0

::::::::::::

0

0

0

0

0

No. of (2n − 3)-input majority gate in the proposed design

0

0

0

0

n2

No. of (2n − 1)-input majority gate in the proposed design

0

0

0

0

1

No. of inverters in the proposed design

1

1

2

3

n2

No. of levels in the proposed design

2

2

2

2

2

During the survey for multi-input XOR gate design approaches with majority function, one attempt was found in [9]. In this attempt, the 3-input majority gate was used to construct the logic combination of XOR gate with one simple modification to construct the 3-input XOR, and then a tree structure that depend on the 2 and 3 inputs XOR gates is presented and used for higher inputs. The number of components and the number of levels (i.e., the gate delay) of each design are presented in Table 5. It is clear from Table 5 that there is a significant improvement in the gate levels where in the proposed design a con-

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stant gate level of two is expected, while in the conventional designs and the one reported in [9], there are huge expansion in the gate levels when the number of inputs of XOR increased.

3 Multi-input Majority with CNFET The Carbon Nano Tube (CNT) is a cylindrical tube with graphite wall, which were first synthesized in microscopic scale in [10]. This graphite wall could be made of single

Author's personal copy Arab J Sci Eng Fig. 5 Multi-input majority not function with CNFET. a Voltage mode. b Current mode

Fig. 6 Circuit diagram for the proposed voltage mode 5-inputs XOR

or multiple sheets. One or more semiconducting SWCNT (Single-Wall Carbon Nano Tube) is used as a channel for the transistor [11,12]. Then the first transistor on a flexible and transparent substrate was made in 2003[13]. CNFET has higher performance with faster response than CMOS and lower power consumption. Another superiority of CNFET is unique one-dimensional band structure, which suppresses backscattering and causes near-ballistic operation. Moreover, another significant attribute of CNFET is that P-CNFET and N-CNFET with the same device geometries and have the same mobility, and consequently the same current drive capabilities, which are very important for transistor sizing in the complex circuits. Good reviews on the types of CNT-based transistors, the relations that compute the threshold voltage from the tube

diameter, the advances in their fabrication process can be found in [14,15]. In this paper, the design of multi-input majority function with CNFET is presented to be used in the proposed multi-input XOR design as an example of Nanotechnology implementation of the proposed approach. This technology is selected because of its super conductivity and large fanin and fan-out capability; so many inputs can be supplied to the majority gate (up to 13 in this paper) unlike conventional CMOS. The compact SPICE CNFET model presented in [16,17] was used for the simulation of the CNFET. This model had been used in many research articles [18–20] because of its superiority in describing the CNFET with all the non-idealities. The following simulation parameters are used in this work:

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Author's personal copy Arab J Sci Eng X1 X2 X3 X4 X5 0

0

X1 X2 X3 X4 X5

i

i

i

i

i

2i X1 X2 X3 X4 X5 1

1

2i

Y

Fig. 7 Circuit diagram for the proposed current mode 5-inputs XOR Table 6 Simulation results

1. Physical channel length 32 nm 2. The mean free path in the intrinsic CNT channel is 100 nm 3. The length of doped CNT source-side extension region is 32 nm 4. The length of doped CNT drain-side extension region is 32 nm 5. The dielectric constant of high-k top gate dielectric material (HfO2) is 16 6. The thickness of high-k top gate dielectric material is 4 nm 7. The coupling capacitance between the channel region and the substrate is 40 pF/m 8. The Fermi level of the doped S/D tube is 6 eV Two types of circuits were presented in [21] to achieve the multi-input majority gate with CNFET. The voltage mode circuits, where the use of n equal values capacitors to connect ninputs to an inverter with a threshold voltage of (1/2)×VDD, demonstrate the n-inputs majority NOT function shown in Fig. 5a. Here it depends on the fan-in capabilities of the CNFET. Another form for the current mode circuits is presented [21] in Fig. 5b. It can be seen that this form has fewer components and faster response, and it could be used when the speed is the most important factor in the circuits. In both designs, the method described in [22] was used to tune the CNFET structure to obtain optimum design. These two types are used to construct the 5-inputs XOR circuit in voltage and current modes. The 5-inputs XOR is selected as an example to compare it with the one constructed in [23] using CNFET. In [23], they used non-uniform design for the CNFETs used with multiple threshold voltages and with different number of tubes for each CNFET, which is not a practical approach on the nanoscale, and also, the design

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No.

Model

No. of devices

Delay × 10−12 s

1

Proposed voltage mode 5-inputs XOR with CNFET 32 nm

27

56.406

2

Proposed voltage mode 7-inputs XOR with CNFET 32 nm

45

59.196

3

Proposed current mode 5-inputs XOR with CNFET 32 nm

16

4

Conventional serial 5-inputs XOR with MOSFET 32 nm

50

174.21

5

Conventional tree 5-inputs XOR with MOSFET 32 nm

50

106.67

6

5-inputs XOR with CNFET I [23]

20

107.1

7

5-inputs XOR with CNFET II [23]

16

93.66

8

Conventional serial 7-inputs XOR with MOSFET 32 nm

70

255.06

9

Conventional tree 7-inputs XOR with MOSFET 32 nm

70

143.1

2.5019

presented in [23] cannot be extended to n-inputs XOR. In this work, a uniform structure for the CNFET with the same threshold voltage and number of tubes is used. The proposed circuit diagrams are shown in Figs. 6 and 7. The same approach with its voltage mode is used to implement 7-inputs XOR shown in Fig. 4. This approach could be extended to n-inputs XOR where n depends on the driving capabilities of the inverter of the majority gate.

4 Simulation Results The 5-inputs XOR in current and voltage mode and the 7-inputs with voltage mode were simulated with HSPICE

Author's personal copy Arab J Sci Eng Fig. 8 Proposed voltage mode output waveform

at room temperature with VDD=0.9 V and a frequency of 100 MHz. The results were compared with the conventional designs and the design proposed in [23] from the speed and the number of devices point of views. The results are shown in Table 6, and the output waveform of the proposed 7-inputs voltage mode is shown in Fig. 8. It is clear from the table that there is a significant improvement in the speed for the proposed design method. For a realistic design with fixed threshold voltage for the CNFET, a significant improvement in the number of devices (transistors and capacitors) is achieved. The important aspect in the proposed design is the ability to be extended to n-inputs XOR with fixed gate levels of 2. To show the superiority of the proposed circuits, a 16bit parity generator is designed based on the proposed approach which includes (2 × 7-input XOR gates) and (1 × 5input XOR gate) and compared with 16-bit parity generator designed with conventional 2-input XOR with CNFET to exclude the technology change effect. The output waveforms

are shown in Fig. 9. Besides the clean output compared with the conventional XOR gate design which has a lot of clichés, a noticeable reduction in the number of components of the circuit is achieved, where 180 transistors are used for the conventional design, while 28 transistors + 92 capacitors are used in the design based on the proposed XORs. The circuit time delay is 3.0202E-10 sec for the design with multi-input XOR and more than twice this value (6.3592E−10 s) for the design with conventional 2-input XOR. The process variation had become an important aspect that limits the scaling on CMOS technology; therefore, in this work, its effect is studied for the proposed 7-input XOR gate. The previous studies [24] of the process variation effect on CNFET circuits showed that the most effecting factors are tube diameter and density. The density variation can be defined as (Density variation = tubes + pitch variation), and the pitch is the distance between the centers of two adjoining SWCNTs under the same gate of a CNFET.

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Author's personal copy Arab J Sci Eng

Fig. 9 16-Bit parity generator output waveforms. a With the proposed multi-input XOR. b With conventional 2-input XOR

We applied the variation analysis using SPICE Monte Carlo simulation with 6σ and with percentage variation of 5, 10 and 15 % in the density and CNT diameter. Figure 10 shows the effect on circuit-consumed power and circuit delay. Changing the supply voltage shows noticeable effect on the circuit time delay as shown in Fig. 11, where 3 supply voltages are tested 0.8, 0.9 and 1 V and the time delay decreases with increasing the supply voltage. The thermal effect is also tested by varying the operation temperature of

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the 7-input XOR between 0 and 80 ◦ C, and there are no effect on the circuit as shown in Fig. 11 because of the ability of CNFET to tolerate the temperature variation.

5 Conclusions In this paper, a multiple input majority design-based method for the n-inputs XOR is presented. This method is very effi-


Fig. 10 Process variation of density and diameter of CNFETs for the proposed 7-input XOR gate and the effect on circuit-consumed power and circuit delay

Fig. 11 Temperature and supply voltage variation effect on the proposed 7-input XOR gate

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cient for nanotechnologies since most of them implement the majority function more efficiently than other logic functions. The presented method showed about 67 % improvement in the delay for the 5-inputs compared with conventional serial design and 47 % compared with conventional tree design for 5-inputs XOR. Good improvement in the number of circuit’s components (i.e., circuit area) of about 46 % was achieved for 5-inputs in the worst case. The process variation study shows that the density variation has more effect than the tube diameter. The results of this paper are encouraging to extend this approach to general logic design method for the new technologies.

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