A novel Design Methodology for Current Reference Circuits H.Aziza
E.Bergeret
A. Perez
Aix-Marseille Université, IM2NP CNRS, IM2NP (UMR 6242) IMT - Technopôle de Château Gombert, 13451 Marseille Cedex 20, France
[email protected]; Tel: (33)-491-054-784 Abstract— In this paper, design parameters of a current reference circuit are automatically generated according to specific design constraints. These constraints can be minimal consumption current or minimal temperature coefficients. This methodology is based on a current reference mathematical model. This model is generated thanks to a “Design Of Experiment” (DOE) technique. The DOE technique takes as input electrical simulation results of a current reference circuit for different component geometries. DOE generates polynomial equations of the current reference output IREF, the consumption current ISUNK, the temperature dependency factor βT and the supply voltage dependency factor βV. Using these equations and according to a given design specification (IREF, ISUNK, βT or βV), the most suitable design parameter values are generated.
I.
components (including passive and active elements) as well as extrinsic parameters (like the supply voltage) can be considered by the methodology. In addition, only few simulations are needed to optimize the circuit. This methodology is based on a DOE technique to build CR models. These models link CR parameters (transistor widths) to specific CR outputs like the consumption current ISUNK. This paper is organized as follow. Section 2 gives an overview of the automated design methodology. In section 3, the DOE technique is detailed in order to explain the CR polynomial model generation. Section 4 is dedicated to results and discussions. Finally, section 5 gives some concluding remarks.
INTRODUCTION
Current references (CR) are used in almost all analog and digital systems to provide stable and temperature-independent current [1] [2]. The optimization of CR in terms of power consumption is a key design target to extend battery and embedded systems lifetime. Besides, the CR output current IREF has to be accurately monitored regarding temperature and supply voltage variations. Knowing that, an effective method to quickly determine the most suitable design parameters for a given CR structure is highly desirable. Many analytical models have been developed for analog circuits’ optimization. These models allow a good understanding of circuits and can be used to determine the optimal parameter values [3]. However, the use of analytical models to optimize a circuit is not a generic method and the model building consumes huge time. Previous studies propose generic methods for analog circuits’ design and optimization. In [4], a method based on transistors’ size optimization for low-power applications is presented. But, circuit parameters others than transistors’ size can not be considered by the method. In [5], the author presents a generic method for analog design optimization using the Tabu Search heuristic. The goal is to minimize a given cost function which depends on a set of designer specifications. The main limitation of this method is the large number of simulations or measurements to perform in order to minimize the cost function. This paper proposes an automatic generation of CR design parameter values under specific design constraints. Circuits’
978-1-4244-2182-4/08/$25.00 ©2008 IEEE.
II.
CURRENT REFERENCE DESIGN METHODOLOGY
When dealing with CR circuits, constraints like design robustness, minimal consumption and small temperature and supply voltage dependency factors have to be considered during the design process. VDD P3
P1
P2
Ws
Wp
Wp IREF
N3 Wnb
Figure 1.
N1
N2
Wn
Wn2 current mirror
N4 Wnb
Current reference circuit
The complete design scheme of a CR circuit needs an optimization step, with global simulations which take into account all effects. The optimization of CR designs with several parameters to determine could take a long time, even if approximated values are defined for the main parameters. In this work, a CR design methodology is presented for the structure presented Figure 1, which currently presents the best choice for low voltage circuits. In the proposed CR circuit a current mirror imposes equal
238
currents in the two branches of the circuit. Transistor N4 works as an active resistance (below saturation) and is biased by 2 additional MOS N3 and P3 in order to provide a suitable gate voltage for N4 [2]. In this kind of structure, the W/L ratio of each transistor has to be monitored as well as possible because it impacts directly the CR outputs. In a first approximation, one can be assume that the CR output IREF depends mainly on the transistors widths Ws, Wp, Wn, Wn2 and Wnb. These five parameters, presented Figure 1 are chosen as the CR input parameters. 74
IREF (nA) βT = dI/dT
72 70 68
Temperature (°C)
66 -20
10
40
70
100
IREF (nA) 72
βV = dI/dV
70
VDD (V)
68 0.8
1.0
Figure 2.
1.2
1.4
1.6
1.8
Current reference simulation results
CR reference output curves obtained for the nominal circuit input parameters values are shown Figure 2, after DC simulations. By considering that the current IREF increases linearly with the temperature and the supply voltage VDD, two factors can be extracted from the simulation results: the temperature dependency factor βT and the supply voltage dependency factor βV. Another important parameter is the total consumption current called ISUNK, obtained for a given load and a given supply voltage VDD. IREF, βT, βV and ISUNK are considered as the CR outputs. Design Target Definition
DOE
configurations to simulate simulation results
Map of Simulations
Circuit polynomial models List of circuit design parameters Figure 3. Current reference design methodology
The design methodology, presented Figure 3 starts with the definition by the designer of a specific target: a CR current (IREF), an acceptable consumption current (ISUNK) or a given CR factor (βT or βV). Then, for this target value, a CR polynomial model generates a list of all the possible sets of design parameters values that meet the specification. CR polynomial models are obtained by using a DOE technique. The DOE technique takes as input electrical simulation results of a CR circuit for different component geometries. Section 3 presents in details the CR model generation.
III.
CURRENT REFERENCE POLYNOMIAL MODELS
A. Design Of Experiment Methodology To link circuit parameters Pi to a specific output Oi, any possible variations of all Pi has to be considered. It clearly appears that a classical approach based on changing one parameter at a time for all other possible parameter values is intractable because of number of experiments to perform. For example, considering 100 possible values for “m” parameters leads to perform 100m simulations to build a database. Although this approach is very accurate, it requires several thousands of simulations. To pass over this limitation, a technique based on “Design Of Experiment” (DOE) is used. DOE methods use probabilities and statistics to define the minimum number of experiments needed to identify significant cause-and-effect relationships between a given number of factors and one or more responses. Mathematically, DOE methods are developed to identify efficient experimental designs. In Doehlert designs, experimental points are uniformly placed in the experimental domain. Doehlert [6] suggests using a polynomial model to approximate the response. This polynomial model is computed using a Response Surface Methodology (RSM). The broad aims of RSM are to investigate the nature of the response surface over a region of interest and to identify input factors combinations associated with maximum or minimum responses. The nature of the function relating the responses to the variables is modeled empirically using a first or a second-order polynomial model. The fundamentals of RSM are set out in the seminal paper of Box and Wilson [7]. RSM is a combination of experimental and regression analysis and statistical inferences [8]. The broad aims of RSM are to investigate the nature of the response surface over a region of interest and to identify input factors combinations associated with maximum or minimum responses. B. Current Reference polynomial model In our case, experiments are in fact a set of simulations, thus this technique is here called “Design Of Simulation” (DOS). DOS allows having a complete knowledge of the selected outputs (IREF, CR factors and ISUNK) in the domain of variation of the 5 CR input parameters, from a limited number of simulations (the minimal number of simulations to perform is given by the Doehlert design according to the number of input parameters). In practical terms, a Doehlert matrix is selected to define all the configurations to simulate. With this information, a map of simulations is build around 31 different configurations of input parameters values (see Table I). TABLE I. n° 1 2 : : 31
239
Ws 18 12
15
CR Input parameters (Pi) Wp Wn Wnb 7.5 37 167.0 7.5 37 167.0 : : 7.5
35
169.0
SIMULATION MAP Wn2 0.55 0.55
IREF 95.8 46.62
0.52
71.60
CR outputs (Oi) βT βV 10.44 5.25 5.28 3.00 : : 7.98
4.04
ISUNK 419.5 167.3
285.0
IREF = IREF_TARGET ± ∆IREF
From the simulations results (i.e. CR outputs extraction), a multi-regression algorithm extracts the polynomial model of the outputs. The general form of the polynomial model is given by the following equation: O i = b0 + ∑ bi . Pi + ∑ bii .( Pi . Pi ) + ∑ bij .( Pi . Pj ) i
i
DATABASE PROCESSING
IREF Model
(1)
Candidate1 : Ws1, Wp1, Wn1, Wn21, Wnb1
ij
The confidence on the 4 output equations is given by the study of residuals, i.e. the difference between values obtained from the equations and ones obtained from simulations. The CR outputs residual study gives excellent results: the maximal difference is 1.5nA for IREF, 5.4nA for ISUNK, 0.09nA/V for βV and 0.10pA/C for βT. These values represent respectively less than 2.10%, 1.90%, 2.10% and 1.38% of error compared to the simulated values. Figure 4 summarizes the different steps of the polynomial model generation. Advantages offered by this model are listed below: - A simple polynomial expression which allows fast computing time, - Only 31 simulations are necessary, allowing a short generation time. - The validation of the model is achieved by monitoring the output accuracy (residuals).
Candidate 2 : Ws2, Wp2, Wn2, Wn22, Wnb2 ….. Candidate N : WsN, WpN, WnN, Wn2N, WnbN
Figure 5. IREF Candidate generation
IV.
A. Current Reference design methodology The domain of variation of each CR input parameters related to its nominal value has been selected constant to 20% (Table II). Nominal CR simulated outputs are 285nA for ISUNK, 70nA for IREF, 8pA/°C for βT and 4.1nA/V for βV. This domain of variation is called the sphere of knowledge. TABLE II.
CR Input parameters Wp Wn Wn2 7.5µm 37.5µm 167µm ± 20% ± 20% ± 20%
TABLE III.
Outputs (Oi) extraction Max Min
Dœhlert Matrix
output models Figure 4.
CR INPUT PARAMETERS DOMAIN VARIATION
Ws 15µm ± 20%
Nom.Val. ∆
Input parameters (Pi) domain variation Generation of the simulation map
RESULTS & DISCUSSION
Model generation bloc diagram
C. Design methodology: CR polynomial model processing Assuming the model fit to the simulation results is correct, the polynomial equation serves as model to predict what happens for any given combination of input parameters. The design methodology starts by building a global database made from combination of the circuit input parameters. This is done by varying each parameter of the polynomial model step by step for all other possible parameter values, in the domain of validity of the output polynomial model (the step of variation is given by the process capability). Thus, a global database of all possible configurations with their corresponding output values is generated. In this study 652 960 CR design parameters configurations are generated. Then, from this initial database, the configurations that meet a targeted output value plus or minus a given filter (i.e.variation around the target value) are extracted. These configurations are called candidates. Figure 5 gives an illustration of the IREF polynomial model processing. To limit the number of candidates, the filter value ∆IREF has to be small.
IREF (nA) 210,44 18,74
Wnb 550nm ± 20%
CR OUTPUT LIMITS
ISUNK (nA) 985,10 78,44
βV (pA/V) 2,54 10,43
βT (nA/°C) 21,45 1,18
The first step of the design methodology is to identify the maximum and minimum values of the CR outputs, within the sphere of knowledge. With this information, the designer will be able to set a realistic ouput target value in order to generate the corresponding design parameters. To do that, for each database configuration, the four outputs are computed using the polynomial models. Once, the maximal and minimal values of each output are extracted. The output limits are given Table III. One design parameter configuration corresponds at least to these limit values.
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Candidates
∆IREF
ISUNK ± ∆ISUNK
IREF ± ∆IREF
βV ± ∆βV
IREF ± ∆IREF
ISUNK ± ∆ISUNK
βT ± ∆βT (a)
(b)
Candidates Candidates
IREF ± ∆IREF
IREF ± ∆IREF βT ± ∆βT
βT ± ∆βT
ISUNK ± ∆ISUNK (c)
βV ± ∆βV
ISUNK ± ∆ISUNK (d)
Figure 6. CR outputs consideration
The second step of the design methodology consists in choosing one or more output value as a design target. However, by considering more than one output, the designer takes the risk to not generate any candidate (Figure 6.a). Indeed, the CR outputs are correlated. For instance, when dealing with CR circuits, a small IREF is correlated with low consumption current ISUNK. Therefore, the design methodology approach based on considering several outputs values needs a good knowledge of the circuit responses to be sure to generate at least one candidate (Figure 6.b.c.d) B. Application examples 1) CR design methodology considering one ouput To validate the CR design methodology approach, a numerical application based on the CR circuit presented Figure 1 is proposed. In this study, a CR IREF equal to 50nA±0.1nA is targeted. For this value, 12 candidates, presented Table IV, are generated (after the CR database processing, see Figure 5). For instance, candidate 5 is associated with a value of 12.9µm for Ws, 7.4µm for Wn, 34.4µm for Wp, 145.6µm for Wn2 and 0,58µm for Wnb. With this information, the designer is able to choose the most suitable set of design parameters (among the 12 proposed). TABLE IV. n° 1 2 3 4 5 6 7 8 9 10 11 12
Ws 12,30 12,30 12,60 12,60 12,90 12,90 13,80 13,80 14,40 15,00 15,90 15,90
CR CANDIDATES FOR IREF= 50NA±0.2NA CR Input parameters Wp Wn Wn2 6,40 44,00 169,6 8,00 37,40 187,6 6,80 41,00 163,6 8,20 30,80 151,6 7,40 34,40 145,6 9,00 31,40 169,6 8,00 42,20 181,6 8,40 37,40 169,6 8,80 30,80 139,6 7,00 44,00 151,6 8,40 34,40 133,6 8,40 44,00 169,6
Wnb 0,55 0,55 0,58 0,55 0,58 0,49 0,56 0,49 0,45 0,44 0,64 0,66
IREF 50,03 50,04 49,98 49,96 49,98 50,03 49,97 49,99 50,00 50,01 49,99 50,03
less important output specification), until at least one candidate is generated. The following output values are targeted: IREF=50nA±0.2, ISUNK=180nA±0.6, βT=5.5nA/V±0.2 and βV=3.0nA/V±0.2. In this example, target values are voluntarily chosen to generate candidates (Table VI). TABLE VI. n° 1 2 : 5
1 2 : 9
Ws 12,00 12,60 : 15,30
Wnb 0,55 0,58 : 0,64
IREF 50,03 50,04 : 50,00
IREF
ISUNK
βT
βV
49,9
179,5
5,68
3,13
50,1
180,2
5,66
3,11
: 49,9
: 179,8
: 5,62
: 3,18
CONCLUSION
In this paper, an efficient design methodology for CR circuits is presented. Knowing that CR circuit performances are strongly dependant on the CR design parameters, the proposed design strategy is very useful to speed up CR design. Indeed, according to a given design criteria, the most suitable design parameters are generated thanks to CR polynomial models. Simulations are performed to check the model prediction results for all generated candidates. REFERENCES [1]
[2]
[3]
CR CANDIDATES FOR IREF= 50NA±0.2 & ISUNK=180NA±0.5 CR Input parameters Wp Wn Wn2 7,20 31,40 139,60 7,60 35,00 157,60 : : : 9,00 30,80 133,60
Wnb
0,55 0,58 : 0,62
C. Model results validation To confirm the model results, electrical simulations are performed considering candidate 5 of Table IV (Ws=12.9µm, Wn=7.4µm, Wp=34.4µm, Wn2=145.6µm and Wnb=0,58µm). Candidate 5 simulations give 50.34nA for IREF (0.7% of error). Considering candidate 2 of Table VI for instance, simulations give 50.33nA for IREF, 182.1nA for ISUNK, 3.17nA/V for βV and 5.72nA/C for βT, which represents respectively 0.46%, 1.05%, 1.93%, and 1.06% of error compared to the model values. Simulations are also performed for all generated candidates to check the accuracy of the model. Simulation results are in good agreement with the polynomial model prediction.
[4]
n°
CR Input parameters Wp Wnb Wn2 7,40 32,60 145,60 7,60 35,00 157,60 : : : 8,00 33,20 145,60
V.
2) CR design methodology considering two ouputs In this second example, a CR output IREF equals to 50nA±0.2 and a consumption ISUNK equals to 180nA±0.5 are targeted. For this kind of circuit, it is accepted that the consumption current is fourth higher than the reference current, so this combination of output may lead to potential candidates. Otherwise, the corresponding filters have to be relaxed to obtain enough candidates (i.e. to offer multiple choices to the designer). Table V presents the 9 generated candidates. TABLE V.
Ws 12,30 12,60 : 13,50
CANDIDATES FOR 4 OUTPUT VALUES
[5]
ISUNK 180,09 180,29 : 180,16
[6]
3) CR design methodology considering four ouputs With this approach, a group of four pertinent outputs values have to be set. Then, for each run, if no candidate is generated, output filters have to be relaxed (beginning by the
[7]
[8]
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