A Novel Orthogonal Gate EDMOS Transistor With Improved dv/dt ...

IEEE ELECTRON DEVICE LETTERS

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A Novel Orthogonal Gate EDMOS Transistor With Improved dv/dt Capability and Figure of Merit (FOM) Hao Wang, H. P. Edward Xu, Wai Tung Ng, Senior Member, IEEE, Kenji Fukumoto, Ken Abe, Akira Ishikawa, Yuichi Furukawa, Hisaya Imai, Takashi Naito, Nobuyuki Sato, Kimio Sakai, Satoru Tamura, and Kaoru Takasuka

Abstract—A transistor with an orthogonal gate (OG) electrode is proposed to improve dv/dt capability, reduce the gate-to-drain overlap capacitance (Cgd ), and improve figure of merit (FOM). The OG has both a horizontal section and a vertical section for MOS gate control. This 30 V device is implemented in a 0.18 μm CMOS compatible process. Comparing to a conventional extended drain MOSFET transistor with the same voltage rating and device size, four times higher dv/dt capability and 53% improvement in FOM are observed. Index Terms—dv/dt capability, extended drain MOSFETs (EDMOS), figure of merit (FOM), gate-to-drain capacitance, orthogonal gate (OG).

I. I NTRODUCTION

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HE POWER semiconductor industry has achieved rapid progress in the reduction of specific on-resistance (Ron,sp ) and improvement of breakdown voltage in power MOSFETs, particularly in the low voltage range such as 30 V rating for display driver or DC–DC converter applications [1]. Extended drain MOSFET (EDMOS) is particularly attractive in these applications. However, only focusing on breakdown and specific on-resistance relationship is not enough for modern power devices; thus, dv/dt capability of power MOSFETs should also be considered. Since the power MOSFETs are widely used as on–off switches, the dv/dt capability of power MOSFETs determines the overall reliability. In this letter, we propose an EDMOS transistor with a novel orthogonal gate (OG) electrode designed to provide high dv/dt capability, fast switching speed, low gate charge, and reduced Ron,sp . The device structure and the fabrication processes are described, and the device characterization results are presented.

Manuscript received June 10, 2008; revised September 23, 2008. Current version published November 21, 2008. The review of this letter was arranged by Editor S.-H. Ryu. H. Wang is with the Department of Materials Science and Engineering, University of Toronto, Toronto, ON M5S 3E4, Canada (e-mail: eehao. [email protected]). H. P. E. Xu and W. T. Ng is with the Department of Electrical and Computer Engineering, University of Toronto, Toronto, ON M5S 3G4, Canada (e-mail: [email protected]). K. Fukumoto, K. Abe, A. Ishikawa, Y. Furukawa, H. Imai, T. Naito, N. Sato, K. Sakai, S. Tamura and K. Takasuka are with Asahi Kasei EMD, Tokyo 160-0023, Japan (e-mail: [email protected]). Color versions of one or more of the figures in this letter are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/LED.2008.2007225

Fig. 1. Cross-sectional view of the OG EDMOS and conventional gate EDMOS transistors.

II. D EVICE S TRUCTURE AND F ABRICATION The OG-EDMOS transistor fabrication process is based on a 0.18 μm high voltage (HV) CMOS technology developed by Asahi Kasei EMD. Both HV devices (30 V n- and p-type EDMOS transistors) and standard CMOS are available in this technology. A cross-sectional view of the OG-EDMOS transistor is shown in Fig. 1. The starting wafer is a (100) oriented p-type wafer with doping concentration of 1 × 1015 cm−3 . The fabrication process begins with field oxidation where a thick layer of oxide is formed. This is followed by lithography for the active device area and oxide etching. Prior to the formation of the STI, deep n-well and HV p-well ion implantations are performed. All the implanted impurities can be activated together during the STI annealing for the standard CMOS. The n-drift ion implantation is carried out after the STI annealing, because RESURF conditions [2], [3] require careful control of the n-drift dose and junction depth. The choice of this dose is based on diffusion trials and extensive process and device simulations. Gate

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Fig. 2. SEM cross-sectional view of the n-type OG-EDMOS. TABLE I COMPARISON OF ELECTRICAL CHARACTERISTICS BETWEEN OG AND C ONVENTIONAL G ATE EDMOS T RANSISTORS

Fig. 3. Cgd comparison between OG and conventional gate EDMOS transistors. (a) NMOS measurement data. (b) PMOS measurement data.

lithography and etch, gate oxidation, polysilicon deposition, polysilicon gate etch, and doping annealing are then carried out to form the gate electrode. The gate mask is then used to define the entire OG electrode. Thereafter, a thick interlevel oxide deposition of TEOS is followed by contact lithography and oxide etching to form the contact window. Finally, metallization and passivation are carried out to complete the EDMOS transistor fabrication sequence. The cross-sectional diagram of the device is illustrated in SEM micrograph shown in Fig. 2. Fig. 4.

Power MOSFET equivalent circuit.

III. C HARACTERIZATION AND D ISCUSSION The OG-EDMOS transistor achieved a breakdown voltage of 35.2 V and Ron,sp = 32.4 mΩ · mm2 at Vgs = 5 V and Vds = 1 V, respectively. The electrical characteristics of both the fabricated OG and conventional gate EDMOS transistors are compared in Table I. The specific on-resistance is reduced by 24% due to the reduction of lateral channel length A (see Fig. 1). The OG-EDMOS drift region is completely underneath the STI; this reduces the risk of punch through between the drift region and the source. The minimum lateral channel length A1 is 0.3 μm in OG-EDMOS before punch-through breakdown would occur. As a result, we can reduce channel length from

A2 = 1 μm to A1 = 0.3 μm. Since the STI depth is 0.35 μm, the total channel length is estimated to be 0.3 + 0.35 = 0.65 μm for the OG-EDMOS. As the effective channel length is reduced, the total on-resistance is also lowered for the OG-EDMOS. One of most prominent features of the OG-EDMOS transistor is a reduction in Cgd due to the minimization of the gateto-drain overlap capacitance [4]. The gate trench opening width is 0.2 μm, and there is no vertical sidewall overlap between gate and drain. Comparing to a conventional EDMOS transistor with the same voltage rating and device size, 75% and 88%


WANG et al.: NOVEL ORTHOGONAL GATE EDMOS TRANSISTOR WITH IMPROVED dv/dt CAPABILITY AND FOM

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Fig. 5. dv/dt capability comparison between OG and conventional gate EDMOS transistors.

reductions in Cgd are observed at Vds = 0 V for n-type and p-type OG-EDMOS, respectively (see Fig. 3). The transient dv/dt capability is defined as the maximum rate of rise in drain–source voltage without causing inadvertent turn-on of the transistor, dv/dt = vth /Rg Cgd . If this rate exceeds a certain value, the voltage across the gate–source terminals may become higher than the threshold voltage, turning on the device (see Fig. 4). Moreover, in extreme cases, catastrophic failure may occur. Therefore, dv/dt capability is an important reliability characteristic. For devices at a given voltage rating, higher dv/dt capability is more desirable. From the dv/dt simulation comparison as shown in Fig. 5, the OG-EDMOS transistor demonstrates four times higher dv/dt capability for transistors with threshold voltage = 1 V. The comparison of gate charge (Qg ) between the OG and conventional gate EDMOS transistors is presented in Fig. 6, where Qg specifies the amount of gate charge required to drive the MOSFET gate-to-source voltage (Vgs ) from 0 to 10 V. It is obtained by integrating the gate current as a function of time, Qg = Ig · dt. The OG-EDMOS transistor demonstrates a 37.5% reduction in total Qg at Vgs = 10 V. The figure of merit (FOM) (Ron × Qg ) is improved by 53%. IV. C ONCLUSION In summary, an orthogonal gate structure has been developed for EDMOS transistor. The fabrication process is based on

Fig. 6. Gate charge comparison between OG and conventional gate EDMOS transistors.

a 0.18 μm CMOS compatible technology. The breakdown voltage and on-resistance are comparable with conventional EDMOS transistors. The proposed OG-EDMOS transistor achieved four times higher dv/dt capability, 75% reduction in Cgd for n-type OG-EDMOS, 88% reduction in Cgd for p-type OG-EDMOS, 24% reduction in Ron,sp , and 53% improvement in FOM without degradation in breakdown voltage or onresistance. The enhanced performance of the OG-EDMOS will translate into better power conversion efficiency with higher reliability when employed in switched mode power supply applications. R EFERENCES [1] S. Ono, Y. Yamaguchi, Y. Kawaguchi, and A. Nakagawa, “30 V sub-micron shallow junction planar-MOSFET for DC-DC converters,” in Proc. ISPSD, 2004, pp. 401–404. [2] A. W. Ludikhuize, “A review of RESURF technology,” in Proc. ISPSD, 2000, pp. 11–18. [3] M. Imam, Z. Hossain, M. Quddus, J. Adams, C. Hoggatt, T. Ishiguro, and R. Nair, “Design and optimization of double-RESURF high-voltage lateral devices for a manufacturable process,” IEEE Trans. Electron Devices, vol. 50, no. 7, pp. 1697–1701, Jul. 2003. [4] Y. Zhu, Y. C. Liang, S. Xu, P.-D. Foo, and J. K. O. Sin, “Folded gate LDMOS transistor with low on-resistance and high transconductance,” IEEE Trans. Electron Devices, vol. 48, no. 12, pp. 2917–2928, Dec. 2001.
