A Novel Technique for Wideband Bipolar Amplifiers Mehdi Ghasemzadeh Microelectronic Research Laboratory Urmia University Urmia, Iran
[email protected]
Morteza Mousazadeh Microelectronic Research Laboratory Urmia University Urmia, Iran
[email protected]
Amin Akbari Microelectronic Research Laboratory Urmia University Urmia, Iran
[email protected]
Khayrollah Hadidi Microelectronic Research Laboratory Urmia University Urmia, Iran
[email protected]
Abdollah Khoei Microelectronic Research Laboratory Urmia University Urmia, Iran
[email protected] Abstract— In this paper a novel wideband amplifier based on a positive feedback is presented. The utilizing feedback network includes two capacitors and an emitter degeneration resistor which does not affect the low frequency behavior of the amplifier. Also a series- series mode is exploited to compensate the miller effect of Cμ and to decrease the input capacitance. The proposed method is obtained a 200% gain bandwidth enhancement with respect to a simple differential pair and a 21% improvement considering other topologies in the literature.
Keywords: Bandwidth enhancement, positive feedback, wideband amplifier. I.
INTRODUCTION
Nowadays, wideband gain stages are in extensive use in communication systems. It is necessary to achieve high bandwidth while no longer affecting the low frequency behavior. There are some bandwidth enhancement methods such as cascoding, Cc-cancelation, and “parasitic capacitance compensation” techniques. The first two techniques prevent bandwidth reduction by means of “Miller effect”. The third technique is based on omitting undesired capacitors of an amplifier. However, full capacitor cancelation does not achieved because of frequency limitation of active compensating networks. Speaking of low-power amplifiers which use high speed bipolar transistors, these techniques are not more effective.
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Wakimoto and Akazawa [5] suggested a parasitic neutralization technique which uses a compensation network that exploits high frequency positive feedback to neutralize the capacitance, to remove what effect it has on the frequency behavior of the amplifier. This compensation circuit basically uses an active feedback network, hence additional transistors are needed. However, this can impose constraints on the input common mode range. Furthermore, active compensation networks have frequency limitations that do not allow an exact cancelation of the pole. Even if the effect of the unfavorable capacitor is omitted, the poles and zeroes of the compensation circuit impact the frequency response of the amplifier, resulting in bandwidth limitation and yielding peaking. Vadipour [4] has been proposed a compensation technique for buffered differential amplifiers which uses positive capacitive feedback. That technique uses two capacitors between the buffer outputs and the differential pair inputs, to obtain compensation similar to the one proposed in [2]. Another compensation technique which has been proposed in [3] uses a series-shunt high-frequency positive feedback to achieve bandwidth enhancement, exploiting the same principle as in [4]. This technique provides a bootstrap action that introduces a large increase of the gain-bandwidth product considering the previous wide-banding methods. In this paper a new compensation technique has been proposed which exploits the same principle as in [3] but uses a series-series high frequency positive feedback. The compensation capacitors are placed between the base nodes of
the cascoded differential pair and the emitter nodes of a degenerated differential pair. The topology is described in section 2, and a linear analysis applying a feedback approach is shown in section 3. In order to compare these techniques, the small signal model is utilized. Section 4 compares new technique with the predescribed ones. Section 5 illustrates the simulation results using Maxim GST-2 Si BJT technology (fT≈27 GHz). Section 6 is attributed to conclusion. II.
Fig. 1 shows that the voltage gain of the amplifier ⁄ is almost constant and the bandwidth enhancement is achieved. Vcc RL Q3
VO+
RS
VO-
Q1
CF
RS
Q2
CF
IEE
VS+ IEE
Fig. 1: The proposed topology in [4]
According to the proposed topology in [3] which is shown in fig. 2, the degeneration resistor REE permits the enhancement of input impedance which results in an extra degree of freedom in the design of feedback network. The compensation capacitors CF close a loop between the output buffers and the emitter nodes of the differential pair. The more the frequency increases, the more the feedback voltage gain gets near unity and it results in a bootstrap action which cancels the effect of the output capacitance. Vcc
RL Q3
RL VO+
VSIEE
RS CF
RL
RL
Q1 IEE
Q4
VO-
REE
RS
Q2
VO+
RB
Q2
Bias
VO-
RB
Q4
Bias
CF
VS-
CF
RS
RS
Q1 R Q3 EE IEE
VS+
IEE
Fig. 3: Proposed topology
In [3], the output of differential pair is buffered and then the compensation capacitors are added between the buffer’s output and the emitter of input transistors. There is no need for output buffers in the proposed compensation method. III.
RL Q4
IEE
Vcc
TOPOLOGY DESCRIPTION
It is popular that in a common emitter gain stage the capacitance Cμ acts as a local miller compensation capacitor which produces a local negative feedback. This kind of feedback reduces the amplifier’s bandwidth by means of a pole splitting action [4]. The positive capacitive feedback is in contrast with the previous action and demonstrates an “antipole-splitting” effect which caused a bandwidth increase. If the positive feedback becomes stronger than the effect of Cμ, the poles of the amplifier move closer and bandwidth enhancement is obtained.
VS-
Our proposed topology of wideband amplifier is shown in fig. 3. The circuit is based on cascode amplifier. Two compensation capacitors (CF) are placed between the emitter of input transistors and the base of cascode transistors to provide the series-series positive feedback. The positive feedback enhances the gain-bandwidth product which will be clarified in the analysis section.
CIRCUIT ANALYSIS – AC MODEL
In order to figure out the features of the proposed topology and to compare it with various wide-banding techniques, a small signal model of the amplifier is developed based on the feedback approach. In this approach, the input impedance and the total voltage gain of the amplifier are obtained as a function of transistor parameters and of the loop gain. The loop gain itself is determined by the compensation capacitor CF. The half-circuit open-loop small signal mode for the proposed amplifier in fig. 3 is shown in fig. 4 where (1) 2 is the emitter degeneration. By applying miller theorem, the capacitors, Cµi and Cµo, could be used instead of the basecollector capacitance Cµ1. 1
(2)
1
(3)
Where K is the voltage gain between the base–emitter and the collector–emitter ports of a transistor in common emitter configuration with emitter degeneration and it can be shown by its approximate low frequency value:
VS+
(4) IEE
CF
Fig. 2: The proposed topology in [3]
IEE
It is worth noting that the value of k is close to zero, so the value of substitution capacitance can be approximated by Cμ and consequently the value of input capacitance is reduced.
Cμ2
CF
VO
+
RE
RB
vπ2 rπ2 Cπ2 _
rO2
gm2vπ2
RL
In order to simplify the calculations, the base resistance (rb) of the transistors are neglected. Considering preassumptions, the transconductance of the forward amplifier is (11)
VS
Rs
rb1 +
vπ1
Cμ1 rπ1 Cπ1
_
Where rO1
gm1vπ1
Ψ = ( rπ + RE + g m rπ RE ) ic1
RE
CF
+ s ( rπ RBCF + rπ RE CF + RE RBCF + g m rπ RE RBCF + RE rπ Cin )
β
+ s 2 RE RBCinCF
The equation (13) refers to the open transconductance from the source to the output.
Fig. 4: Half-circuit open-loop small signal mode
Gv ( s ) =
The circuit in Fig. 4 can be analyzed as a feedback voltage amplifier. Fig. 5 illustrates the RC high-pass feedback network. This network’s transfer function (Γ(s)) is (5)
=
ic
loop
Z in .G ( s ) Zin + Rs
−rπ . g m ( 1 + ( RB + RE ) CF S )
Ψ + Rs ((1 + Srπ Cin )(1 + RB + RE )CF S )
(13)
Where 1
CF
ic
(12)
RB
(14) β
RB
RE
is the open loop input impedance, and Fig. 5: Feedback network
Fig. 6 shows the forward amplifier with the load effect of the feedback network, where (6) (7)
(15) is its dc value. The closed loop voltage gain can be calculated considering the diagram in fig. 7 as
(8) (9) (10)
(16) With Ψ
1
1 1
ZinF
]
Zπ
Vs RS + ZinF
-gm
Zin
SRE RB CF SCF (RE + RB)+1
Fig. 6: Forward amplifier
(17)
ZL
1 β
Fig. 7: Block diagram of the proposed topology
Vo
IV.
ANALYSIS OF AC MODEL
The AC model described in previous section can be used to obtain precise behavior of the circuit. The poles with the most effect on the bandwidth is given by ||
(18)
(19) (20)
1
(25)
∆
Where
1
In [3] a series-shunt capacitive feedback is exploited and the closed-loop voltage gain of the amplifier topology in fig. 2 is
(21)
With Δ = ( RG + Rin ) + s ⎣⎡Cin rπ ( RG + RE ) + CB RL ( RG + Rin ) + CF RE ( RG + rπ − g m rπ RL ) ⎦⎤ + s 2 ⎡⎣CBCin rπ RL ( RG + RE ) + CinCF rπ RE RG + CBCF RE RL ( rπ + RG ) ⎤⎦
( 26 )
+ s 3CinCB CF rπ RE RL RG
Where
(22)
(27)
(23)
In order to have the same dc gain for each three topology, RC has to be selected as (28)
And
Where (24) Mostly P1 is the dominant pole. In fig. 8 the location of the presented topology’s poles as a function of the feedback capacitance CF, for a given value of RE is provided by spice simulations and is evaluated under the intrinsic parameter set of bipolar transistors in technology Maxim GST-2.
In [4] a shunt-shunt positive capacitive feedback is used and the closed-loop voltage gain of the amplifier topology in fig. 1 is ∆
(29)
With
ΔV = ( RG + rπ ) +s ⎡⎣Cin' rπ RG + CB RL ( RG + rπ ) + CF RS ( rπ + rb − gm rπ RL ) ⎤⎦ +s 2 ⎡⎣Cin' CB rπ RL RG + Cin' CF rπ rb Rs + CF CB RL Rs ( rb + rπ ) ⎤⎦ +s3Cin' CF CB rπ rb RL Rs
(30)
is the input capacitance and it is given by: 1
(31)
The comparison can be carried out by considering the position of the open loop poles. These poles are given by (32)
1 3
Fig. 8: The location of our topology’s poles
Increasing the value of CF causes the poles of (16) become complex conjugate and maximum bandwidth is achieved when the damping factor is 1/√2. It is better to compare this proposed topology with the topologies proposed in [4] and [3] shown in fig. 1 and fig. 2 which are based on a same principle. An AC model of each topology has been developed applying the same approximation used to get (16).
And 1
(33)
23
Also the dominant open loop poles of the topology proposed in [4] are ||
(34)
And (35)
In both cases, the first pole is dominnant. Considering equations (20), (27), and (31), the valuue of the input capacitance for the proposed topology is lower than other topology’s input capacitance. For typicaal values of the parameters of high frequency transistors, it reesults | | V.
&| |
.
TABLE Ⅱ. Bandwidth Comparison for a 16 dB Amplifier Topology
Max. Bandwidth
Relative Bandwidth
Differential pair
3.4 GHz
1
Cascode
5.55 GHz
1.61
[4]
7.27 GHz
2.13
[3]
8.48 GHz
2.49
[6]
8.5 GHz
2.5
This work
10.3 GHz
3.02
SIMULATION RESULTTS
To evaluate the concept of the propossed topology, the simple differential pair gain stage, the cascoode gain stage and the amplifiers depicted in fig. 1 and fig. 2 arre simulated using Maxim GST-2 Si Bipolar transistor modeels (fT≈27 GHz). Table.Ⅰshows the parameters of this model. T The gain stages are designed with the same bias current and low frequency gain of 16 dB, and also as high as possible bandwidthh. TABLEⅠ. The Parameters of GST-2 Siliconn Bipolar parameter
vallue
Cje
31.8 fF
Cjc
14.2 fF
Ccs
15.8 fF
Rb
164.4 Ω
Rc
56.7 Ω
Re
11.2 Ω
Is
8.331 aA
τf
4p ps
β
225
ft
27 GHz
v on the frequency Fig 10 shows the effect of CF variation response of the proposed wideband amplifier. CF varies in the range of 0 to 500fF. Fig. 11 shows the dependence of o bandwidth and peaking on the frequency response of the pro oposed wideband amplifier to different values of feedback capaacitors (CF). The optimum bandwidth of 10.8 GHz with less than 0.1 dB peaking is achieved with CF=310 fF. The abssolute value of CF could be varied and consequently affect the baandwidth of amplifier.
Fig. 9 shows the frequency responnse of different amplifiers. The bandwidth of each design is summarized in table Ⅱ. In addition, by assuming the ddifferential pair’s bandwidth as the basic bandwidth, the relatiive bandwidths of aforementioned methods are achieved. The bandwidth of the proposed wideband amplifier is higher than oother structures. Fig. 10: Overall voltage gain with different values of CF
Fig .11: Bandwidth and peaaking versus CF Fig. 9: Bandwidth comparison for a 16 dB amplifier
Considering 25% variation in the value of CF, the bandwidth sensitivity in different designs is shown in table Ⅲ. The proposed design is less sensitive to the CF variations in contrast with the amplifiers depicted in fig. 1 and fig. 2. TABLE Ⅲ. Sensitivity of Bandwidth to the Feedback Capacitor CF ΔBW% ΔCf % Cf
This work
Topology in [3]
Topology in [4]
190 fF
20 fF
50 fF
-25%
-4.7%
-11.01%
-12.11%
+25%
+1.9%
+10.87%
+15.71%
VI.
CONCLUSION
In this paper a novel approach which exploits a seriesseries capacitive positive feedback has been presented. The feedback network acts as a high-pass filter that does not affect the frequency response and gain product of the amplifier in the range of lower frequencies. Increasing frequency causes the main amplifier’s poles to be transferred to high frequencies, giving a large gain-bandwidth product enhancement. Moreover, in proposed technique, emitter degeneration resistors have been exploited that allow further degree of freedom in the design of the amplifier, so it can be applied to single-ended gain stages. The proposed structure allows a lower sensitivity to variations and lower power dissipation with respect to other topologies. A small signal model of the proposed topology has been developed to compare it with the topologies in [3] & [4]. Silicon bipolar technology with 27 GHz of fT has been carried out, showing that our topology is obtained a 200% gain bandwidth enhancement with respect to a simple differential pair and a 21% improvement considering the topology in [3]. REFERENCES [1] [2] [3] [4] [5] [6]
P. R. Gray and R. G. Meyer, Analysis and Design of Analog Integrated Circuits. New York: Wiley, 2009 J. A. Mataya, G. W. Haines, and S. B. Marshall, “IF amplifier using Cc compensated transistors”, IEEE J. Solid-State Circuits, vol. SC-3, pp.401–407, Dec. 1968. Centrulli, F.; Luzzi, R.; Olivieri, M.; Trifiletti, A. “A bootstrap technique for wideband amplifiers”, IEEE J. Transactions, vol. 49, pp. 1474 – 1480, Oct. 2002. M. Vadipour, “Capacitive feedback technique for wide-band amplifiers”, IEEE J. Solid-State Circuits, vol. 28, pp. 90–92, Jan. 1993. T. Wakimoto and Y. Akazawa, “A low-power wide-band amplifier using a new parasitic capacitance compensation technique ,”IEEE J. Solid-State Circuits, vol. 25, no. 1, pp. 200–206, Feb. 1990. Bharade, Ashish ; Ghyvat, Hemant ; Ajnar, D. S. ;Jain, Pramod, “Design of CMOS based ultra wideband low noiseamplifier using acti ve shunt feedback technique” , Multimedia, Signal Processing and Communication Technologies (IMPACT), 2011 International Conference (pp. 200-203). Aligarh. Dec. 2011
