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IEEE ELECTRON DEVICE LETTERS, VOL. 35, NO. 2, FEBRUARY 2014
A Proposal for a Novel Hybrid Interconnect Technology for the End of Roadmap Chenyun Pan, Student Member, IEEE, and Azad Naeemi, Senior Member, IEEE
Abstract— To suppress the impact of size effects on sub-20 nm wide wires, a novel aluminum-copper hybrid interconnect architecture is proposed and its potential performance has been quantified. Al wires offer lower resistivities at nanoscale dimensions because they do not need diffusion barriers, and size effects are less prominent in them due to their smaller bulk mean free path. However, their current conduction capacity is substantially lower than that of Cu wires. To get around this limitation, this letter proposes a hybrid interconnect technology to replace only short narrow local signal wires by Al wires. This scheme takes advantage of the fact that signal wires conduct bi-directional currents and are therefore virtually immune to electromigration. The improvement in chip clock frequency is predicted to be between 50% and 100% for the 7 nm technology node. Index Terms— Interconnect, Al-Cu hybrid interconnect, subtractive process, system-level design, performance analysis.
I. I NTRODUCTION S THE semiconductor industry approaches sub-20 nm technology nodes, it faces major challenges imposed by interconnects. Size effects, including the surface and grain boundary scatterings, are expected to dramatically increase the effective resistivity of copper (Cu) interconnects [1]. Moreover, diffusion barriers, which are very poor conductors, will take an ever-increasing fraction of the wire volume. The scaling of keff for interconnect dielectrics has greatly slowed down. While the search for novel interconnect materials such as carbon nanotubes and graphene is ongoing, there are no clear alternative materials at this point. Due to the long transition time from research to production, there is a great risk that no novel material will be ready to replace Cu/low k interconnects at 11nm or even smaller technology nodes. More than a decade ago, the semiconductor industry switched from aluminum (Al) to Cu for its superior conductivity and its significantly better resistance to electromigration. However, it has long been known that Cu loses its conductivity advantage at nanoscale dimensions because the bulk electron mean free path (MFP) in Cu (40 nm) is larger than that in Al (16nm), leading to more pronounced size effects in
A
Manuscript received October 16, 2013; revised November 13, 2013; accepted November 15, 2013. Date of publication December 6, 2013; date of current version January 23, 2014. This work was supported by the Semiconductor Research Corporation Global Research Collaboration. The review of this letter was arranged by Editor S. List. The authors are with the School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA 30332 USA (e-mail:
[email protected]). Color versions of one or more of the figures in this letter are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/LED.2013.2291783
Cu wires [2]. Furthermore, Al wires do not need diffusion barriers, which take a large fraction of the volume of a wire at nanoscale dimensions. Despite these facts, it is widely believed that it is improbable to switch back to Al because of the reliability problems caused by almost 5 times lower current conduction capacity of Al as compared to Cu [3]. However, electromigration is a major challenge mainly for power and ground wires where unidirectional currents exist, while signal wires that conduct bi-directional currents are immune from electromigration [4]. The mean-time-to-failure for Al wires conducting an AC current is more than 4 orders of magnitude higher compared to Al wires conducting a DC current equal to the root mean square value of the AC current [5]. This fact opens the possibility of a hybrid interconnect technology, where metals with high current conduction capacities (e.g. Cu or tungsten (W)) are used for local power distribution networks, and a low resistivity metal is used for signal wires. For short local signal wires that are minimum-sized, Al can be a promising candidate. For longer interconnect lengths when larger cross-sectional dimensions are used, again Cu can be used as it offers a better resistivity at larger dimensions. This letter quantifies the potential performance of this novel hybrid interconnect technology, in which the conductor and the thickness of signal and power wires routed in the local interconnects levels are selected independently to maximize chip performance and reliability and to minimize power dissipation, simultaneously. The proposed scheme can benefit from a subtractive patterning process for short signal wires to achieve large grain sizes. The potential improvements in chip performance offered by the proposed scheme have been quantified at various technology generations and have been compared with those of conventional interconnect technologies with incremental modifications such as Cu wires with selfforming barriers (SFB) and Cu wires formed by subtractive processes. It should be noted that there would be challenges in implementing the proposed interconnect technology. For instance, etching an Al film at such small dimensions will be a challenging task. However, the proposed scheme is based on widely used metals such as Cu, W, or Al, which will be less risky than using alternative technologies based on novel materials such as carbon nanotube and graphene. II. Al-Cu H YBRID I NTERCONNECT T ECHNOLOGY A simplified sequence of the fabrication steps for the proposed hybrid interconnect technology is shown in Fig. 1. A thick layer of Al is deposited and annealed so that the grain
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PAN AND NAEEMI: PROPOSAL FOR A NOVEL HYBRID INTERCONNECT TECHNOLOGY
Fig. 1.
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Flow chart of subtractive Al-Cu hybrid interconnect process. Fig. 3. Chip clock frequency versus aspect ratio for six interconnect configurations at the 16nm technology node. Here, R = p = 0.5.
suffer more from the size effects. Therefore, below 90nm wire widths, Al wires offer lower resistivities, where up to a 4× smaller value can be observed at 10nm width. For those wires that are dominated by the surface scattering, the critical width decreases to 40nm, indicating a more moderate but still significant advantage of using Al wires at sub-20nm widths. III. S YSTEM -L EVEL E VALUATION AND C OMPARISON A. Design Methodology
Fig. 2. Resistivity versus the width of Cu and Al wires with two grain boundary reflectivity co-efficient R and surface specularity parameter p. Here, the aspect ratio is 2.
size can be enlarged. This will result in an average grain size that is equal to the film thickness [6]. The Al film is then polished down to the desired thickness, which is followed by pattering minimum-sized Al wires with a subtractive process. Then, the dielectric material is deposited, and the trenches are made for the Cu power wires. Finally, liner/diffusion/seed layers are formed inside the trenches, and Cu is electroplated into trenches. Although this process requires two lithography/etch steps, the cost of the second step will be lower because of the relaxed pitch used for Cu wires. In principle, this process allows the signal and power wires to have different thicknesses. For power wires, important metrics are resistance and current density; thereby, larger thicknesses are desired. For signal wires, a larger thickness increases the interconnect capacitance, which adversely affects power dissipation and even signal delay for short wires because the resistance is dominated by driver resistance. Based on the wire resistivity model in [7], Fig. 2 shows the resistivity versus the width of the wires. For Al wires, no barriers are needed and the grain size is assumed to be twice the wire pitch, which corresponds to the initial Al film thickness selected in Step 1 in Fig. 1. The ITRS projections for diffusion barrier thickness [8] are known to be quite optimistic and challenging to achieve. Hence, for Cu wires, the ITRS projected barrier thicknesses and twice of those values are considered as references. Here, two sets of reflectivity coefficient R and specularity parameter p are used based on the experimental data [1], [9]. The upper figure in Fig. 2 shows that wires that are dominated by the grain boundary scattering
Following the previous work [10], the system-level design methodology provides the optimal clock frequency based on the multi-level interconnection network optimization, the number of logic gates, die size and power density budgets, and the device-level model. Later, this methodology has been applied to several commercially available Intel multi-core processors crossing three technology generations from 65nm to 32nm technology node from three architectures. The simulation data for the chip throughput and clock frequency match the published raw data, and the geometric mean errors for the logic core area and number of logic transistors compared with the raw data are less than 10%. In this letter, device models for bulk FinFET from 20 nm to 7 nm nodes are obtained from [11]. The design rules including fin pitches and M1 pitches for various technology nodes are obtained from [8], [12]. The maximum number of metal levels is set based on the ITRS projection [8]. B. Comparisons In this subsection, a single logic core with 20 million logic gates is analyzed under a 100 W/cm2 power density constraint. The core area at the 16 nm technology node is assumed to be 5 mm2 , and for other technology nodes, the core area is proportionally sized based on the feature size squared. Fig. 3 investigates and compares six different types of interconnect architectures. The first and second configurations are the conventional Cu wires with liner/barrier thicknesses of 5.2nm (2× ITRS projection) and 2.6nm (ITRS projection), respectively [8]; the third is Cu wires without a barrier, which is the idealized SFB technology; the fourth is the Cu interconnect technology patterned using a subtractive process to achieve grain sizes twice as wide as the wire pitch; the fifth is the Al-Cu hybrid interconnect technology, where all the Cu signal wires whose width is narrower than the critical width
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IEEE ELECTRON DEVICE LETTERS, VOL. 35, NO. 2, FEBRUARY 2014
interconnect architectures. The optimal clock frequency begins to decrease below the 14 nm technology node, particularly for the processors using Cu interconnects with thick diffusion barriers, in which the size effects are prominent. The proposed Al-Cu interconnect technology significantly suppresses the frequency drop. For the upper chart, in which grain boundary is dominant, up to 2× improvement in chip clock frequency is predicted by using the novel interconnect architecture at the end of the roadmap; for the lower chart, in which surface scattering is more dominant, there is a 50% improvement in clock frequency. Fig. 4(b) shows the optimal aspect ratio for local signal wires to reach the optimal clock frequency, corresponding to each bar in Fig. 4(a). The optimal aspect ratio in the proposed scheme is up to 70% smaller than that in a conventional Cu interconnect technology at the 7 nm technology node. IV. C ONCLUSION
Fig. 4. (a) Optimal clock frequency and (b) aspect ratio versus technology node for six different interconnect configurations that are defined in Fig. 3.
(shown in Fig. 2) are replaced by Al wires; the last one is based on the fifth option where the thickness of the power wires is twice the thickness of the local signal wires. From Fig. 3, optimal aspect ratios are observed to maximize the clock frequency. This is because if the aspect ratio is too low, the frequency suffers significantly from the large resistance of the wire, particularly for the conventional Cu wires with thick diffusion barriers; if the aspect ratio is too high, the delay is dominated by the large wire-to-wire parasitic capacitance, which also increases the dynamic power dissipation of the interconnect network. Another observation from Fig. 3 is that the optimal aspect ratio required to achieve the maximum chip frequency decreases when a better interconnect technology is used, which improves the manufacturability and the circuitlevel performance such as crosstalk noise and delay variation. By using the hybrid interconnect technology, a 25% improvement in chip clock frequency is observed at the optimal aspect ratio for the same power budget. One reason for the improvement is that the aspect ratio of the copper wires in the local power distribution network is enlarged, which helps to reduce the power via density, increasing the overall wiring efficiency. Another reason is that the power dissipation of wires is saved by reducing the aspect ratio of the wires thanks to the low resistivity of the Al wires. For a fixed power density budget, this contributes to the performance increase. The simulation results also confirm that the AC current density in local signal wires is in the order of 105 A/cm2 , which is 10 times smaller than the DC current density limit set by the ITRS [8]. Because of the 104 increase in time-to-failure due to the self-healing effect for bi-directional currents [5], there should not be electromigration issues for signal wires. For various technology nodes, Fig. 4(a) shows the optimal clock frequency at the optimal aspect ratio for six types of
A novel Al-Cu hybrid interconnect architecture is proposed to alleviate the ever-increasing size effects caused by the small grain size and thick barrier of the conventional Cu wires. Using Al for the short signal wire with a subtractive process can achieve a smaller resistance per unit length at a small dimension without suffering from the electromigration because of the self-healing effect for wires that conduct alternating currents. Compared with the conventional Cu interconnect technology, the proposed scheme is projected to offer between 50 to 100% improvement in the clock frequency of a logic core implemented at the 7 nm technology node. R EFERENCES [1] W. Steinhogl, G. Schindler, G. Steinlesberger, et al., “Comprehensive study of the resistivity of copper wires with lateral dimensions of 100 nm and smaller,” J. Appl. Phys., vol. 97, no. 2, pp. 023706-1–023706-7, 2005. [2] P. Kapur, J. P. McVittie, and K. C. Saraswat, “Technology and reliability constrained future copper interconnects. I. Resistance modeling,” IEEE Trans. Electron Devices, vol. 49, no. 4, pp. 590–597, Apr. 2002. [3] J. Lienig, “Interconnect and current density stress: An introduction to electromigration-aware design,” in Proc. Int. Workshop Syst. Level Interconnect Predict., 2005, pp. 81–88. [4] M. H. Lin and A. S. Oates, “AC and pulsed-DC stress electromigration failure mechanisms in Cu interconnects,” in Proc. IEEE IITC, Jun. 2013, pp. 1–3. [5] B. Liew, N. Cheung, and C. Hu, “Electromigration interconnect lifetime under AC and pulse DC stress,” in Proc. Int. 27th Annu. Rel. Phys. Symp., 1989, pp. 215–219. [6] K. Schuegraf, M. C. Abraham, A. Brand, et al., “Semiconductor logic technology innovation to achieve sub-10 nm manufacturing,” IEEE J. Electron Devices Soc., vol. 1, no. 3, pp. 66–75, Mar. 2013. [7] W. Steinhoegl, G. Schindler, G. Steinlesberger, et al., “Scaling laws for the resistivity increase of sub-100 nm interconnects,” in Proc. SISPAD, 2003, pp. 27–30. [8] (2012). International Technology Roadmap for Semiconductors [Online]. Available: http://www.itrs.net [9] S. Maîtrejean, R. Gers, T. Mourier, et al., “Experimental measurements of electron scattering parameters in Cu narrow lines,” Microelectron. Eng., vol. 83, no. 11, pp. 2396–2401, 2006. [10] C. Pan and A. Naeemi, “System-level performance optimization and benchmarking for on-chip graphene interconnects,” in Proc. IEEE 21st Conf. EPEPS, Oct. 2012, pp. 33–36. [11] (2012). Predictive Technology Model [Online]. Available: http://ptm.asu.edu [12] S. Sinha, G. Yeric, V. Chandra, et al., “Exploring sub-20 nm FinFET design with predictive technology models,” in Proc. 49th ACM/EDAC/IEEE DAC, Jun. 2012, pp. 283–288.
