A Proposed Low-offset Sense Amplifier for SRAM ... - IEEE Xplore

2015 2nd International Conference on Signal Processing and Integrated Networks (SPIN)

A Proposed Low-offset Sense Amplifier for SRAM Applications Anil Kumar Gundu Department of ECE IIIT-Delhi, India [email protected]

Wazir Singh Department of ECE IIIT-Delhi, India [email protected]

Sai Manoj Divi Department of ECE DCE-Delhi, India [email protected]

variation and mismatch between the paired transistors increases as technology increases which leads in the increment of offset voltage (VOS) of SA. With larger offset voltage, the SA requires higher differential voltage (¨VBL) for correct sensing. In SRAM design, the memory area is very constrained, and proximity effects can play a big role in determining SA offset.

Abstract– Random variations play a critical role in determining SRAM yield, by affecting both the bitcell and the read Sense Amplifiers (SA). A low-offset sense amplifier capable of static random access memory (SRAM) applications has been presented in this work. Simulated results show that the proposed sense amplifier has very low offset of 31.284 mV compared to the conventional sense amplifiers. Index Terms – Delay, Offset, Sense Amplifier (SA), SRAM (Static Random Access Memory)

I. INTRODUCTION Embedded memory forms an integral part of design of today’s processor and SoC. With the increase in random variation with scaling (due to RDF, LER and other sources), SRAMs become extremely sensitive to process variations especially as the supply voltage is reduced. Random variations causes yield loss due to several mechanisms such as read stability, writeability, retention and read sense margin (access yield), however read sense margin is the mechanism that typically limits SRAM speed [1], [2]. Sense amplifiers (SA) are used extensively in memories read operation to amplify the small signal bitline differential voltage to digital level. The main purpose of embedded memory is to particularly improve the instruction and data access time. The propagation delay of each cache data path element directly contributes to total access time. One of the elements in data path of cache memory (SRAM) is sense amplifier. Increasing demand of speed of SA in modern low power applications has set a trade-off between Speed and Power [3]-[7]. Sense amplifier is activated in the read operation and it will be deactivated in the other operations. The sense amplifier which is activated during the read operation is used to sense the difference of the bit line voltages and amplify the differential voltage which has set up in the nodes of the bit lines to full rail voltage swing. The basic voltage sense amplifiers and current sense amplifiers which will be discussed in further sections. A good sense amplifier is the one whose reaction time is very less and having minimum Offset Voltage. An ideal Sense-amplifier will have infinitely small offset (> 0 Volt) (Offset is the minimum voltage differential needed at input nodes to resolve the latch in correct state). But in reality, a Sense-amplifier will have finite offset. Parameter 978-1-4799-5991-4/15/$31.00 ©2015 IEEE

Fig. 1 Conventional Sense Amplifier-I

The main contribution of the paper is to design the Sense Amplifier with low offset. In this paper we propose a Sense Amplifier and the structure is designed and simulated using 28nm CMOS technology. The paper is further organized as follows. The Conventional Sense Amplifiers are briefly discussed in section II and proposed Sense Amplifier is discussed in section III. The performance summary and simulation results of the proposed Sense Amplifier are introduced in section IV. Finally, the paper is concluded in section V. 964


II. PREVIOUS WORK

The other kind of latch type sense amplifier topology is shown in the below Fig. 2 [11]. This is also sense the difference between the voltage levels of both the bit lines and amplifies to the full swing voltage.

VLSI sense amplifier topologies are shown in below figure. Both the sense amplifiers have their input from BL and BLB. The sense enable input is activated once there establishes a sensible amount of voltage difference between the two bit lines. Since it depends on the voltage difference between the two bit lines, the sensible voltage difference also qualifies the sensitivity of sense amplifier. In one of the conventional sense amplifier called voltage sense amplifier, two cross coupled inverters will be there which convert the voltage difference between the two bit lines to the full swing rail voltages.

But in this sense amplifier type, the sense amplifier will not get isolated with the bit cells, as the bit lines are connected to the gates of the transistors. The operation of the sense amplifier will be explained as follow. Initially sense enable (SEN) signal will be active low and thus the pull up transistors gate which was connected to SE signal will be ON and maintains Node SEIL and Node SEIR to high voltage (VDD). The gates of the transistor M7 and M8 are connected to BL and BLB. As we know when read cycle is activated on, the bit line will start discharge, whenever there was a significant difference of voltage set up then the Sense Enable (SEN) signal will go active high and then transistors M5 and M6 will be OFF and transistor M9 will pick up and tries to discharge the value of drain of M9 to 0, because of start of positive feedback action the difference of voltage at Node SEIL and Node SEIR will amplify to full swing. When compared to conventional sense amplifier-I, the sensing delay of this Sense Amplifier would fall down and the dip caused at the Node SEIL or Node SEIR would be less. This is because of the increase in the resistive path from Node SEIL to ground. This topology increases the sensing delay as the effective resistance from Node SEIL is increasing. In this configuration DIBL effect is relatively less compared to the previous configuration.

A. Conventional Sense Amplifier-I The literature survey on sense-amplifier circuit design has included in [8]-[10]. Fig.1 shows the most commonly used sense amplifier in SRAM which is known as cross coupled senseamplifier or voltage latched sense amplifier. Transistors M1, M2, M3, M4 forms cross coupled complementary structure and transistors M5, M6 decouples the sense amplifier once the sensing has started depending on the signal sense enable (SEN). However, the SA enable signal (SEN) should be carefully controlled for clear separation of internal node and the bit lines of the sense amplifier. Since, a feedback forms between the internal node and the bit line of SA. The other disadvantage which can be seen in voltage latched sense amplifier is current flow from output to the input of SA due to voltage difference between drain and source of PMOS (DIBL) even when SEN signal is at logic 1. This current flow makes additional power dissipation when the SA starts sensing the data from bit lines. The method of isolating the input from output of the SA will be discussed in the following section and the previous art for this method is being included in [9], [10]. In this work, we have proposed a new design for sense amplifier and analysed.

III. PROPOSED SENSE AMPLIFIER The proposed sense amplifier is shown in the figure below. This can also grouped under the category of Latch type Sense Amplifier but with reduced sensing delay and offset voltages compared to the conventional type I sense amplifier with extra two transistors. This sense amplifier will not be isolated with the bit lines of memory like how the conventional type 1sense amplifier isolates from the memory, but the leakage current will be less than conventional 1 type SA. The operation of this sense amplifier can be described as follow. In the conventional type 1 sense amplifier, PMOS transistors are used between the internal nodes (SEIL/SEIR) of SA and bit lines of the memory cell (which the SEN signal goes to PMOS access transistor between the bit lines and memory cell). In this proposed design, instead of using the PMOS access transistors between the bit lines and the SA, the bit lines were connected to the gate of the NMOS transistor (M9/M10). In this proposed SA, two NMOS were connected in series between Internal node (SEIL/SEIR) and the drain node of M11 in which SEN signal is connected to gate of M11 and bit lines (BL/BLB) were connected to gate of other transistor (M9 and M10). The operation of the sense amplifier can be explained as follow. Initially the nodes SEIL and SEIR holds 1V before the sensing starts when SEN signal is 0.

B. Conventional Sense Amplifier-II

Fig. 2 Conventional Sense Amplifier-II

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Fig. 4 Simulation Result for the Sensing Delay Fig. 3 Proposed Sense Amplifier

When considerable differential voltage set up between the bit lines, SEN signal goes active high (Comes from dummy row of SRAM), then the NMOS transistor (M11) gets ON and hence the drain voltage of transistor M11 tries to discharge to 0V, and hence depending on the data on the bit lines one of the internal node of SA (SEIR/SEIL) will also discharges towards zero because of the start of positive feedback action. Assume that both of the internal nodesof SA are initially at 1V (node SEIR and SEIL), and the memory cell storing 1at the right node of cell and 0 on left node of the cell. When read pulse comes, both of the bit lines (BL/BLB) will be pre charged to 1V. Because the left node of memory cell is holding 0V, the bit line BL will try to discharge and the other bit line stays at 1V. When the voltage difference between the bit lines becomes considerable then SEN signal goes active high, which makes the NMOS (M2) ON which results in dragging the internal node voltage (SEIR) to 0V and because of positive feedback action the internal node SEIL charges to 1V and hence the data from memory cell has transfèrred to internal node of the Sense Amplifier. This data can be converted to single bit by latching from SA.

Fig. 5 Simulation Result for Sensing Delay at different corners

IV. SIMULATION RESULTS The Proposed Sense Amplifier is designed and simulated using 28nm CMOS technology. The offset and performance of the Sense Amplifier is measured at 1V supply with load of 200fF. Timing responses of the proposed Sense Amplifier are depicted in Fig. 4 and Fig. 5.Simulation for sensing delay of Sense Amplifier (SA) at different corners are also presented. From the Fig. 5, we can observe that MAXMAX lot has the minimum delay compared to the other lot’s. The TYPTYP lot have a typical delay of around 57 ps. The offset calculations were made by performing Monte-Carlo (MC) simulations for TYPTYP lot. Simulations of 1000 were launched and calculated the success probability and then plotted CDF from the calculated success ratio. Fig. 6 Sensing delay Vs. Capacitive Load 966


The results of the sensing delay with capacitive load and cumulative distribution function are shown in the Fig. 6 and Fig. 7 respectively.

V. CONCLUSION In this paper we have designed and simulated the proposed Sense Amplifier in 28nm CMOS technology and achieved a offset of 39.284 mV and sensing delay of 57.38 ps with 1 V power supply. This proposed design gives less offset than the state-of-the-art designs. As part of future work, we would like to design a 4MB memory with this proposed sense amplifier. REFERENCES [1] [2] [3] [4] [5]

Fig. 7 Cumulative Distribution Function

[6]

The Probability Distribution Function (PDF) of the bit line differential voltage is depicted in the Fig. 8. The performance results of the proposed SA are summarized in Table I.

[7]

[8]

[9] [10]

[11]

Fig. 8 Gaussian Profile of the Differential Bit Line Voltage

TABLE I. COMPARISON WITH STATE-OF-THE-ART DESIGNS SA type

Sensing Delay

Offset (mV) Capacitive Load

CMOS Tech. (m)

Conventional I

204 ps

59

200 fF

0.028

Conventional II

0.50 ns

-

60 fF

0.35

Proposed

57.38 ps

31.284

200 fF

0.028

967

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