A Real Time EDAC System for Applications Onboard Earth ...

I. INTRODUCTION

A Real Time EDAC System for Applications Onboard Earth Observation Small Satellites Y. BENTOUTOU Centre for Space Technology Algeria

Onboard error detection and correction (EDAC) devices aim to secure data transmitted between the central processing unit (CPU) of a satellite onboard computer (OBC) and its local memory. A follow-up is presented here of some low-complexity EDAC techniques for application in random access memories (RAMs) onboard the Algerian microsatellite Alsat-1. The application of a double-bit EDAC method is described and implemented in field programmable gate array (FPGA) technology. The performance of the implemented EDAC method is measured and compared with three different EDAC strategies, using the same FPGA technology. A statistical analysis of single-event upset (SEU) and multiple-bit upset (MBU) activity in commercial memories onboard Alsat-1 is given. A new architecture of an onboard EDAC device for future Earth observation small satellite missions in low Earth orbits (LEO) is described.

Manuscript received April 7, 2009; revised December 21, 2009 and September 16, 2010; released for publication January 31, 2011. IEEE Log No. T-AES/48/1/943639. Refereeing of this contribution was handled by M. Akella. Author’s address: Centre des Techniques Spatiales (CTS), 1 Avenue de la Palestine BP13, 31200-Arzew, Algeria, E-mail: ([email protected]).

c 2012 IEEE 0018-9251/12/$26.00 ° 648

Earth observation missions using small satellites in low Earth orbit (LEO) provide fast and cheap access to space [1—4]. To make a start-up in space technologies in Algeria, the National Center for Space Technology (CNTS) has initiated a small satellite project named Alsat-1. Alsat-1 is the first step in CNTS’s plan to develop Algeria’s national space infrastructure [2]. It is part of a wider international collaboration to launch the first disaster monitoring constellation of Earth observation satellites. The primary goal of the mission is to provide daily imaging worldwide for the monitoring and mitigation of natural and man-made disasters as well as dynamic Earth observation. Alsat-1 was launched into a 686 km Sun-synchronous orbit in November 2002. This microsatellite carries specially-designed Earth imaging cameras which provide 32-m resolution imaging in 3 spectral bands (green, red, and near infrared) with an extremely wide imaging swath of 600 km on the ground that enables a revisit of the same area anywhere in the world at least every 4 days with just a single satellite. Images are stored in an 8-Gbit solid state data recorder (SSDR) for high capacity onboard storage of image data, and transmission to the ground is via an 8-Mbps S-band downlink. The Alsat-1 main onboard computer (OBC) is an Intel 80C386EX based system that was designed, built, and tested at Surrey Satellite Technology Limited (SSTL), a company owned by EADS-Astrium at the University of Surrey in Guildford, UK. The OBC plays a dual role for Alsat-1, acting as the key component of the payload computer as well as the command and control computer for the microsatellite. It has also been adopted by several other satellite projects. Fig. 1 shows the system block diagram of the OBC. It is a general purpose computer for space applications. It features 4 Mbytes of program memory which is protected by error detection and correction (EDAC) and 32 Kbytes of firmware storage erasable programmable read only memory (EPROM). The EDAC is implemented using triple modular redundancy (TMR) with voting logic, requiring 12 Mbytes in total. The board also supports multiple data inputs and can store a maximum of 128 Mbytes of data. This memory is normally referred to as the Ramdisk. Compared with the program memory there is no hardware protection on the Ramdisk, instead a double-error correcting modified Reed-Solomon (RS) (256, 252) code is used [5]. The encoding and decoding process is executed entirely in software. Data are transferred in 256-byte blocks, which comprise 252 bytes of information, three RS code bytes and one byte is used to give the capability of double byte correction. The RS (256, 252) code can

IEEE TRANSACTIONS ON AEROSPACE AND ELECTRONIC SYSTEMS VOL. 48, NO. 1

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Fig. 1. Block diagram of Alsat-1 primary OBC.

correct any number of bit errors affecting no more than two bytes per block. Thus, three or more bytes would have to be affected to cause a “severe” error under this scheme [5]. In space applications it is well known that in LEO stored digital data suffers from single-event upsets (SEUs). These upsets are induced naturally by radiation. Bit-flips caused by SEUs are a well-known problem in memory chips and EDAC techniques have been an effective solution to this problem. For the transmission of secure data between the central processing unit (CPU) of the OBC and its local random access memory (RAM), the program memory on the SSTL satellites have generally made use of Hamming (12, 8) code EDAC, or have used TMR, which is a hardware implementation that includes replicated memory circuits and voting logic to detect and correct a faulty value. These error correction techniques are well known and widely used. The Hamming (12, 8) code allows the correction of a single bit per word. For computers onboard a satellite, there is however a definite risk of two or more bit errors occurring within one byte of stored data; either from the impact of a particularly energetic event, or from a second SEU creating a second error [3—6]. As a result, later SSTL satellites made use of the TMR voting EDAC technique, which can correct any number of bit-flips in a single byte. This scheme offers excellent protection against the effects of SEUs and single-byte multiple-bit upsets (MBUs) but it cannot correct severe errors, i.e., bit errors affecting the same logical bit position in more than one of the three physical memory locations. Another

disadvantage of TMR is the large memory overhead of 200% in terms of storage. In recent work, a new real-time, low-complexity codec has been described and implemented in field programmable gate array (FPGA) technology for application to small satellite SSDRs, such as the one operating onboard Alsat-1 [3]. This paper aims to present a new architecture of an onboard EDAC device for future Earth observation small satellite missions in LEOs and its implementation in FPGA technology. The performance of the proposed EDAC device is measured and compared with three different EDAC devices, using the same FPGA technology. This paper also presents a statistical analysis of SEU and MBU activity in commercial memories onboard Alsat-1. The in-orbit observations show that the typical SEU rate at Alsat-1’s orbit is 3:67 £ 10¡7 SEU/bit/day, where 98.6% of these SEUs cause single-bit errors, 1.21% cause double-byte errors, and the remaining SEUs result in multiple-bit and severe errors. II.

ERROR DETECTION AND CORRECTION

Since Alsat-1 is placed in a LEO of 686 km, elevated levels of radiation caused by the lack of atmosphere increase the probability of SEUs. An SEU is a nondestructive error which usually affects logic cells in such a way that it can cause a bit in a memory device to change logic states. This phenomenon is caused by a false charge created by the transit of a single ionizing particle through a memory chip. There are various methods of EDAC, but the most commonly used solutions are based on Hamming and RS codes, and TMR.

BENTOUTOU: A REAL TIME EDAC SYSTEM FOR APPLICATIONS ONBOARD EARTH OBSERVATION

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Fig. 2. Block diagram of TMR-based EDAC device and its memory.

A. TMR-Based EDAC A well-known technique for providing tolerance against single hardware component failures is triplication of the component, called TMR. It is a method of protecting a program memory from both hard and soft failures. The implementation involves using three identical program memories containing the same data. The output from each memory is then processed by a voter circuit, which outputs the majority of the three inputs. As long as two of the memories are functioning properly, the output will be valid. The integrity of the program memory is important for proper operation of the OBC. A single-bit error in one memory location can cause the 80C386 to enter an endless loop or corrupt a command to an actuator. For the transmission of secure data between the CPU of the OBC and its local RAM, the memory is protected by TMR. The EDAC is implemented in two Actel A1020B 2000 gate FPGAs as shown in Fig. 2. The disadvantages of the TMR-based EDAC are the large memory overhead of three times the required memory and the large number of I/O pins required on the EDAC logic. The 4 Mbytes of memory requires an additional 8 Mbytes to implement the TMR. Each individual memory bank of the TMR can be accessed by the CPU. This allows the TMR to be tested and exercised while in orbit. The individual banks can be accessed by changing two bits of the 386EX parallel port. Fig. 3 shows the basic TMR cell. B. In-Orbit Observations Recently, in-orbit observations of SEU and MBU in the static random-access memory (SRAM) 650

memories of the OBC for the Alsat-1 in a LEO of 686 km were presented in [7] from November 2002 to June 2007. In this paper, the period of the in-orbit observations has been extended to include the Alsat-1 life-time (i.e., from November 29, 2002 to October 12, 2009). The Ramdisk memories are based on eight Samsung SYS 84000 parts of 4 Mbytes each in size. In Fig. 4, the yearly average of the number of SEU/day is plotted for the period from 29/11/2002 to 12/10/2009. This figure shows the increase of the upset rates with the increasing time. During this period, in 2,510 days of observation, 247,595 errors were logged in the memory devices, giving a mean error rate of 3:67 £ 10¡7 error/bit/day. In 2002 and 2009, the average SEU rate is 41 SEU/day and 119 SEU/day, respectively. Table I summarizes the observations from the Alsat-1 main computer “OBC-386” 32 MBytes Ramdisk. From these observations, the correct average SEU rate is 98.64 SEU/day in 8 memories of 4MBytes each. The mean SEU rate at Alsat-1’s orbit is 3:67 £ 10¡7 SEU/bit/day, where 98.6% of these SEUs cause single-bit errors, 1.21% cause double-byte errors, and the remaining SEU result in multiple-bit and severe errors. Most of the single-byte MBUs are double-bit upsets. Double-byte errors are events which affect two bytes. Severe errors are due to single-event MBUs affecting bits spread across more than two bytes. The severe (uncorrectable) error rate of these memory devices is 3:41 £ 10¡10 severe error/bit/day when using the double-error correcting modified RS (256, 252) code. Figs. 5, 6, and 7 show the yearly average of the number of single-bit, double-byte, and multiple-bit


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Fig. 3. TMR cell. TABLE I SEU Observations For Alsat-1 System monitored

OBC 386 RAMDISK Memory

EDAC code

R-S (256, 252)

Memory size

32 Mbytes

Hybrid

SYS84000RKXLI-70 (4M £ 8-bit)

Device

Samsung SEC KM684000BLT-5L 512K £ 8-BIT SRAM

Observation period

2510 days November 29, 2002— October 12, 2009

Bits monitored

268435456

No. of Single-bit errors

244150 (98.6%)

No. of Multiple-bit errors

217 (0.08%)

No. of Double-byte errors

299S (1.21%)

No. of Severe errors

230 (0.09%)

Fig. 5. Plot of yearly average of number of single-bit errors per day from November 2002 to October 2009.

Fig. 6. Plot of yearly average of number of double-byte errors per day from November 2002 to October 2009.

Fig. 4. Plot of yearly average of number of SEU/day versus time from November 2002 to October 2009.

errors per day, respectively. From these figures it’s clear that the majority of SEU cause single-bit upsets.

Fig. 7. Plot of yearly average of number of multiple-bit errors per day from November 2002 to October 2009.


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Fig. 8. Orbital position of OBC386 Ramdisk memory upsets.

Fig. 9. Daily SEU rates on Alsat-1 Ramdisk from November 29, 2002 to October 12, 2009.

Fig. 8 shows the location of upsets accumulated from 29/11/2002 to 12/10/2009 on the Alsat-1 spacecraft. The majority (¼ 80%) of SEU occurs only within the South Atlantic Anomaly (SAA), i.e., in bursts lasting for » 5—10 minutes each orbit and the other SEU are induced by the galactic cosmic rays in the high latitude regions. The number of upsets occurring outside the SAA under quiet-time conditions (i.e., no solar particle events (SPEs)) is small by comparison. The behavior shown in Fig. 4 of the increasing SEU could be explained by changes in the solar cycle over this period. 652

Solar particle events (SPEs) may have a significant impact on the upset rates. A high sensitivity to high-energy solar particles has been observed on all spacecraft exposed to the solar particles during solar activity. Fig. 9 shows the daily SEU counts on Alsat-1 from November 29, 2002 to October 12, 2009. From this figure it can be seen that 4 major solar events have induced an increased SEU number on the Alsat-1 memories. Other solar events have been observed during this period but only the events with a significant increase of high-energy protons have induced increased SEU rates on the Alsat-1


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Fig. 10. Block diagram of quasi-cyclic EDAC.

memories. Major SPEs caused upsets to occur in most of the spacecraft memory systems. The most significant event being that of October 29, 2003 which caused 790 upsets in the sensitive memory devices of Alsat-1. C. Quasi-Cyclic EDAC One class of codes for which very low complexity encoding schemes have been demonstrated are quasi-cyclic codes [8—9]. They are the most powerful available short block codes having the half-rate structure (n, n=2), where n represents the number of bits of the codeword. A code is quasi-cyclic if for any cyclic shift of a codeword by c places, the resulting word is also a codeword. The quasi-cyclic code has a minimum distance of 5. It is also linear. The code has a structure (16, 8) for allowing the most efficient use of byte-size RAM. These codes allow a correction of two error bits per stored word. A quasi-cyclic code with a structure (16, 8) and with the requisite minimum distance is described in detail in [6]. The EDAC device, when encoding, uses the quasi-cyclic codec to read an 8-bit data vector m from the 386EX microcontroller to generate a parallel 8-bit parity vector P. The data vector is stored unaltered in RAM (referred to as the data memory). Simultaneously the encoder stores the parity vector into parallel RAM (referred to as the parity memory). The initial 4 Mbytes of data memory requires an additional 4 Mbytes of parity memory to implement the quasi-cyclic EDAC [4]. The first step in the decoding process is to compute the syndrome. The syndrome consists of 8 symbols and the values are computed from the read code vector. The syndrome depends only on the error vector, and is independent of the original code vector. The error detection block receives the calculated syndrome and tries to determine the error magnitude and location. Single, multiple, and triple bit errors can be introduced to the corrected data vector. When the error port (ER) is 00, no single, two, or greater bit error is detected. In other words, the examined data

has no error. When the ER port is 01, it indicates a single-bit error occurred within the 16-bit code word. When the ER port is 10, a two-bit error has occurred within the code word. In these two cases, the error can be corrected. When the ER port is 11, errors beyond the detection capability can occur within the code word and no error correction is possible. Fig. 10 shows the block diagram of the quasi-cyclic EDAC. The implementation of the quasi-cyclic EDAC method is described in detail in [3]—[4]. III. A NEW PROPOSED EDAC SYSTEM FOR FUTURE EARTH OBSERVATION SMALL SATELLITE MISSIONS IN LEO In this section, an onboard real-time EDAC system for future Earth observation small satellite missions is proposed. It is based on the combination of the two previous described methods: TMR and quasi-cyclic EDAC methods. A very simple method for implementing EDAC for SEU mitigation in an FPGA design is to replicate redundant instances of the entire quasi-cyclic EDAC module and vote the final outputs of the modules. This is a very effective means of SEU mitigation that is easy to implement and can be performed entirely within a single device as long as the module does not utilize more than a third of the total device. In order to avoid total FPGA device failure, triple device redundancy and mitigation is proposed. This approach has the highest reliability for detecting single and multiple event upsets, multiple transient upsets, and any other functional interrupts including total device failure. To implement the quasi-cyclic EDAC device, the choice is based on FPGA technology, which is the least expensive and also available in space-qualified versions. A major advantage of FPGA is power consumption and radiation tolerance in satellite applications. The implementation of the EDAC device uses three Actel FPGAs for the encoding and decoding of the two bytes of data, and one FPGA for the majority voter circuit. This FPGA implementation is designed by technology-independent VHDL and synthesized by Synplify synthesis tool.


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Fig. 11. Block diagram of proposed EDAC system.

Fig. 11 shows a functional block diagram of the proposed EDAC system for application in future small satellite OBCs. Two (16, 8) quasi-cyclic EDAC modules were used in parallel to handle the 16 data bits of the 80C386EX microcontroller. Each (16, 8) quasi-cyclic EDAC module has been triplicated and a voter is added to vote the final outputs of the modules. A total of six (16, 8) quasi-cyclic EDAC modules were used in each FPGA device. The reliability of the system can be improved by using the proposed EDAC system. The 386EX micro controller uses 16-bit data words combined with 16-bit parity words. During memory read and write cycles, the codec can automatically detect and correct single-bit and double-bit errors. If any one of the SRAM chips should fail (data or parity memory), the program code can be mapped to run out of this failed memory chip. In this case the EDAC system will still operate with half of the entire program memory. In the case of FPGA device failure, the program code can be mapped to run out of the failed EDAC device by using one of the others FPGA devices. In this case the quasi-cyclic EDAC method is used without TMR. This is an improvement over the TMR case since the TMR case will not be able to tolerate any FPGA failure. If the voter FPGA chip should fail, both the encoded and decoded data can be mapped to run out of this failed device and thus connect directly to the buffered data bus. In this case, only one of the three FPGAs (FPGA 1 or FPGA 2 or FPGA3) is used to implement the quasi-cyclic EDAC method. The need for low cost and high performance computing systems in space has created a strong motivation for investigating new fault tolerance techniques. The use of commercial off-the-shelf 654

(COTS) components, as opposed to radiation-hardened components, has been suggested for building cheaper and faster systems [10]. COTS devices are attractive due to their relatively low power consumption and high processing performance. Radiation-hardened FPGA devices are available and are much more expensive than standard devices. Moreover, in the proposed design, SEU-immune FPGAs are based on antifuse technology that have already been tested, qualified, and applied in several SSTL missions. Both the commercial and radiation-hardened versions are immune to single-event latch up (SEL). There is no significant difference in the susceptibility of the commercial and radiation-hardened codec to SEU. The difference between them lies in tolerance to total ionization dose. Here the space-hardened version is significantly better. In the LEO environment however the total radiation dose is not a problem [11]. There is no significant difference between commercial and space-hardened in respect of linear energy transfer (LET) [12]. IV. EXPERIMENTAL RESULTS The proposed EDAC system design was implemented in VHDL as described in the previous section. A powerful FPGA design and development software “Actel Libero” was used for compilation, fitting, and simulation of the design in an Actel FPGA. The design has been verified both functionally and with the timing model generated when fitting in a FPGA. A fault injection system described in VHDL was specifically developed to test and validate the proposed technique. The fault injection system is able to randomly choose the instant of insertion of the fault, the faulty bit position, and the faulty memory


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TABLE II Design Synthesis Results EDAC Type

Hamming

TMR

Quasi-Cyclic

The Proposed EDAC

Number of FPGAs

2

2

2

4

Total cells in each FPGA

25%

12%

27%

90%

Encoding delay

10 ns

02 ns

12 ns

15 ns

Decoding delay

16 ns

10 ns

26 ns

36 ns

Memory overhead

50%

200%

100%

100%

EDAC Capability

SEC-SED in a 12-bit word

MEC-MED

DEC-DED in a 16-bit word

DEC-DED in a 16-bit word; Module and FPGA failure detection and correction.

Severe errors correction

No

No

Yes

Yes

Corrected in-orbit errors

98.6%

98.7%

100%

100%

Note: (SED: single error detection, SEC: single error correction, DED: double error detection, DEC: double error correction, MED: multiple error detection, MEC: multiple error correction.

chip. It is also able to inject the exact Alsat-1 memory faults in-orbit. The verification of the design was achieved by individual testing of smaller logical blocks of the design. Functional test benches were developed for each quasi-cyclic encoder/decoder block, the error detection block, and the chip select control block. The testability of the device was achieved by instantiating the EDAC design with an SRAM model into the top test bench, and by generating random test data (8 bits for each memory chip) with known error location and magnitude. A software version of the EDAC code was written in Matlab to generate and write test data and error information in two separate files. The test bench reads the test data file and asserts the values from this file at appropriate times onto the EDAC data bus. The error file is used to compare the location and magnitude of errors generated by the proposed EDAC design with those generated by using Matlab. Experiments in the proposed EDAC have shown that 100% of the injected in-orbit faults can be detected and corrected. The proposed EDAC based on TMR and the quasi-cyclic EDAC is needed for computers onboard a satellite when there is a definite risk of two error bits occurring at the same logical bit position in two physical memory locations (containing data and parity codes), and which cannot be corrected by TMR and the Hamming (12, 8) code. Implementation of this EDAC is transparent to the computer: there are no interrupts and no additional computation. The overall system cost is a 100% increase in stored data, which is significantly smaller than when using TMR in a comparable context (the overall system cost is a 200% increase in stored data when using TMR). The increase in delay time, from implementing the proposed EDAC code in a typical application, is small.

The chance that multiple-bit positions within a byte will be upset can be kept small by scrubbing the memory (i.e., sequentially reading, correcting, and writing back each word of memory) at a sufficiently rapid rate. In this case multiple bit-flips within a byte will be spread as single bit-flips across several bytes, thus causing no difficulty for the proposed EDAC. For the TMR case, memory scrubbing is applied for reducing double byte errors. Moreover, from the in-orbit observations, we have found that most of the single-word MBUs are double-bit upsets. In this case, the proposed EDAC circuit is therefore robust to these upsets. During the observation period 29/11/2002 to 12/10/2009, in 2510 days of observation, 2998 double-byte errors were logged in the memory devices. The investigation of the MBU error patterns shows that these double-byte errors nearly all take the form of a single bit-flip in the same logical bit position in two separate bytes within the data block. Previous observations of single-event MBUs in some of the SRAM devices [13] imply that in the majority of double-byte errors, the outcome is a single bit-flip occurring in the same logical bit position in two separate bytes of the three physical memory locations. Of the observed 247595 SEU, 1.2% of all events occur in the same logical bit position in two separate bytes of the three physical memory locations. These upsets cannot be corrected by TMR, whereas the proposed EDAC circuit is capable of correcting these severe errors. The average rate of SEU affecting the same logical bit position in two separate bytes of the three physical memory locations is 1.19 uncorrectable errors per day. In this case, the mean uncorrectable error rate at Alsat-1’s orbit is 4:4 £ 10¡9 error/bit/day using TMR.


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To measure the performance of the proposed EDAC, a comparison between the delay times in four different EDAC devices is performed using the same FPGA technology. The first EDAC is based on the Hamming code, the second one is based on TMR technique, the third one is based on the quasi-cyclic code, and the fourth one is the proposed one. On this basis for the Actel A54SX08, a typical delay in encoding is significantly greater (2 ns for the TMR FPGA to 10 ns for the Hamming EDAC to 12 ns for the quasi-cyclic EDAC and 15 ns for the proposed EDAC), while the delay in decoding increases from 10 ns to 36 ns. For the OBC operation, this is not a significant increase in overhead, compared with a relatively long access time (typically 100 ns) of the usual low-power memory employed. Table II shows synthesis results (module count usage) after running the design through the place and root software.

[2]

[3]

[4]

[5]

[6]

V. CONCLUSION This paper has presented a follow-up of some EDAC systems onboard Alsat-1. In-orbit observations of SEUs and MEUs are presented for the period between November 2002 and October 2009. In this period of time the mean SEU rate at Alsat-1’s orbit is 3:67 £ 10¡7 SEU/bit/day, where 98.6% of these SEU cause single-bit errors, 1.21% cause double-byte errors, and the remaining SEUs result in multiple-bit and severe errors. More than 80% of the SEUs occur in the SAA and the others are induced by the galactic cosmic rays in the high latitude regions. A powerful and efficient error correcting technique is proposed and implemented in FPGA technology. The EDAC is based on the combination of TMR and quasi-cyclic EDAC techniques for the routine error protection of SRAM program memory for satellites in LEO. This scheme is sufficient to handle the typical SEU rate at this LEO environment. The device is mostly transparent to the routine transfer of data between CPU and its local RAM. The proposed EDAC approach was validated by using a fault injection procedure developed in VHDL. Experiments in the proposed EDAC have shown that 100% of the faults can be detected and corrected.

[7]

[8]

[9]

[10]

[11]

[12]

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Wicks, A., et al. Advancing small satellite Earth observation: Operational spacecraft, planned missions and future concepts. In Proceedings of the 14th Annual AIAA/USU Conference on Small Satellites, Logan, UT, Aug. 21—24, 2000.

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Bekhti, M., Sweeting, M., and Sun, W. Alsat-1: The first step into space for Algeria. In Proceedings of the 53rd IAC and World Space Congress, Houston, TX, 2002, 10—19. Bentoutou, Y. A real time low complexity codec for use in low Earth orbit small satellite missions. IEEE Transactions on Nuclear Science, 53, 3 (2006), 1022—1027. Bentoutou, Y. Efficient memory error coding for space computer applications. InProceedings of the 2nd IEEE International Conference on Information & Communication Technologies: From Theory to Applications, vol. 2, Damascus, Syria, Apr. 2006, 2347—2352. Hodgart, M. S. Efficient coding and error monitoring for spacecraft digital memory. International Journal of Electronics, 73, 1 (1992), 1—36. Hodgart, M. S. and Tiggeler, H. A (16, 8) error correcting code (t = 2) for critical memory applications. In Proceedings of Data Systems in Aerospace, Montreal, Canada, May 22—26, 2000. Bentoutou, Y. and Djaifri, M. Observations of single-event upsets and multiple-bit upsets in random access memories on-board the Algerian satellite. In P. Sellin (Ed.), 2008 IEEE Nuclear Science Symposium Conference Record, Oct. 2008, 2568—2570. Underwood, C. I. and Ecoffet, R. Observations of single-event upset and multiple-bit upset in non-hardened high-density SRAMs in the TOPEX/Poseidon orbit. In Proceedings of the IEEE Radiation Effects Data Workshop, Snowbird, UT, July 1993, 85—92. Townsend, R. L. and Weldon, E. J. Self-orthogonal quasicyclic codes. IEEE Transactions on Information Theory, IT-13, 2 (Apr. 1967), 183—195. LaBel, K. A., et al. Commercial microelectronics technologies for applications in the satellite radiation environment. In Proceedings of the IEEE Aerospace Applications Conference, vol. 1, 1996, 375—390. Dyer, C. S., et al. The low Earth orbit radiation environment & its evolution from measurements using the CREAM and CREDO experiments. IEEE Transactions on Nuclear Science, 40, 6 (Dec. 1993), 1471—1478. Wang, J. J. Radiation performance of ACTEL products, rev 1. Actel Corporation, Technology Development, 1997. Underwood, C. I. and Oldfield, M. K. Observations on the reliability of COTS-device-based solid state data recorders operating in low-Earth orbit. IEEE Transactions on Nuclear Science, 47, 3 (June 2000), 647—653.


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Y. Bentoutou received his Engineer, Magister, and Doctorate degrees in electrical engineering from the University of Sidi Bel Abbes, Algeria, in 1997, 2000, and 2004 respectively. Since March 2002, he has been working as a research team leader at the Center for Space Techniques (CTS), Algeria. He is also a senior researcher in the Communication Networks, Architecture, and Multimedia laboratory at the University of Sidi Bel Abbes. From November 2000 to March 2002, he was in training at the Surrey Space Centre (SSC), University of Surrey, U.K. His principal research interests are in the fields of digital signal and image processing, medical and satellite imaging, and satellite onboard data handling. Dr. Bentoutou received the 2009 TWAS-AAS-Microsoft award for young scientists for his contributions to the fields of pattern recognition and information processing. BENTOUTOU: A REAL TIME EDAC SYSTEM FOR APPLICATIONS ONBOARD EARTH OBSERVATION

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