and the. FFT. The demodulator consists of carrier, clock and data recovery modules which ... hardware that is efficient in terms of speed, power consumption and.
N92-14213 A RECONFIGURABLE
MULTICARRIER ARCHITECTURE
S. C. Kwatra Department
and
DEMODULATOR
M. M. Jamali
of Electrical Engineering University of Toledo Toledo, Ohio 43606 419-537-2060
ABSTRACT An architecture based on parallel and pipeline design approaches has been developed for the FDMA/TDM conversion system. The architecture has two main modules namely the transmultiplexer and the demodulator. The transmultiplexer has two pipelined modules. These are the shared multiplexed polyphase filter and the FFT. The demodulator consists of carrier, clock and data recovery modules which are interactive. Progress on the design of the MCD using commercially available chips and ASIC and simulation studies using Viewlogic software will be presented at the conference.
INTRODUCTION Presently most satellite communication systems require a large earth station to supply a network with multiplexed speech and video channels. In the future, satellite communication systems will consist of a large number of small capacity, multi-service users. For these systems the conventional transmission methods of FDMA or TDMA access are no longer efficient. One approach to offer these services at a low cost to the user is to use SCPC/FDMA on the uplink and TDM on the downlink [i-3]. The problem with this type of communication is that it transfers the burden of computation on-board the satellite, where power and area requirements are critical. It can thus be seen that hardware that is efficient in terms of speed, power consumption and components needs to be developed for performing the computations conversion
on ,
a
board Multicarrier
the
satellite. Demodulator
To
perform (MCD),
the FDMA/TDM baseband switch
matrix, TDM multiplexer and modulator are required on board the satellite. The MCD consists of a transmultiplexer followed by a bank of demodulators. The transmultiplexer is required to separate the FDMA signal into individual channels. The bank of demodulators take the separated channels and recover the data from them.
This
research
is partly
supported
by
87
NASA
grant
NAG3-799.
To take advantage of the developments in the area of VLSI and digital systems, a digital implementation of the reconfigurable MCD has been proposed [3,5]. The algorithm selected for performing the transmultiplexing is the polyphase FFT method. The polyphase FFT algorithm consists of a filter bank followed by a FFT operation [4,9]. A PROgrammable DEModulator (PRODEM) which uses a single shared device to demodulate all the channels has also been proposed [5]. The demodulator consists of three modules namely carrier recovery, clock recovery and data recovery [6-8]. SYSTEM
the
Quadrature components
sampling used in
the
DESIGN
is used to digitize the analog architecture can operate
and also because the complex FFT. The RTMUX is capable different cases. The three cases
representation of demultiplexing are :
1) 800 channels at 64 Kb/s each. 2 (a) A mix of 400 channels at 64 Kb/s Mb/s each. 3) 24 channels at 2.048 Mb/s each.
and
2 (b)
is
signal so a lower
at
compatible channels
12
that rate
with the in three
channels
at
2.048
Since case 2 is a mix of two carriers, each carrier having its own demultiplexing characteristics, it is split into its two constituent parts 2(a) and 2(b) so that each case can then be demultiplexed individually. The system diagram (RTMUX) that is capable shown in Fig. 1. The demultiplexer modules, below. half of individual Module
that namely,
routes modules
of the Reconfigurable Transmultiplexer of demultiplexing the above three cases front end of the RTMUX consists of the 1,
input 2 and
FDMA signal to 3 whose functions
one
is a
of the three are described
Since cases 2(a) and 2(b) are part of case 2 and each occupies the total spectrum, they need to be split into two halves. The channels can then be demultiplexed from the two halves. 1 is used to split the input FDMA signal into two halves for
cases 2(a) and 2(b). Module or case 2(a) by reconfiguring demultiplex either case Reconfigurable Shared Filter Fig. 2. The varying the programmable
2 is designed to demultiplex either case itself. Similarly module 3 is designed 2(b) or 3 by reconfiguring itself. Bank has been designed and is shown
FFT pipeline proposed number of FFT stages FFT coefficient and
RFFT that can perform multiplexed AE (MAE), designed along with its pipeline and is shown in
in
[3,4] in the address
is made pipeline generator.
reconfigurable by and by having a A N-1/N stage
either a 2 N-1 or 2 N FYI" is shown to implement the FFT butterfly interface to the other components Fig. 4.
88
1 to A in
in Fig. 3. A operation is in the RFFT
Programmable The
PRODEM
Multiplexed Recovery (MDRM).
Demodulator
consists
of
three
main
modules
namely
Carrier Recovery Module (MCRM), Multiplexed Module (MTRM) and Multiplexed Data Recovery The hardware is constructed to demodulate all the
simultaneously. total bit rate
The is below
number of channels the maximum bit
Moreover
bit
of a group
the
rate
A MCRM channels. At the
(PRODEM)
is designed
Samples same time
to
can be varied rate sustained
of channels obtain
could
the
of several channels these samples are
as by
also
carrier
long as the the modules.
vary.
phase
are input also input
Timing Module channels
for
each
serially to this to the Multiplexed
of the module. RAM
Buffer for Samples (MRBS) which stores these samples to be operated on later by the phase recovered information of the MCRM. The output of the MCRM module will be needed by the MDRM. The in-phase and quadrature-phase shown in Fig. A
samples
MRBS of an
duration
of the
channels
are
input
to the
MCRM
as
5. is designed estimation
to interval
store and
the incoming is shown in
samples Fig. 6. The
for the MCRM
operates on the samples obtaining the carrier phase for the channels. Also, at this time the input samples are buffered in the MRBS. The MDRM uses the output of the MCRM along with the stored values of MRBS to recover the digital data. This design uses a single RAM-Latch combination at each stage to store samples of different channels corresponding A operates hardware in-phase sine and the
to each
AGC
cycle.
MDRM is designed to extract the digital information. It on the samples processed by the MCRM and MRBS. The design is shown in Fig. 7. The MDRM module utilizes the and quadrature-phase samples from the MRBS along with the cosine values of the MCRM to extract the digital data for all
channels.
At
any
time
four
values
are
input
to
this
module.
output is computed and stored in a latch preceeding the Data RAM (DDR). Also, these values are used as an input MTRM. After the necessary computations are performed the are stored in unique locations of the Digital Data RAM (DDR). A for
MTRM
tracking
the
information
is
latches
used
latches
is used
modules called
is
a
input used
to
as
namely PRODEM. The of
extract
samples by
the
preceeding
interfaced. integration
designed
an
and
is
interpolator. the
input
MCRM, These
DDR to the
MRBS, four
addressing
addressing
the
shown Its
of
the
MTRM. MDRM modules
scheme, units
timing
for
89
information in
input
MDRM. The
Fig. is
and need the
This
available
The MTRM to be
modules
Digital to the results
needed
output
combination
control all
8.
The
timing from
the
of these of the
four
is collectively appropriately
circuitry need
and
the
special
attention. shown
A de,_ign for each
in Fig.
of the
CONCLUSION
used and filter
In this paper in the design the PRODEM. bank module
consists of three modules, which The shared filter multiplexed PRODEM
both
modules
with
proper
interfaces
is
9.
AND
FUTURE
DIRECTIONS
parallel, pipeline and time sharing concepts are of a digital MCD. The MCD consists of the TMUX The TMUX is implemented by means of a shared and a pipelined FFT module. The PRODEM modules have been bank and
m_mner. at the
At board
namely optimized PRODEM
carrier, clock and data recovery for high speed demodulation. process the channels in a time
present we are and ASIC levels.
designing
both
TMUX
and
REFERENCES [1]
G.Perrota
and
G.Losquadro,
"FDMA/TDM
systems for domestic/business Conference on Digital Satellite [2] B.G.Evans and F.P.Coaldey, satellites", 243-251,
International 1988.
Journal
[3] J.Campanella demultiplexer/demodulator",
and
satellite
of Satellite S.Sayegh, NASA contract
Communication, "Onboard no cr
[4] P.J.Fernandes, "A Reconfigurable Architecture", M.S.Thesis, University of Toledo, [5] L.P.Eugene, "A Parallel Pipelined Architecture Demodulator", M.S.Thesis, University of Toledo, [6] E. multicarrier
Del
Re and R. demodulation,"
Communications, [7] A.J. Viterbi
Vol. 6, and
modulated carrierphase IEEE Transactions 1983.
on
Fantacci,
"Alternatives International
pp. 267-281, A.M. Viterbi, with application Information
and P. Daguet, and FFT," IEEE 1974.
'TDM/FDM Transactions
9o
6,
pp.
multichannel 1801827 , 1987.
Transmultiplexer I. for a Multi 1991.
for Journal
to burst Theory,
Vol
199
1988. "Non-linear
[8] F.M. Gardner, "A BPSK /QPSK sampled receivers," IEEE Transactions on 34, pp. 423-429, 1986. [13] M. Bellanger digital polyphase 1199-1205, Sep.
communication
services", Proceedings International Communication -7, pp. 155-162, 1986. "Multi carrier demodulators for OBP
onboard of
Carrier digital Satellite
estimator
digital IT-29,
of
PSK
transmission," pp. 543551,
timing error Communications,
detector
transmultiplexers: on Communication,
for COM-
pp.
,
:
""i
Control s_nala M_m.D_,m_ tO rtcoru't_une
Fig. ,
r
O_l_
I.
Reconflgurable
Transmultlplexer
m_
to
modules
(RTMUX}
clock
_
_o
o
:I
4
•
$
lllch
¢ml
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Fig.
2.
Reconflgurable
Shared
Filter
Bank
-,,I
I_0
IW i_IiIi
l
(RSFB)
i ilIiA! eO_¢l_i
Ilnl
II
I_lmnllll_
Fig.
_
lid
3. N-I/N
RlrllT
p_lltl_
Stage 91
RFFT
Fig. 4. Detailed
Implementation
_
Structure
of the
MAE
A_
in the
_aou
C_,K Tr_
Fig. 5. Multiplexed
Carrier
Recovery
Module
• "_" • "_" "I" i 71 T7[ 2"i
T_.
i Ti Tr_
ri i ri
_t_
(MCRM}
_'_" ! r, ; ;2 , 7_. , ri
_r[ ] rl i
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6.
Multiplexed
RFFT
'_'. L_.:.T... ....." RAM
Buffer
92
for
Samples
(MRBS}
Fig.
7.
Multiplexed
Data
Recovery
Module
(MDRM)
t,
_-_--_2. •
_
i
&
c'_
_
_'rOIU
Fig.
!
_
Multiplexed
Timing
I
_"
2.
8.
,
_ I
__
_,°..
r_
,
__--_
I_ ,
I
__....
2 _-_
7._: _"....
i _ ,__-_. -,__-
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Ill ___
[ _---_-_--
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:._-_
_' 93
Fig.
9. PRODEM
(MTRM)
