A Self-Normalizing Symbol Synchronization Lock ... - IEEE Xplore

IEEE TRANSACTIONS ON WIRELESS COMMUNICATIONS, VOL. 5, NO. 2, FEBRUARY 2006

347

A Self-Normalizing Symbol Synchronization Lock Detector for QPSK and BPSK Yair Linn, Member, IEEE

Abstract— This paper presents a new lock detector structure for symbol timing recovery PLLs (Phase Lock Loops), which operate in QPSK (Quaternary Phase Shift Keying) and BPSK (Binary Phase Shift Keying) receivers in AWGN (Additive White Gaussian Noise) channels. The lock detector requires only 2 samples/symbol, which coincide with those required for the Gardner timing error detector. Simulation results are used to characterize the detector’s behavior quantitatively. Both rectangular and square-root raised-cosine baseband data pulses are treated. It emerges that the lock detector has two very useful qualities. First, it is self-normalizing, and, secondly, the channel ES /N0 ratio can be easily determined from its value when the receiver is locked. Finally, a simple hardware structure is found for the lock metric computation process, which allows for its efficient implementation within an FPGA (Field Programmable Gate Array) or ASIC (Application Specific Integrated Circuit). Index Terms— BPSK, detector, lock, M-PSK, MPSK, phase locked loop, phase shift keying, PLL, PSK, QPSK, signal to noise ratio, SNR, synchronization, timing.

I. I NTRODUCTION

W

HEN constructing a BPSK or QPSK receiver a symbol synchronization circuit must be incorporated into its design ([4],[5]). That circuit, which usually takes the form of a PLL, is entrusted with the task of finding the best sampling instances of the I and Q channels, so that, ultimately, the Symbol Error Rate (SER) is minimized. The symbol synchronization PLL attempts to produce a phase-coherent replica of the symbol clock of the transmitted signal. This is carried out using a Timing Error Detector (TED), which supplies the error estimate upon which the PLL operates. A TED suggested by Gardner in [1] has come to be very popular, due mainly to the fact that it provides good performance while requiring only two samples per symbol. An essential complement to any PLL, including the one under discussion, is a lock detector. Lock detectors operate by producing a lock metric which is compared to a threshold; when that threshold is surpassed, the PLL is considered to be locked. In terms of lock detectors which work in conjunction with the Gardner TED, two lock detectors have been proposed by Karam et al. in reference [2], one which requires four samples per symbol (called “Detector A” in that paper), and another which requires two samples per symbol (which they called “Detector B”). In fact, the lock detector suggested here Manuscript received January 1, 2003; revised October 24, 2003 and January 1, 2004; accepted December 30, 2004. The associate editor coordinating the review of this paper and approving it for publication was L. Hanzo. This work was supported by the National Sciences and Engineering Research Council of Canada (NSERC). The author is with the University of British Columbia, 2111 Lower Mall, Vancouver BC, Canada V6T-1Z4 (e-mail: [email protected]). Digital Object Identifier 10.1109/TWC.2006.02014.

is related to “Detector B” in [2], and it can be said that this paper’s purpose is the definition and exploration of a modified version of that detector. Though similar to the detector in [2], the proposed detector will be shown to possess several advantages, which will now be outlined. First, the suggested lock detector will be shown to be selfnormalizing, or, put another way, signal-level1 independent. What this means is that the proposed lock detector will be highly resistant to imperfect AGC (Automatic Gain Control) circuit behaviour, a quality which is particularly important when demodulating fading signals whereupon the AGC’s operation is often quite nonideal. Secondly, it shall be seen that there is a very simple way to estimate the ES /N0 ratio from the lock metric. Thirdly, it shall be shown that the detector has a particularly compact hardware structure that is ideal for implementation within an ASIC or FPGA, and hence provides a method by which lock detection can be done “on chip” and in real time. The layout of this article proceeds as follows. First, in Section II we outline the signal and receiver models upon which the discussion applies. In Section III we define the detector and discuss its hardware implementation. Then, Section IV investigates the detector’s probability distribution, and a method is developed for deciding on the appropriate lock thresholds according to the desired lock probabilities and false alarm rates. Finally, Section V is devoted to formulating conclusions. II. S IGNAL AND R ECEIVER M ODELS Let us denote the baseband signal as m(t) = ∞ √ √ ar / 2 + j · br / 2 p(t − rT ), where we use p(t) to

r=−∞

denote the data pulse and 1/T for the symbol rate. For independent data QPSK ar , br ∈ {−1, 1} and√are√mutually streams. For BPSK, ar ∈ − 2, 2 and ∀r, br = 0. In this paper, we shall deal with the cases of rectangular important 1/T − T /2 ≤ t ≤ T /2 baseband pulses, i.e. p(t) = , 0 otherwise as well as SRRC (Square-Root Raised-Cosine) pulses ([10] cos((1+α)πt/T )+ sin((1−α)πt/T )

4αt/T √ . Using τi to eq. 68.15) p(t) = 4α π T (1−16α2 t2 /T 2 ) signify the signal’s propagation delay, the modulated signal at the entrance of the I-Q demodulator is [4] sm (t) = Re[m(t − τi )ejωi t+jθi ] and that signal is corrupted by an

1 The term signal level as it is employed in this paper should not be confused with the term ES /N0 ratio. The former refers to the total signal+noise power at the inputs of the samplers in Fig. 1, while the latter refers to the signalto-noise ratio of that signal. This shall be elaborated upon shortly.

c 2005 IEEE 1536-1276/06$20.00

348


AWGN channel. The receiver has the general structure of Fig. 1, where: 1. 1/TS = 2/T is the sample rate. 2. n(t) ∼ N (0, N0 W ) where W is the width of the IF (Intermediate Frequency) filter (not shown). 3. K represents the equivalent physical gain associated with the circuit. Generally, K is a slow function of time that is controlled by the AGC, which regulates its value in order to attain desired signal amplitude levels at the inputs of the I and Q samplers (ideally, the nominal signal level is such that the samplers never saturate yet their entire dynamic range is exploited). It can be shown (see [14] chap. 9) that, as well as being a function of the AGC’s parameters, K is also a function of the ES /N0 . For simplicity, K is assumed the same in the I and Q arms, though this is not a necessary condition for the analysis in this paper to be valid and in fact the I and Q arms may have arbitrarily different K’s. 4. Δω is the frequency difference between the local and received carriers, and θo is the phase of the local carrier. We shall assume, unless otherwise indicated, that the carrier synchronization loop is ideally locked, i.e. Δω = 0 and θi = θo . However it is declared without proof that the proposed detector works quite well in the presence of small2 carrier frequency errors. 5. The matched filter h(t) = p(−t) is assumed ideal. When in this paper the terms “signal-level dependence” or “AGC-dependence” are cited, this alludes to a dependence on the AGC-controlled gain K. Since K is arbitrary and multiplies both the signal and noise terms in each of the I and Q arms, it is clear that such a dependence of the lock detector characteristics or threshold is a mathematical and practical liability, it brings in K’s dynamic range as a quantity that needs to be taken into account as part of the lock detection circuit’s parameters. Even more troubling, since K is not a constant but is rather a function of time controlled by the AGC, any dependence on K implies a dependence of the lock detector on the AGC’s behavior, often through a distinctly nonlinear relationship. The independence of the suggested lock detector vis-à-vis K is one of its primary advantages with respect to the detectors in [2], because it decouples the lock detector’s threshold and value from the AGC’s operating point and performance. This aspect of the detector’s characteristics is elaborated upon throughout the ensuing sections. III. D ETECTOR D EFINITION AND I MPLEMENTATION A. Basic Definitions and Equations We use the notation τî to refer to the receiver’s estimate of τi . We define the symbol synchronization timing error3 as Δ τ = (τi − τî ) mod T , with the modulo operation’s destination 2 Defined as Δω/2π > (Δfmin · T ) , 5 where Δfmin is the minimum frequency error for which there is a desire for the out-of-lock state to be detected reliably. Equations (7)-(9) can be said to be contingent upon that assumption.

(assuming6 Γ < μS (χ)): Es = χ PD = P sN > Γ N 0

∞ −(υ−μ (χ))2 · N 1 S 4 dυ ≥√ e 4π/N Γ N = 12 erf c (Γ − μ (χ)) S 4 PF A = P ( sN > Γ| noise only input)

∞ −υ2 · N 1 N 4 dυ = ≤ √1 e 2 erf c 4 ·Γ 4π/N

(10)

(11)

Γ

from which it immediately follows that a suitable Γ and N are given by: erf c−1 (2PF A ) · μS (χ) , erf c−1 (2PF A ) − erf c−1 (2PD ) 2 erf c−1 (2PF A ) − erf c−1 (2PD ) N =4 μS (χ) Γ=

C. Lock and False Alarm Probabilities and Circuit Parameter Determination Dealing first with QPSK, from eq. (8), at a given threshold Γ > 0, for a given input ES /N0 ratio denoted χ, the lock detection probability PD and false alarm probability PF A are

Using similar derivations regarding the case of BPSK and sI,N , one arrives at: Γ=

5 Typically, we would have Δf min < ΔfL , where ΔfL is the lock-range ([5],[6]) of the symbol synchronization PLL. Thus, when the timing frequency error is smaller than Δfmin we would transition to the locked state, hence avoiding the problem just outlined.

(12)

erf c−1 (2PF A ) · μB (χ) , erf c−1 (2PF A ) − erf c−1 (2PD )

6 We are making the implicit assumption that we are disinterested in detecting lock for any ES /N0 = λ for which Γ ≥ μS (λ), since for all Es /N0 = λ for which Γ ≥ μS (λ), we have PD ≤ 0.5.

352


V. C ONCLUSIONS A new symbol synchronization lock detector for QPSK and BPSK was presented. The subsequent analysis revealed that it is self-normalizing, hence decoupling the symbol lock detection process from the AGC circuit and considerably simplifying the computation of the lock thresholds, the lock probabilities, and the false alarm rates. It was found that the ES /N0 ratio can also be estimated from the lock metric value. A simple hardware implementation for the detector was outlined, one which is particularly appealing for implementation within an ASIC or FPGA. For all of the above reasons, the detectors suggested in this paper have immediate practical applications in contemporary receivers. ACKNOWLEDGMENT Fig. 5. Required number of symbols 2 · N that are needed to achieve a desired PD and PF A , with χ = 1 dB, for sN (for QPSK) and sI,N (for BPSK).

The author would like to thank his supervisor Prof. Matthew J. Yedlin (University of British Columbia) and Prof. Shmuel Zaks (Technion Israel Institute of Technology) for their continued mentorship, encouragement and support. Additionally, the author would like to thank the editor Prof. Lajos Hanzo for his guidance, and the anonymous reviewers for their efforts and their helpful feedback. R EFERENCES

Fig. 6. Required threshold Γ that is needed to achieve a desired PD and PF A , with χ = 1 dB, for sN (for QPSK) and sI,N (for BPSK).

N=

erf c−1 (2PF A ) − erf c−1 (2PD ) μB (χ)

2 (13)

Unsurprisingly, all the quantities in eqs. (10)-(13) are completely independent of K. Refer to Fig. 5 and Fig. 6 for an example of the use of (12)-(13) to determine7 the required Γ and N needed to fulfill requirements of PD and PF A for a given minimum ES /N0 of χ. Note that, in those figures, the results for α = 1 apply for rectangular pulses as well. This is because the expected value of the lock detector for both pulse shapes is the same (see Fig. 3), and hence (from (12)-(13)) so are Γ and N . 7 Eqs. (10) and (11) are inequalities because the variance of s N is bounded by the limit 2/N (see (7)), and not necessarily equal to it. Thus employment of (12) to determine N will produce conservative (i.e. larger than needed) values of N . For similar reasons, the use of (13) for sI,N and BPSK will yield conservative values of N .

[1] F. M. Gardner, “A BPSK/QPSK Timing Error Detector for Sampled Receivers,” IEEE Trans. Commun., vol. 34, no. 5, pp. 423-429, May 1986. [2] G. Karam, V. Paxal, and M. Moeneclaey, “Lock Detectors for Timing Recovery,” Proc. ICC , pp. 1281-1285, June 1996. [3] A. D. Whalen, Detection of Signals in Noise. New York: Academic Press, 1971. [4] J. G. Proakis, Digital Communications, 4th ed. New York: McGraw-Hill, 2001. [5] H. Meyr, M. Moeneclaey, and S. A. Fechtel, Digital Communication Receivers. New York: John Wiley & Sons, 1997. [6] F. M. Gardner, Phaselock Techniques, 2nd ed. New York: John Wiley & Sons, 1979. [7] H. Gudbjartsson and S. Patz, “The Rician distribution of noisy MRI data,” Magnetic Resonance Medicine, vol. 34, no. 6, pp. 910–914, Dec. 1995. [8] M. R. Spiegel, Mathematical Handbook of Formulas and Tables. Singapore: McGraw-Hill International Edition, 1990. [9] R. L. Peterson, R. E. Ziemer, and D. E. Borth, Introduction to Spread Spectrum Communications. New Jersey: Prentice Hall, 1995. [10] J. D. Gibson (editor), The Communications Handbook, 2nd ed. Boca Raton: CRC Press, 2002. [11] Y. Linn, “A Symbol Synchronization Lock Detector and SNR Estimator for QPSK, with Application to BPSK,” Proc. 3rd IASTED International Conf. on Wireless and Optical Communications (WOC 2003), pp. 506514, July 2003. [12] Y. Linn, “Quantitative Analysis of a New Method for Real-Time Generation of SNR Estimates for Digital Phase Modulation Signals,” IEEE Trans. Wireless Commun., vol. 3, pp. 1984-1988, Nov. 2004. [13] Y. Linn, ”A Hardware Method for Real-Time SNR Estimation for MPSK using a Symbol Synchronization Lock Metric,” Proc. 9th Canadian Workshop on Information Theory (CWIT 2005), pp. 247-251, June 2005. [14] A. Blanchard, Phase-Locked Loops Application to Coherent Receiver Design. New York: John Wiley & Sons, 1976. [15] H. Gudbjartsson and S. Patz, “Erratum to the Rician distribution of noisy MRI data,” Magnetic Resonance Medicine, vol. 36, pp. 331–333, Aug. 1996.

LINN: A SELF-NORMALIZING SYMBOL SYNCHRONIZATION LOCK DETECTOR FOR QPSK AND BPSK

Yair Linn (M’01) received his B.Sc. (honors) in computer engineering from the Technion Israel Institute of Technology, Haifa, Israel, in 1996. He is currently pursuing the Ph.D. degree in electrical engineering at the University of British Columbia, Canada, under the direction of Prof. M. J. Yedlin. In the years 1996-2001 he was employed as an Electrical Engineer in the Israeli Ministry of Defense, where he worked with the development, implementation, and deployment of wireless communications systems. His current research interests include synchronization in wireless receivers, estimation of wireless channel

353

parameters, and implementation of real-time digital signal processing algorithms in FPGAs. Mr. Linn was awarded the Jean MacDonald Graduate Fellowship scholarship as a winner of the University Graduate Fellowship competition at UBC in 2002. In April 2003, he was awarded a postgraduate scholarship by the National Sciences and Engineering Research Council of Canada (NSERC), as a winner of the 2003/4 NSERC Postgraduate Scholarship Competition. In April 2005, he was awarded an NSERC Canadian Graduate Scholarship as a winner of the 2005/6 NSERC Postgraduate Scholarship Competition. In November 2005 he was awarded the Bell Canada 125th Anniversary Graduate Scholarship.