A Self-Testing Platform with a Foreground Digital Calibration ... - MDPI

applied sciences Article

A Self-Testing Platform with a Foreground Digital Calibration Technique for SAR ADCs Yi-Hsiang Juan 1 , Hong-Yi Huang 2 , Shuenn-Yuh Lee 1 , Shin-Chi Lai 3 , Wen-Ho Juang 1 and Ching-Hsing Luo 1, * 1 2 3

*

The Department of Electrical Engineering, National Cheng Kung University, Tainan 701, Taiwan; [email protected] (Y.-H.J.); [email protected] (S.-Y.L.); [email protected] (W.-H.J.) The Department of Electrical Engineering, National Taipei University, Taipei, 23741, Taiwan; [email protected] The Department of Computer Science and Information Engineering, Nanhua University, Chiayi 62249, Taiwan; [email protected] Correspondence: [email protected]; Tel.: +886-6-2757575-62375; Fax: +886-6-234-548

Academic Editor: Teen-Hang Meen Received: 29 May 2016; Accepted: 26 July 2016; Published: 29 July 2016

Abstract: This study presents a self-testing platform with a foreground digital calibration technique for successive approximation register (SAR) analog-to-digital converters (ADCs). A high-accuracy digital-to-analog converter (DAC) with digital control is used for the proposed self-testing platform to generate the sinusoidal test signal. This signal is then implemented using an Arduino board, and the clock signal is generated to test the ADCs. In addition, fast Fourier transform and recursive discrete Fourier transform (RDFT) processors are adopted for dynamic performance evaluation and calibration of the ADCs. The third harmonic distortion caused by the non-linearity of the track-and-hold circuit, the mismatch of the DAC capacitor array, and the direct current (DC) offset of the comparator can be calculated using the processors to improve the ADC performance. The advantages of the proposed platform include its low cost, high integration, and no need for an extra analogy compensation circuit to deal with calibration. In this work a 12 bit SAR ADC and an RDFT processor are used in the Taiwan Semiconductor Manufacturing Co., Ltd. (TSMC) 0.18 µm standard complementary metal–oxide–semiconductor (CMOS) process with a sampling rate of 18.75 kS/s to validate the proposed method. The measurement results show that the signal-to-noise and distortion ratio is 55.07 dB before calibration and 61.35 dB after calibration. Keywords: analog-to-digital converters (ADCs); digital calibration method; self-testing; successive approximation register ADC (SAR)

1. Introduction An analog-to-digital converter (ADC) is an important component in various areas, such as communication and biomedical systems, among others. The performance limitations of the ADCs are mainly dominated by the static and dynamic non-linearity effects, which cause the harmonic distortion in the output power spectrum. These non-linearities slightly deteriorate the overall system performance, and also increase the sensitivity to the process variation and system interface noise because of the technology scaling into the nano-scale region. A calibration method is thus essential to ensure system quality [1,2]. The successive approximation register (SAR) analog-to-digital converter (ADC) has the advantages of medium speed conversion and medium to high resolution. It is therefore very suitable for biomedical and communication systems. With regard to the implementation of most SAR ADCs, the performance should be maintained by the internal circuits, including the track-and-hold (T/H) circuit, the DAC capacitor array, and the comparator circuit. However, the non-linearity of

Appl. Sci. 2016, 6, 217; doi:10.3390/app6080217

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the internal circuits always limits the performance of the ADCs. This is the reason why a calibration method is required to overcome this problem. In this paper we focus on the digital calibration method. For example, the lookup table or the state-space technique is a common calibration method for ADC error correction [3]. The correction in this approach is based on a table that uses pre-calculated values or the slope of the input signal. However, the drawback of this method is the requirement of a large memory size, thus consuming more areas. An equalization-based digitally calibrated method is proposed in Reference [4]. The advantage of this is the reduction of both the ADC testing time and the convergence time. In addition, this paper utilizes the least mean squares (LMS) algorithm to correct and calibrate the ADC error, similar to that in Reference [5]. An internal redundancy dithering (IRD) technique is reported in Reference [6]. The IRD method based on bit-weight calibration employs a pseudorandom bit sequence to determine the threshold values. The method utilizes the LMS algorithm to calibrate the SAR ADC error. However, the main drawback of the approaches in References [5,6] is that a high resolution ADC is required, which is impractical in actual implementation. A fast-Fourier transform (FFT)-based calibration method for pipelined ADC is reported to calibrate the capacitor mismatch and non-linearity error of the operational amplifier (OPAMP) [7]. However, the shortcoming of the FFT process is the consumption of more power because all frequency bins should be computed during the operation mode. Juan et al. proposed an RDFT-based calibration algorithm to overcome this problem [8], because the RDFT processor has the advantages of variable transform length, lower complexity, and less hardware cost. In this paper, we present a self-testing platform based on previous works [7,8] to measure the ADC performance using the proposed testing stimulus and compensate for the error using a simplified digital calibration algorithm. A 12 bit SAR ADC and an RDFT processor are implemented in the TSMC 0.18 µm to verify the proposed platform. The output is analyzed using MATLAB (version 7.6.0.324 (R2008a), The MathWorks, Natick, MA, USA, 2008), including the performance calculation and ADC calibration. 2. Proposed Self-Test Platform 2.1. Conventional SAR ADC Architecture The basic block of the traditional SAR ADC includes a track-and-hold circuit (T/H), an N-bit DAC capacitor array, a comparator circuit, and a SAR controller (Figure 1). The SAR ADC generally uses a binary-weighted method to implement the circuit [9]. According to the results for the switching capacitor array, the digital output signal can be obtained as Logical High (“1”) or Logical Low (“0”). In addition, some biomedical applications require an adaptive resolution using a multi-switch operated in 8 bit or 12 bit mode [9]. However, the non-linearity of the multi-switch in the T/H circuit will limit the SAR ADC performance. The proposed calibration method also has the capability of eliminating the non-linearity and enhancing the performance of the multi-mode SAR ADC. Figure 2 depicts the multi-mode SAR ADC structure. In this, switch S2 is applied to control the two operation modes, namely the 8 bit and 12 bit modes. The bootstrapped switch is also adopted to provide a small on-resistance with a constant value and better linearity.

multi‐switch operated in 8 bit or 12 bit mode [9]. However, the non‐linearity of the multi‐switch in  the T/H circuit will limit the SAR ADC performance. The proposed calibration method also has the  capability of eliminating the non‐linearity and enhancing the performance of the multi‐mode SAR  ADC. Figure 2 depicts the multi‐mode SAR ADC structure. In this, switch S2 is applied to control  the  two  operation  modes,  namely  the  8  bit  and  12  bit  modes.  The  bootstrapped  switch  is 3 also  Appl. Sci. 2016, 6, 217 of 13 adopted to provide a small on‐resistance with a constant value and better linearity. 

 

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Figure 1. Traditional  Traditional successive approximation register Analog-to-Digital converter Figure  1.  successive  approximation  register  (SAR) (SAR) Analog‐to‐Digital  converter  (ADC)  (ADC) structure. structure. 

  Figure 2. Multi‐mode SAR ADC structure.  Figure 2. Multi-mode SAR ADC structure.

2.2. Proposed Calibration Method  2.2. Proposed Calibration Method A  previous  work  [8]  derived  the  proposed  calibration  formula  using  the  FFT  and  a  cosine  A previous work [8] derived the proposed calibration formula using the FFT and a cosine wave wave input  signal.  The  third  harmonic distortion  value a3  can  be detected  by  an  RDFT  processor.  input signal. The third harmonic distortion value a3 can be detected by an RDFT processor. The error The error factor Δn can be further calculated for the calibration. In addition, the calibration code was  factor ∆n can be further calculated for the calibration. In addition, the calibration code was only used only  used  for  the  first‐time  test  to  reduce  the  complexity.  This  calibration  method  can  not  only  for the first-time test to reduce the complexity. This calibration method can not only compensate for compensate  for  the  error  caused  by  the  capacitor  mismatch  and  DC  offset  in  the  traditional  ADC  the error caused by the capacitor mismatch and DC offset in the traditional ADC but it can also be but it can also be applied to calibrate the T/H circuit in the multi‐mode SAR ADC (Figure 2).  applied to calibrate the T/H circuit in the multi-mode SAR ADC (Figure 2). The main calibration equation can be written as follows:  The main calibration equation can be written as follows: ˆ  A   1.696  C ˙  a  20 logA ˆ ∆n ˆn 1.696 ˆ Cn `n 1.696  1.696  Vos,  ,  ˆ V os 2048   2048

3 20log a3 “

(1) (1)

where A is the amplitude of the cosine wave, C where A is the amplitude of the cosine wave, Cnn is the value of each capacitor ratio, Δ is the value of each capacitor ratio, ∆nn is the error  is the error factor of each capacitor mismatch, and V os is the DC offset. The DC offset voltage of the comparator  factor of each capacitor mismatch, and V os is the DC offset. The DC offset voltage of the comparator circuit can be expressed as:  circuit can be expressed as:

    (2) (2)   W R 2 2      L   are the overdrive voltage, transistor size, and threshold voltage of the ˙22 ˆ ˙2 W W{Lq 2  V ∆R V ∆ p ov ov 22  Vov RDD ` Vov L  `  p∆V Vttq , ,  2 pW{Lq  2 RD  

d ˆ

V Vos “ os

D

where V ov , W/L, and V t differential to Equation (2), the threshold is a staticvoltage  offset, which where  Vov, pair, W/L, respectively. and  Vt  are According the  overdrive  voltage,  transistor  size,  voltage and  threshold  of  the  does not affect the dynamic performance of the ADC. Meanwhile, both the overdrive voltage and differential  pair,  respectively.  According  to  Equation  (2),  the  threshold  voltage  is  a  static  offset,  transistor size will degrade the ADC performance. Some approaches have been used to overcome which does not affect the dynamic performance of the ADC. Meanwhile, both the overdrive voltage  this and improve the DC offset, suchperformance.  as reducing the overdrive voltage or increasing and problem transistor  size  will  degrade  the  ADC  Some  approaches  have  been  used the to  comparator size. However, the drawbacks of these methods are the decrease in the comparison speed overcome  this  problem  and  improve  the  DC  offset,  such  as  reducing  the  overdrive  voltage  or  and higher power consumption, respectively. Therefore, the problem can be overcome using the RDFT increasing the comparator size. However, the drawbacks of these methods are the decrease in the  processor in aspeed  system-on-a-chip calibrate the ADC error [8]. Generally, if a DCthe  offset value will comparison  and  higher  to power  consumption,  respectively.  Therefore,  problem  can  be be  very small, it will not affect the performance of the ADC. However, if a DC offset is a bigger value, overcome using the RDFT processor in a system‐on‐a‐chip to calibrate the ADC error [8]. Generally, 

if a DC offset value will be very small, it will not affect the performance of the ADC. However, if a  DC  offset  is  a  bigger  value,  the  performance  of  the  ADC  will  be  decreased.  Figure  3  shows  the  MATLAB simulation results with different DC offset variations. 

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the performance of the ADC will be decreased. Figure 3 shows the MATLAB simulation results with 4 of 13  variations.

Appl. Sci. 2016, 6, 217  different DC offset

Output Spectrum of ADC

Power spectral density(dB/FS)

Power spectral density(dB/FS)

Output Spectrum of ADC 0

SNDR = 73.07 dB ENOB = 11.8 bit

-50

-100

-150

0

50

100 150 Frequency (kHz)

0

-50

-100

-150

200

SNDR = 72.92 dB ENOB = 11.8 bit

0

Without offset

Power spectral density(dB/FS)

Power spectral density(dB/FS)

-100

0

50

200

Output Spectrum of ADC

SNDR = 70.05 dB ENOB = 11.3 bit

-50

-150

100 150 Frequency (kHz)

With 0.5mV DC offset

Output Spectrum of ADC 0

50

100 150 Frequency (kHz)

0

-50

-100

-150

200

SNDR = 68.32 dB ENOB = 11.0 bit

0

50

100 150 Frequency (kHz)

200

With 2mV DC offset

With 1.5mV DC offset

 

Figure  3.  MATLAB  Figure 3. MATLAB simulation  simulation result  result with  with different  different direct  direct current  current (DC)  (DC) offset  offset variation  variation (The  (The signal‐to‐noise and distortion ratio, SNDR; The effective number of bits, ENOB).  signal-to-noise and distortion ratio, SNDR; The effective number of bits, ENOB).

The  calibration equation equation can can bebe  rewritten  Here,  assume  =  and 1  V, the and  the  DC  The calibration rewritten asas  (3).(3).  Here, wewe  assume thatthat  A = A  1 V, DC offset offset (V os) is 2 mV:  (V os ) is 2 mV: p10a3 ´ 0.0033q ˆ 2048 ∆n 10 “ a3  0.0033  2048 , n “ 11 „ 0, (3) 1 ˆ 1.696 ˆ Cn (3) n  , n  11 ~ 0 ,   Cn 1RDFT 1.696processor In addition, the input signal of the can be a sine or cosine wave signal. Therefore, the power spectra of the RDFT have real (Re) and imaginary (Im) part energies, respectively, in which In  addition,  the  input  signal  of  the  RDFT  processor  can  be  a  sine  or  cosine  wave  signal.  a3 is equal to: bhave  real  (Re)  and  imaginary  (Im)  part  energies,  Therefore,  the  power  spectra  of  the  RDFT  2 2 (4) respectively, in which a3 is equal to:  20log pReq ` pImq ,





The value of a3 can be substituted as the real and imaginary parts. Therefore, Equation (3) can be 2 2 (4) 20 log Re  Im ,  further simplified as follows:

   

b ˆ ˙ The value of a3 can be substituted as the real and imaginary parts. Therefore, Equation (3) can  1 log pReq2 `pImq2 2 10 ´ 0.0033 ˆ 2048 be further simplified as follows:  ∆n “ , n “ 11 „ 0, (5)  1 log  Re 2 1 Imˆ21.696 ˆ Cn 

 10

2

 0.0033   2048

where Cn is the value of each capacitor array. Equation (5) to evaluate the error factor (∆(5) n ).  can be ,used ,  n 11 ~ 0    n The final correction code utilized to compensate for the error is further obtained as follows:

1 1.696  Cn

11

10

0

Dnew “ Bit12 ˆ 2 ˆ p2 ˘ ∆12 q ` Bit11 ˆ 2 ˆ p2 ˘ ∆11 q ` ¨ ¨ ¨ ` Bit1 ˆ 2 , (6) where Cn is the value of each capacitor array. Equation (5) can be used to evaluate the error factor  (Δn). The final correction code utilized to compensate for the error is further obtained as follows: 

D

new

 Bit12  211   2  12   Bit11  210   2   11     Bit1  2 0 , 

(6)

The third harmonic distortion can be significantly reduced when the compensation is finished.  The  ADC  performance  can  then  be  improved.  In  addition,  the  residue  errors  are  not  only  compensated, but also corrected by fine‐tuning. 

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The third harmonic distortion can be significantly reduced when the compensation is finished. The ADC performance can then be improved. In addition, the residue errors are not only compensated, but also corrected by fine-tuning. 2.3. MATLAB Verification MATLAB is used to simulate and verify the proposed self-testing platform technique and calibration method and build the behavior model, which includes the 12 bit SAR ADC, RDFT computation, signal generator, and proposed calibration. In addition, a 1% capacitor mismatch, 2 mV DC offset, thermal noise, sampling jitter and switch nonlinearity are adopted in the 12 bit SAR ADC model to demonstrate the proposed calibration. Generally, the backgate effect of the switch transistor is the main source of its resistance nonlinearity. So, the input-dependent switch transistor can be defined as: 1 ´ ¯ R“ , (7) W µCox L rVDD ´ Vth s In this work, the parameters of the sampling switch are determined by the virtual process, so the backgate effect value of this switch transistor is: Rp “

1 86 ˆ 10´6 p0.18q r1.8 ´ p´0.5qs

Rn “

« 0.911k,

1 « 0.358k, 387 ˆ 0´6 p0.18q r1.8 ´ 0.5s

(8)

(9)

It is worthily noted that the body effect problem is not considered in this issue. In this work, the switch model given by using the MATLAB Simulink tool is the transmission gate (pmos and nmos) architectures, and then we further determine the switch nonlinearity error according to the virtual CMOS process parameter. After putting these parameters into Equation (7), we can process the performance analysis of the SAR ADC under the conditions of a 1% capacitor mismatch, 2 mV DC offset, thermal noise, sampling jitter and switch nonlinearity error. Figure 4a shows the simulation result. It can be easily observed that the distortion deteriorates the ADC performance in the simulation result with a 5 Hz input frequency at a sampling rate of 126.26 Hz. Furthermore, the third harmonic distortion tone is ´55.29 dB without calibration and ´80.97 dB with calibration (Figure 4b). The signal-to-noise and distortion (SNDR) can be improved from 48.32 dB to 65.65 dB, while the effective number of bits (ENOB) is improved from 7.73 bits to 10.61 bits. However, the proposed calibration method cannot compensate for the error of the thermal noise, sampling jitter and sampling switch nonlinearity, which generated the harmonic distortion at the output power spectrum, so the ADC such as SNDR and spurious-free dynamic range (SFDR) cannot achieve the ideal ADC performance. Figure 5 shows the time domain result, and it is clear that the signal can be improved when the proposed calibration method is applied. Figure 6 shows the simulation result with capacitor mismatch only and analyzes the performance of the ADC before/after calibration. According to the simulation result, the third harmonic distortion tone is ´65.59 dB without calibration and ´90.81 dB with calibration. The ENOB can be improved from 9.92 bits to 11.11 bits. In addition, Figure 7 shows the simulation result with 2 mV DC offset only and analyzes the performance of the ADC before/after calibration. According to the simulation, the proposed calibration method can reduce the DC offset error and enhance the performance of the ADC.

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  (a)  (a) 

   

  (b)  (b) 

   

Figure 4. Simulation result from the MATLAB tool (a) without and (b) with calibration. (Total third  Figure 4. Simulation(a)  result from the MATLAB tool (a) without and (b) with (b)  calibration. (Total third Figure 4. Simulation result from the MATLAB tool (a) without and (b) with calibration. (Total third  harmonic distortion, THD3; Spurious‐free dynamic range, SFDR).  harmonic distortion, THD3; Spurious-free dynamic range, SFDR). harmonic distortion, THD3; Spurious‐free dynamic range, SFDR).  Figure 4. Simulation result from the MATLAB tool (a) without and (b) with calibration. (Total third  harmonic distortion, THD3; Spurious‐free dynamic range, SFDR). 

  Figure 5. Time domain result with/without calibration.  Figure 5. Time domain result with/without calibration.  Figure 5. Time domain result with/without calibration. Figure 5. Time domain result with/without calibration. 

(a)  (a) 

   

 

   

(b) (b)

Figure 6. Simulation result from the MATLAB tool with capacitor mismatch only (a) before and (b)  (a)  (b) Figure 6. Simulation result from the MATLAB tool with capacitor mismatch only (a) before and (b)  after calibration.  after calibration.  Figure 6. Simulation result from the MATLAB tool with capacitor mismatch only (a) before and (b)  Figure 6. Simulation result from the MATLAB tool with capacitor mismatch only (a) before and after calibration.  (b) after calibration.

 

   

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    (a)  (b) (a)  (b)     (a)  Figure 7. Simulation result from the MATLAB tool with 2 mV DC offset only (a) before and (b) after  (b)

 

Figure 7. Simulation result from the MATLAB tool with 2 mV DC offset only (a) before and (b) after  calibration.  Figure 7. Simulation result from the MATLAB tool with 2 mV DC offset only (a) before and (b) after  calibration.  Figure 7. Simulation result from the MATLAB tool with 2 mV DC offset only (a) before and calibration.  (b) after calibration.

2.4. Testing Stimulus Signal  2.4. Testing Stimulus Signal  Generally,  the  dynamic  performance  of  the  ADC,  including  the  total  harmonic  distortion,  2.4. Testing Stimulus Signal  2.4. Generally,  Testing Stimulus Signal performance  of  the  ADC,  including  the  total  harmonic  distortion,  the  dynamic  signal‐to‐noise  ratio,  signal‐to‐noise  and  distortion  ratio  (SNDR),  and  effective  number  of  bits  Generally,  the  dynamic  performance  of  the  ADC,  the  total  harmonic  distortion,  signal‐to‐noise  signal‐to‐noise  and  distortion  ratio including  (SNDR),  and  number  of  bits  Generally,ratio,  the dynamic performance of the ADC, including the effective  total harmonic distortion, (ENOB), is evaluated by stimulation using the input signal of a sinusoidal waveform and analysis  signal‐to‐noise  ratio,  signal‐to‐noise  and  distortion  ratio  (SNDR),  and  effective  number  of  bits  (ENOB), is evaluated by stimulation using the input signal of a sinusoidal waveform and analysis  signal-to-noise ratio, signal-to-noise and distortion ratio (SNDR), and effective number of bits (ENOB), using a digital signal processor [10]. Therefore, a high‐accuracy DAC controlled by a digital code in  (ENOB), is evaluated by stimulation using the input signal of a sinusoidal waveform and analysis  using a digital signal processor [10]. Therefore, a high‐accuracy DAC controlled by a digital code in  is evaluated by stimulation using the input signal of a sinusoidal waveform analysis usingthe  a digital the  Arduino  board  is  used  to  implement  the  sinusoidal  testing  signal. and Figure  8  shows  basic  using a digital signal processor [10]. Therefore, a high‐accuracy DAC controlled by a digital code in  the  Arduino  board  is  used  to  implement  the  sinusoidal  testing  signal.  Figure  8  shows  the  basic  signal processor [10].generator.  Therefore,A a gain  high-accuracy controlled byemployed  a digital code in thethe  Arduino block  of  the  signal  stage  and DAC a  level  shift  are  to  adjust  signal  the  Arduino  board generator.  is  used  to A  implement  the  sinusoidal  testing  signal.  Figure  shows  the  basic  block  of  signal  gain  stage  and  a  level Figure shift  are  employed  to 8 adjust  the  board is the  used to the  implement the sinusoidal signal. shows basic of thesignal  signal amplitude  and  required  DC  level.  In testing addition,  a  low‐pass 8 filter  is the used  to block reduce  the  noise,  block  of  the  signal  generator.  A level.  gain  In  stage  and  a a  level  shift  are  employed  to reduce  adjust  the  the noise,  signal  amplitude  and  the  required  DC  addition,  low‐pass  filter  is  used  to  generator. A gain stage and a level shift are employed to adjust the signal amplitude and the required eliminate the error, and enhance the signal performance. Figure 9 shows the experimental results,  amplitude  and  the  required  DC  level.  In  addition,  a  low‐pass  filter  is  used  to  reduce  the  noise,  eliminate the error, and enhance the signal performance. Figure 9 shows the experimental results,  DC level. In addition, a low-pass filter is used to reduce the noise, eliminate the error, and enhance the which reveal that this signal generator has a spurious dynamic range (SFDR) of 52 dB.  eliminate the error, and enhance the signal performance. Figure 9 shows the experimental results,  which reveal that this signal generator has a spurious dynamic range (SFDR) of 52 dB.  signalThe clock signal is required to control the ADC for most of the ADC testing platform. Figure 10  performance. Figure 9 shows the experimental results, which reveal that this signal generator which reveal that this signal generator has a spurious dynamic range (SFDR) of 52 dB.  The clock signal is required to control the ADC for most of the ADC testing platform. Figure 10  has a spurious dynamic range (SFDR) of 52 dB. shows the experimental results of the clock signal, and the root mean square of the jitter is 0.808 ns.  The clock signal is required to control the ADC for most of the ADC testing platform. Figure 10  shows the experimental results of the clock signal, and the root mean square of the jitter is 0.808 ns.  shows the experimental results of the clock signal, and the root mean square of the jitter is 0.808 ns. 

    Figure 8. Block diagram of the sinusoidal signal generator.    Figure 8. Block diagram of the sinusoidal signal generator. Figure 8. Block diagram of the sinusoidal signal generator.  Figure 8. Block diagram of the sinusoidal signal generator. 

 

  (b)  (a)  (b)     (a)  (b)   Figure  9. (a)  Output  signal  waveform  of  the  signal  generator.  (b)  Output  power  spectrum  of  the  (a)     

Figure  9. (a)  Figure 9. (a)Output  Outputsignal  signalwaveform  waveformof ofthe  thesignal  signalgenerator.  generator.(b)  (b)Output  Outputpower  powerspectrum  spectrumof ofthe  the signal generator.  Figure  9. (a)  Output  signal  waveform  of  the  signal  generator.  (b)  Output  power  spectrum  of  the  signal generator.  signal generator. signal generator. 

 

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The clock signal is required to control the ADC for most of the ADC testing platform. Figure 10 Figure 10. Output signal waveform of the clock generator.  shows the experimental results of the clock signal, and the root mean square of the jitter is 0.8088 of 13  ns. Appl. Sci. 2016, 6, 217 

2.5. RDFT Design  Figure  11  shows  an  RDFT  processor  structure  used  to  efficiently  compute  the  desired  power  spectrum density of the signals, including fundamental and third harmonic tones [11]. According to  Reference  [11],  we  found  that  the  z‐transform  formula  of  the  N‐point  RDFT  computation  can  be  defined as follows: 

WNk  z 1 H z   ,  1  2 cos 2k  z 1  z  2 N





(10)

The  coefficients  of  cos(θk)  and  2cos(θk)  can  be  shared  to  reduce  the  multiplication  of  cos(θk)  using the same computation; hence, Equation (4) can be written as follows: 

  1 j sin θ  cos θ  z       k Figure 10. Output signal waveform of the clock generator.  Figure 10.HOutput of thekclock generator. ,   z   signal waveform 1 1  z  2 cos  θ k   z 1 

(11)

2.5. RDFT Design  2.5. RDFT Design In  the  11  targeted  the  RDFT  processor  method  would  have  a power  better  Figure  shows application,  an  RDFT RDFT  processor processor  structure  used calibration  to  efficiently efficiently  compute  the  desired desired  Figure 11 shows an structure used to compute the power performance  than  the  FFT  processor  because  only  two  frequency  bins  (i.e.,  the  main  and  third  spectrum density of the signals, including fundamental and third harmonic tones [11]. According to  spectrum density of the signals, including fundamental and third harmonic tones [11]. According harmonic tones) should be calculated. Therefore, the computational complexity can be lower than  Reference  [11],  we  found  be  to Reference [11], we foundthat  thatthe  thez‐transform  z-transformformula  formulaof  ofthe  theN‐point  N-point RDFT  RDFT computation  computation can  can be in  the  FFT  processor.  In  this  work,  an  RDFT  processor  is  implemented  in  the  TSMC  0.18  μm  defined as follows:  defined as follows: standard CMOS process to execute the calibration under the transform length of 4096 and the world  k ´ z ´1 WN k pzq “computational  ,  z ´1 1 ´2 includes  W length  of  24  bits.  Moreover, Hthe  complexity  a  total  of  (2N  + (10) 2)  2πk{N 1 ´ 2cos p N q ˆz `z H z   ,  (10)  1  2 multiplications and (4N + 2) additions.  2k



1  2 cos

N

 z

z

The  coefficients  of  cos(θk)  and  2cos(θk)  can  be  shared  to  reduce  the  multiplication  of  cos(θk)  using the same computation; hence, Equation (4) can be written as follows: 

H z 

j sin  θ k    cos  θ k   z 1  1  z 1  2 cos  θ k   z 1 

, 

(11)

In  the  targeted  application,  the  RDFT  processor  calibration  method  would  have  a  better    performance  than  the  FFT  processor  because  only  two  frequency  bins  (i.e.,  the  main  and  third  Figure 11. The recursive discrete Fourier transform (RDFT) structure.  Figure 11. The recursive discrete Fourier transform (RDFT) structure. harmonic tones) should be calculated. Therefore, the computational complexity can be lower than  in  the  FFT  processor.  In  this  work,  an  RDFT  processor  is  implemented  in  the  TSMC  0.18  μm  2.6. Processing Flow of the Proposed Self‐Testing Platform  standard CMOS process to execute the calibration under the transform length of 4096 and the world  The coefficients of cos(θk ) and 2cos(θk ) can be shared to reduce the multiplication of cos(θk ) using length  of  24  Moreover,  the  computational  complexity  includes  a  total  of  (2N to  + the  2)  the same computation; hence, Equation (4) can written as follows: Figure  12  bits.  shows  the  processing  flow  of be the  self‐testing  platform  method.  According  multiplications and (4N + 2) additions.  block diagram, it starts from a sine wave generator with a frequency condition setting, and then a  ` ˘ jsin pθk q ` cos pθk q ´ z´1 12 bit DAC output signal is fed into the target SAR ADC. Next, the RDFT processor is used to detect  ` ˘ , H pzq “ (11) ´1 1 ´calibration  z´1 2cos pθformula  kq ´ z the  third  harmonic  tone  and  the  proposed  is  employed  to  calculate  the  error  In the targeted application, the RDFT processor calibration method would have a better performance than the FFT processor because only two frequency bins (i.e., the main and third harmonic tones) should be calculated. Therefore, the computational complexity can be lower than in the FFT processor. In this work, an RDFT processor is implemented in the TSMC 0.18 µm standard CMOS process to execute the calibration under the transform length of 4096 and the world length of 24 bits. Moreover, the computational complexity includes a total of (2N +  2) multiplications and (4N + 2) additions. Figure 11. The recursive discrete Fourier transform (RDFT) structure. 

2.6. Processing Flow of the Proposed Self‐Testing Platform  Figure  12  shows  the  processing  flow  of  the  self‐testing  platform  method.  According  to  the  block diagram, it starts from a sine wave generator with a frequency condition setting, and then a  12 bit DAC output signal is fed into the target SAR ADC. Next, the RDFT processor is used to detect  the  third  harmonic  tone  and  the  proposed  calibration  formula  is  employed  to  calculate  the  error 

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2.6. Processing Flow of the Proposed Self-Testing Platform Figure 12 shows the processing flow of the self-testing platform method. According to the block diagram, it starts from a sine wave generator with a frequency condition setting, and then a 12 bit Appl. Sci. 2016, 6, 217  9 of 13  Appl. Sci. 2016, 6, 217  9 of 13  DAC output signal is fed into the target SAR ADC. Next, the RDFT processor is used to detect the third harmonic tone and thethis  proposed calibration formula isfor  employed calculate the error factor. factor.  Finally,  we  can  use  error  factor  to  compensate  the  ADC toerror  using  the  re‐coding  Finally, we can use this error factor to compensate for the ADC error using the re-coding method. method. 

  Figure 12. The processing flow of the proposed self‐testing platform.  Figure 12. The processing flow of the proposed self‐testing platform.  Figure 12. The processing flow of the proposed self-testing platform.

2.7. Proposed Platform Design  2.7. Proposed Platform Design The  proposed self-testing self‐testing  platform  architecture  is  illustrated  in  Figure  This  platform  The proposed platform architecture is illustrated in Figure 13. This13.  platform includes includes  a  power  board,  clock  generator,  sinusoidal  waveform  generator,  and  testing  chip.  In  the  a power board, clock generator, sinusoidal waveform generator, and testing chip. In the power board power board design, the LM317 device is adopted to provide a stable and high‐performance supply  design, the LM317 device is adopted to provide a stable and high-performance supply voltage for voltage for the testing platform. We can utilize the logic analyzer or the Arduino board to catch the  the testing platform. We can utilize the logic analyzer or the Arduino board to catch the output data. output data. Finally, the MATLAB tool is adopted to analyze the output signal.  Finally, the MATLAB tool is adopted to analyze the output signal.

  Figure 13. The self‐testing platform architecture.  Figure 13. The self‐testing platform architecture.  Figure 13. The self-testing platform architecture.

3. Measurement Results  3. Measurement Results 3.1. Multi‐Mode SAR ADC  3.1. Multi-Mode SAR ADC A  A 12  12 bit  bit multi‐mode  multi-mode SAR  SAR ADC  ADC is  is implemented  implemented in  in the  the 0.18  0.18 μm  µm standard  standard CMOS  CMOS process  process to  to demonstrate the proposed idea. The chip microphotograph is shown in Figure 14, in which the core  demonstrate the proposed idea. The chip microphotograph is shown in Figure 14, in which the circuits  have have an  area  of  1.219  mm  ×  0.938  mm.  Figures  core circuits an area of 1.219 mm ˆ 0.938 mm. Figure15a,b  15a,bshow  showthe  theoutput  output power  power spectrum  spectrum before/after  calibration  under  a  3  kHz  and  1  Vp‐p p‐p  input  signal  with  a  125  kHz  sampling  rate.  The  third harmonic distortions without and with calibration are −65.53 dB and −78.95 dB, respectively.  The SFDR here is 65.39 dB before calibration. The SFDR of 78.80 dB can be achieved after calibration.  However,  the  improvement  in  SNDR  and  ENOB  is  not  that  significant  because  the  SAR  ADC  performances  are  dominated  by  system  noise  and  tones  caused  by  supply  noise  and  cross‐talk, 

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before/after calibration under a 3 kHz and 1 Vp-p input signal with a 125 kHz sampling rate. The third harmonic distortions without and with calibration are ´65.53 dB and ´78.95 dB, respectively. The SFDR here is 65.39 dB before calibration. The SFDR of 78.80 dB can be achieved after calibration. However, the improvement in SNDR and ENOB is not that significant because the SAR ADC performances are dominated by system noise and tones caused by supply noise and cross-talk, which should be overcome by careful layout. Appl. Sci. 2016, 6, 217  10 of 13  Appl. Sci. 2016, 6, 217 

10 of 13 

  Figure 14. Chip micrograph of the multi‐mode SAR ADC.  Output Spectrum of ADC

-20

-20 Power spectral density(dB/FS)

0

-40 -60 -80 -100

0

0 0 -20 -20 Power spectral density(dB/FS) Power spectral density(dB/FS)

-60 -80

  

-100

-120 Figure 14. Chip micrograph of the multi‐mode SAR ADC.  Figure 14. Chip micrograph of the multi-mode SAR ADC. Figure 14. Chip micrograph of the multi‐mode SAR ADC. 

-120 -140

-40

-40 -40 -60 -60

10

20

30 40 50 Output Spectrum of ADC Frequency (kHz) Output Spectrum of ADC

(a) 

-140

70

 

0

0 0 -20 -20

10

20

30 40 50 Frequency (kHz) Output Spectrum of ADC Output Spectrum of ADC

(b) 

60

70

 

Figure 15. Measurements (a) without and (b) with calibration.  -40

3.2. Proposed Self‐Testing Platform  -80 -80

60

Power spectral density(dB/FS) Power spectral density(dB/FS)

Power spectral density(dB/FS)

Output Spectrum of ADC 0

-40

-60 -60 -80 -80

The  12  bit  SAR  ADC  and  RDFT  processor  is  implemented  in  the  0.18  μm  standard  CMOS  -100 -100 -100 -100 process to demonstrate the proposed method. The chip microphotograph is shown in Figure 16, in  -120 -120 -120 -120 which the core area is 1.118 mm × 2.13 mm.  -140 -140 0 10 20 30 40 50 under  60 70 0 10 20 show  30 40 50 60 power  70 Figures  17a,b  the  output  spectrum  with -140 and  without  calibration  a 70 1  kHz  -140 0 10 20 Frequency 30 40 50 60 (kHz) 0 10 20 Frequency 30 40 50 60 70 (kHz)   Frequency (kHz)   Frequency (kHz) and 1 Vp‐p input signal with an 18.75 kHz sampling rate. According to the measurement results, the      (b)  (a)  (b)  (a)  third harmonic distortions without and with calibration are −57.23 dB and −74.15 dB, respectively.  Figure 15. Measurements (a) without and (b) with calibration.  The SNDR can be improved from 55.07 dB to 61.35 dB. Figure 18 shows the differential nonlinearity  Figure 15. Measurements (a) without and (b) with calibration.  Figure 15. Measurements (a) without and (b) with calibration. (DNL) and  integral  nonlinearity  (INL)  measurement  results  for  this  work.  The  INL  is  improved  3.2. Proposed Self‐Testing Platform  from +8.3/−7.2 least significant bit (LSB) to +4/−2.9 LSB. This calibration method enhances INL but  3.2. Proposed Self‐Testing Platform  3.2. Proposed Self-Testing Platform not DNL because this method is only adopted using the RDFT processor to evaluate the real radixes,  The  12  bit  SAR  ADC  and  RDFT  processor  is  implemented  in  the  0.18  μm  standard  CMOS  The  12  bit  SAR  ADC  and  RDFT  processor  is  implemented  in  the  0.18  μm  standard  CMOS  and thus the DNL has no significant change. The calibration procedure is also tested with different  The 12 bit SAR ADC and RDFT processor is implemented in the 0.18 µm standard CMOS process process to demonstrate the proposed method. The chip microphotograph is shown in Figure 16, in  process to demonstrate the proposed method. The chip microphotograph is shown in Figure 16, in  testing chips (Figure 19). It is easy to observe that the performance of the ENOB can be enhanced to  to demonstrate the proposed method. The chip microphotograph is shown in Figure 16, in which the which the core area is 1.118 mm × 2.13 mm.  which the core area is 1.118 mm × 2.13 mm.  about 1 bit for different testing chips.  core area is 1.118 mm ˆ 2.13 Figures  17a,b  show  the mm. output  power  spectrum  with  and  without  calibration  under  a  1  kHz  Figures  17a,b  show  the  output  power  spectrum  with  and  without  calibration  under  a  1  kHz  and 1 Vp‐p input signal with an 18.75 kHz sampling rate. According to the measurement results, the  and 1 Vp‐p input signal with an 18.75 kHz sampling rate. According to the measurement results, the  third harmonic distortions without and with calibration are −57.23 dB and −74.15 dB, respectively.  third harmonic distortions without and with calibration are −57.23 dB and −74.15 dB, respectively.  The SNDR can be improved from 55.07 dB to 61.35 dB. Figure 18 shows the differential nonlinearity  The SNDR can be improved from 55.07 dB to 61.35 dB. Figure 18 shows the differential nonlinearity  (DNL) and  integral  nonlinearity  (INL)  measurement  results  for  this  work.  The  INL  is  improved  (DNL) and  integral  nonlinearity  (INL)  measurement  results  for  this  work.  The  INL  is  improved  from +8.3/−7.2 least significant bit (LSB) to +4/−2.9 LSB. This calibration method enhances INL but  from +8.3/−7.2 least significant bit (LSB) to +4/−2.9 LSB. This calibration method enhances INL but  not DNL because this method is only adopted using the RDFT processor to evaluate the real radixes,  not DNL because this method is only adopted using the RDFT processor to evaluate the real radixes,  and thus the DNL has no significant change. The calibration procedure is also tested with different  and thus the DNL has no significant change. The calibration procedure is also tested with different  testing chips (Figure 19). It is easy to observe that the performance of the ENOB can be enhanced to  testing chips (Figure 19). It is easy to observe that the performance of the ENOB can be enhanced to  about 1 bit for different testing chips.  about 1 bit for different testing chips. 

 

Figure 16. Chip micrograph of SAR ADC and RDFT.  Figure 16. Chip micrograph of SAR ADC and RDFT.  

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Figure 17a,b show the output power spectrum with and without calibration under a 1 kHz and 1 Vp-p input signal with an 18.75 kHz sampling rate. According to the measurement results, the third harmonic distortions without and with calibration are ´57.23 dB and ´74.15 dB, respectively. The SNDR can be improved from 55.07 dB to 61.35 dB. Figure 18 shows the differential nonlinearity (DNL) and integral nonlinearity (INL) measurement results for this work. The INL is improved from +8.3/´7.2 least significant bit (LSB) to +4/´2.9 LSB. This calibration method enhances INL but not DNL because this method is only adopted using the RDFT processor to evaluate the real radixes, and thus the DNL has no significant change. The calibration procedure is also tested with different testing chips (Figure 19). It is easy to observe that the performance of the ENOB can be enhanced to Appl. Sci. 2016, 6, 217  11 of 13  about 1 bit for different testing chips. Appl. Sci. 2016, 6, 217  11 of 13 

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(b)  (a)     (b)  (a)  (b)  (a)  Figure 17. Measured output power spectra (a) without and (b) with calibration. 

  

 

Figure 17. Measured output power spectra (a) without and (b) with calibration.  Figure 17. Measured output power spectra (a) without and (b) with calibration. Figure 17. Measured output power spectra (a) without and (b) with calibration.  3

DNL = +2.8 / -1 LSB,

DNL = +2.8 / -1 LSB, DNL = +2.8 / -1 LSB,

32 3 21 2 10 1 0-1 500 1000 1500 2000 2500 3000 3500 4000 0 0 -1 code -1 0 500 1000 1500 2000 3000 3500 4000 INL =2000 +8.3 /2500 -7.2 LSB 0 500 1000 1500 code 2500 3000 3500 4000 10 code INL = +8.3 / -7.2 LSB 10 5 INL = +8.3 / -7.2 LSB 10 50 5 0-5 0 -10 -5 500 1000 1500 2000 2500 3000 3500 4000 -5 0 -10 code -10 0 500 1000 1500 2000 2500 3000 3500 4000 0 500 1000 1500 2000 code 2500 3000 3500 4000

  

(a)  code

(a)  (a) 

 

(b)  (b)  (b) 

  

 

Figure 18. Measured differential nonlinearity (DNL) / integral nonlinearity (INL) (a) without and (b)  Figure 18. Measured differential nonlinearity (DNL) / integral nonlinearity (INL) (a) without and Figure 18. Measured differential nonlinearity (DNL) / integral nonlinearity (INL) (a) without and (b)  with calibration.  Figure 18. Measured differential nonlinearity (DNL) / integral nonlinearity (INL) (a) without and (b)  (b) with calibration. with calibration.  with calibration.  10.0

Without Cal. With Cal. Without Cal. Without With Cal.Cal. With Cal.

ENOB (bit) ENOB (bit) ENOB (bit)

10.0 9.8 10.0 9.8 9.6 9.8 9.6 9.4 9.6 9.4 9.2 9.4 9.2 9.0 9.2 9.0 8.8 9.0 8.8 8.6 8.8 8.6 8.6

1 1 1

2 2 2

3 Chip number 3 4 3 4 Chip number Chip number

4

5 5 5

 

 

Figure 19. Measured performance of ENOB with different testing chips.   Figure 19. Measured performance of ENOB with different testing chips.  Figure 19. Measured performance of ENOB with different testing chips.  Figure 19. Measured performance of ENOB with different testing chips. 

Table  1  compares  the  proposed  method  and  other  state‐of‐the‐art  ADCs.  Although  the  Table  1  compares  the  proposed  method  and  other  state‐of‐the‐art  ADCs.  Although  the  proposed  does the  not  proposed  have  a  better  performance  than state‐of‐the‐art  that  in  Reference  [12], Although  it  still  exhibits  Table  method  1  compares  method  and  other  ADCs.  the  proposed  method  does  not  have  a  better  performance  than  that  in  Reference  [12],  it  still  exhibits  better  power  consumption  and  area  performance  improvement.  In that  addition,  the  performance  of  the  proposed  method  does  not  have  a  better  than  in  Reference  [12],  it  still  exhibits  better  power  consumption  and  area  improvement.  In  addition,  the  performance  of  the  split‐capacitive digital‐to‐analog converter (CDAC) method with 0.9 bit improvement is not as good  better  power  consumption  and  area  improvement.  In  addition,  the  performance  of  the  split‐capacitive digital‐to‐analog converter (CDAC) method with 0.9 bit improvement is not as good  as that of our proposed method.  split‐capacitive digital‐to‐analog converter (CDAC) method with 0.9 bit improvement is not as good  as that of our proposed method. 

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Table 1 compares the proposed method and other state-of-the-art ADCs. Although the proposed method does not have a better performance than that in Reference [12], it still exhibits better power consumption and area improvement. In addition, the performance of the split-capacitive digital-to-analog converter (CDAC) method with 0.9 bit improvement is not as good as that of our proposed method. Table 1. Comparison of Analog-to-Digital Converters (ADCs) with different calibration methods.

Technology Method Supply voltage Resolution Sampling rate SNDR (dB) (Wo/Wi) ENOB (bit) (Wo/Wi) Power (analog) Area

JSSCC'12 [13]

TCASI,13 [14]

TVLSI,15 [12]

This work

0.18 µm Dither 3.3 V (analog) 1.8 V (digital) 10 bit 768 kS/s 49.7/60.9 7.96/9.83 58 µW 10.6 mm2

0.13 µm Split-CDAC

0.6 µm CDAC

0.18 µm RDFT 3.3 V (digital) 1.8 V (analog) 12 bit 18.75 kS/s 55.0/61.35 8.88/9.89 41.5 µW 2.38 mm2

0.5 V

15 V

11 bit 10 kS/s 56.5/61.6 9.09/9.93 0.56 µW 0.58 mm2

14 bit 400 kS/s 61.2/73.3 9.88/11.9 90 mW 9.76 mm2 (only ADC)

4. Conclusion and Discussion In this paper, a self-testing platform with a digital calibration method for SAR ADC is presented to overcome the non-linearity error of the T/H circuit, the capacitor mismatch of the DAC capacitor array, and the DC offset of the comparator. The proposed platform has the advantages of low cost and high integration without requiring extra analogue circuits or a complex digital calibration algorithm. The testing chip is implemented in the 0.18 µm standard CMOS process. The background signal is analyzed by the MATLAB tool to demonstrate the calibration algorithm and measured performance. According to the measurement results, the ENOB can be improved by 1 bit. Acknowledgments: The authors would like to thank the Chip Implementation Center of Taiwan and the Ministry of Science and Technology (MOST) of Taiwan under Grants MOST 104-2218-E-006-022 for their support in this study, as well as the CBIC Lab, APSIC Lab, and Hui-Wen Chang in the CWMI Lab. Author Contributions: Yi-Hsiang Juan, Hong-Yi Huang, Shuenn-Yuh Lee and Ching-Hsing Luo conceived and designed the analog circuit, the proposed calibration method, and the experiments. Shin-Chi Lai and Wen-Ho Juang provided the digital circuit design and analyzed the data. Yi-Hsing Juan and Shuenn-Yun Lee wrote the paper. Conflicts of Interest: The authors declare no conflict of interest.

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