A Simple Implementation of Determinant Decision Diagram Guoyong Shi School of Microelectronics Shanghai Jiao Tong University Shanghai, 200240, China e-mail:
[email protected] different DDD implementations can make drastic performance difference at runtime. The key factors that must be considered in implementation include: 1) the design of hashing, which is the key for sharing; 2) the design of symbol ordering, which is critical for runtime and memory consumption; and 3) the implementation methodology such as whether or not to use an off-the-shelf BDD package. The implementation proposed in the original DDD work [2] is roughly the following.
Abstract—Determinant decision diagram (DDD) uses a Binary Decision Diagram (BDD) to represent the Laplace expansion of a determinant. It is used as the core computation engine in some modern symbolic circuit simulators. The traditional implementations rely on a BDD package for the common-data sharing operations in which symbol ordering plays an essential role. This paper proposes a simple implementation method which does not use any BDD package. Sharing is implemented by directly hashing minors, while the requirement on symbol ordering is weakened to an expansion ordering. The basic mechanism used is a natural formulation of layered expansion which is analogous to manual expansion of a determinant, hence it is easily understood. The simplified DDD construction method not only makes the DDD implementation straightforward, but also results in greater efficiency. A simulator developed based on this new method solves the μa725 op-amp circuit in a few seconds by flat expansion.
Traditional DDD Construction Flow: Step 1. Parse a circuit to an MNA (modified nodal analysis) formulation. Step 2. Expand the coefficient determinant using the GreedyLabeling algorithm to assign each matrix element (symbol) an index. Step 3. Expand the determinant in the greedy order again to construct a DDD. Step 4. Determine the vertex signs. Step 5. Run DDD evaluation to do symbolic AC analysis. In Step 2 the Greedy-Labeling algorithm is basically a minimum degree (abbreviated min-degree) ordering scheme, where the algorithm looks at the row and column nonzero counts (called degrees) of each intermediate minor and chooses one row (resp. column, with priority at a tie) of the mindegree. When a min-degree row (resp. column) is selected, the expansion of the selected elements follows the order of the increasing degrees of the columns (resp. rows) that intersect the selected row (resp. column). (See the procedure described in Fig. 6 of [2].) By a depth-first expansion, the symbols are indexed as the recursion returns (see the illustration in Fig. 7 of [2]). In Step 3 of the flow, typically a standard BDD package is used for implementing DDD vertex sharing. Set operation routines implemented in a Zero-suppressed BDD (ZBDD) package [9], such as Change() and Union(), are invoked to enforce the standard vertex-triple sharing implemented in all BDD packages [10]. In Step 4 of the flow, the vertex signs (required for determinant evaluation) are determined by traversing the 1-paths rooted at all vertices (see equation (8) in [2].) The implementation of these key steps largely determines the performance of a DDD simulator. In the recent work of [8], Step 3 of the flow was replaced by a logic synthesis procedure, where the legal product terms of a determinant expansion are exhaustively described by a set of conjunctive and disjunctive logic terms which are synthesized by a logic BDD package
Index Terms—analog integrated circuit, binary decision diagram (BDD), determinant decision diagram (DDD), Laplace expansion, symbolic circuit analysis.
I. I NTRODUCTION Besides numerical circuit simulators such as SPICE [1], there exists another type of circuit simulators that analyze circuits symbolically. The simulation result of a symbolic simulator takes the form of analytical expressions of certain circuit behavior, which can help the designer judge how to modify the circuit structure or parameter without running the simulation repeatedly, while a numerical simulator is hard to do so. After decades of research, numerous symbolic analysis techniques proposed in the literature could not efficiently deal with the problem of exponential complexity growth until the proposal of Determinant Decision Diagram (DDD) [2]. DDD applies the technique of Binary Decision Diagram (BDD) [3] for determinant expansion, in which identical sub-determinants (minors) are shared. The common-data sharing mechanism essentially transforms an explicit enumeration problem into implicit enumeration, which greatly improves the scale of problems to be solved. Since its proposal, a variety of applications of DDD for circuit analysis have been published [4], [5], [6], [7], [8]. Although DDD is a much more efficient algorithm, it still encounters bottleneck when applied to larger analog circuits containing more than 20 transistors. Since DDD is essentially a BDD, its construction complexity largely depends on a prechosen symbol order [3]. Even with a good symbol order, This research was supported by the National Natural Science Foundation of China (Grant No. 60876089).
978-1-4244-8192-7/10/$26.00 ©2010 IEEE
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to construct a DDD. Except for Step 3 of the flow being substituted by the new technique, the other steps (such as symbol ordering and sign determination) remain unchanged. This paper completely changes such a traditional implementation flow by introducing new mechanisms for expansion and hashing. The new mechanism for expansion always expands a whole selected row (or column) whenever a reduced minor is to be expanded. The row/column selection is made on-thefly. Hence, a pre-phase for symbol ordering (Step 2 of the traditional flow) is not required. In addition, preserving the minor information can help determine the DDD vertex signs during construction. Hence, Step 4 of the traditional flow also becomes unnecessary. On the other hand, the new hash mechanism uses only the row and column indexes of a minor (called minor indexes) for hashing. Consequently, only a Minor Hash Table is sufficient for realizing sharing; any kernel BDD package is not needed in implementation. The two new strategies stated above can greatly simplify the DDD implementation while significantly improve the runtime efficiency. A layered determinant expansion procedure described in Section II is used to create a directed graph (digraph), from which a signed DDD can be constructed by directly modifying the digraph. Section III discusses the implementation details. Experimental results are reported in section IV, where it is demonstrated that the simplified DDD implementation outperforms the traditional implementation in multiple tests. Section V concludes the paper.
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(a) The LED of the 3 × 3 full matrix. (b) The corresponding DDD.
Then we work with the second element ‘b’ in the first queue analogously to element ‘a’. Delete from minor A the row and column where ‘b’ lies, resulting in another reduced minor d f . (3) Mb = g i
II. L AYERED E XPANSION OF D ETERMINANT We use an example to illustrate the layered expansion of determinant. Meanwhile, we state some properties possessed by a Layered Expansion Diagram (LED). The LED-based DDD construction is divided into two phases: an LED construction phase and a conversion phase that converts an LED to a DDD. Let us expand a 3 × 3 determinant a b c (1) A = d e f g h i
Then enqueue the first row elements {d, f} of the reduced minor Mb to the next queue, following the previously enqueued elements. After that, we work with the last element ‘c’ in the first queue as before, repeat the minor reduction and enqueue elements {d, e} to the next queue. After the elements in the first queue are all expanded, the second queue has been filled with the elements coming from the selected rows (columns) of the minors reduced by one-dimension. Then we move on to expand the elements in the second queue as we just did it to the first queue. Scan the elements from the queue head toward the queue tail, expand the associated minor, and enqueue the elements of the subsequently selected row or column to the queue in the nextlayer. Repeat this process until the last queue at the bottom is filled with 1 × 1 minors (Fig. 1(a)). Some special book-keeping tasks are necessary during LED construction. When a minor is expanded with respect to an element in the minor, one row (or column) is subsequently selected from the reduced minor. (A heuristic for specifying the selection of a row (or column) will be discussed in the section on experiments.) The elements in the selected row (or column) are enqueued in the succeeding queue. Therefore, it is a natural consequence of the LED construction that the elements from a selected row (or column) form a sibling group which shares the minor these elements come from. For example, the first two elements {e, f } in the second queue in Fig. 1(a) are from the first row of the minor Ma given in (2) after expanding element ‘a’. A sibling group is managed
to product terms by taking a rowwise expansion order. Whenever a reduced minor is obtained, the same procedure is repeated, until the final minor size becomes 1×1 (a scalar). We shall use a directed graph shown in Fig. 1(a) to book-keep the expansion process and call the digraph a Layered Expansion Diagram (LED). The expansion diagram (Fig. 1(a)) is constructed as follows. Each row (or layer) in Fig. 1(a) is implemented as a queue. Enqueue the first determinant row {a, b, c} to the first (top) queue. Then rewind to the queue head and start expanding the determinant for each element in the queue. For element ‘a’, delete from minor A the row and column where ‘a’ lies, resulting in a reduced minor e f . Ma = (2) h i This minor will further be expanded by its first row {e, f}. Hence, enqueue the elements {e, f} to the next queue, which is the second queue from top in Fig. 1(a).
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in implementation by maintaining a next-layer pointer which points from the expansion element to the leading element of the group. Following this rule, we see an solid arrow connects element ‘a’ to ‘e’ in Fig. 1(a), where element ‘e’ is the leading element (called the group leader) of the group {e, f } resulting from the expansion element ‘a’. Since the sibling groups and the number of elements in each group are known at the time of expansion, the groups in any queue can be managed by assigning the number of elements of each group to the leading element of that group. However, as an exception, the leading element in the top queue (as a single group) is not pointed by any arrow. The above discussion leads to the first property of LED. Property 1: The elements in the same sibling group in any LED queue share the same minor. For example, the elements {a, b, c} are in the same group at the top layer (Fig. 1(a)). They share the same minor, denoted by M {(1, 2, 3); (1, 2, 3)}, where the first tuple (1, 2, 3) lists the row indexes and the second tuple (1, 2, 3) lists the column indexes. In implementation, it suffices to preserve only one minor for all elements in one sibling group. The minor row and column indexes are saved in a hash table, called the Minor Hash Table. Whenever a minor is looked up from the hash table, re-expansion of the minor is not necessary. Again in Fig. 1(a), the first and third elements ‘e’ and ‘d’ in the second queue both point to the same element ‘i’ in the last queue, which means that the minor associated to element ‘i’ is shared. The second LED property is now evident from the discussion above. Property 2: The minors associated with the elements at the same level of an LED are of equal size. The minor size successively decrements from top down. For an n × n determinant, there are n queues (layers) in an LED in general. Although sharing has been enforced in the LED construction, an LED as constructed above is not a DDD yet. We would like to convert an LED to a BDD so that some of the standard operations available in BDD, such as traversal, evaluation, and the derivative operation, etc., can be applied for the tasks in symbolic circuit analysis. A key feature of BDD is the problem-dependent definition of a binary decision. For determinant expansion, the binary decisions are the Minor operation and the Remainder operation defined in [2]. A Minor operation is an operation of selecting an element and eliminating the row and column intersecting at the element, which has been discussed above. However, the Remainder operation has not been explicitly mentioned in our discussion yet. In fact, the element sibling groups mentioned earlier are pertinent to the Remainder operations, which is manifested in the second phase of LED-based DDD construction: Converting an LED to a DDD. The conversion from an LED to a DDD is fairly straightforward. All the existing arrows (i.e., the next-layer pointers) in an LED become the 1-arrows (also called solid-arrows or truearrows) in DDD. In addition, add 0-arrows (also called dashed arrows or false-arrows) successively between the elements in each sibling group. Terminate the last element of each group by a 0-arrow at the vertex zero. Finally, terminate all the elements in the bottom queue by 1-arrows at the vertex one.
After adding all the necessary BDD pointers, we end up with a fully linked standard DDD, with the DDD root being the first element in the top queue. To this end, the DDD construction process is completed. A direct consequence of the conversion process described above leads to the third property of LED. Property 3: The total number of elements in all queues in a LED (counting the elements of repeated names) is equal to the number of DDD vertices, which is the size of DDD, denoted by |DDD|, excluding the terminal vertices one and zero. III. I MPLEMENTATION D ETAILS The LED construction procedure described above greatly simplifies the DDD construction. In particular, this procedure has the following advantages. Advantages of LED: (i) It does not need an explicit symbol order; (ii) It does not rely on any BDD package; and (iii) It does not need an extra phase to determine the vertex signs. The two key strategies that contribute most to the improvements are: 1) reducing the requirement of a full symbol order to a requirement of a row/column expansion order, and 2) replacing the vertex-triple based sharing by direct minor index based sharing. The details are explained in the sequel and at the end of this section the LED construction procedure is summarized. A. Expansion Order The canonicity of BDD requires that the symbols be fully ordered [3]. The canonicity is emphasized analogously in the original DDD work as well [2]. With a fully ordered DDD, the symbols in all 1-paths of a DDD from the root to terminal one comply with the pre-specified order. While the BDD canonicity is important for the purpose of logic representation, its importance in DDD is not as imperative because the main purpose of DDD is for symbolic computation. During the construction of LED, a row or column is selected from a minor by certain heuristic, for which a symbol order is not required. Moreover, as long as one row (resp. column) is selected, it is actually immaterial in which order the in-row (resp. in-column) elements are expanded, as stated in the next property. Property 4: The order of elements inside any sibling group in any queue is immaterial in that any order of sibling elements do not change the LED or DDD size. This fact can be shown easily by looking at the LED given in Fig. 1(a). Shuffling those sibling elements would only change the positions of elements in their own queue and their offspring elements in their respective queues, but not the pointers linking the elements between the queues. By an expansion order we refer to the order in which the rows and columns are chosen for expansion as performed during the LED construction. By Property 4, it is convenient to expand the sibling elements in their natural order in their respective row or column. A heuristic of determining the
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expansion order by the row/column degrees is tested in Section IV on experiments. The notion of expansion order is obviously much weaker than the notion of full-order, as illustrates by the following example. Since different minors may be expanded in their own row (column) order, the 1-paths (representing a product terms) in the converted DDD might not necessarily follow a fixed symbol order. For example, this determinant a 0 0 b 0 e f 0 (4) 0 g h 0 c 0 0 d
one row and one column, the new row/column indexes and the new row/column degrees of the reduced minor can easily be derived from the parent minor. For example, suppose that the 4 × 4 minor 0 a b 0 c d 0 e (5) 0 0 f g h 0 0 i is a minor with indexes M {(2, 4, 6, 8); (1, 3, 5, 7)}, respectively. Its row and column degrees are respectively (2, 3, 2, 2) and (2, 2, 2, 3). Let ‘a’ be selected for expansion. After deleting the first row and the second column of this minor, the resulting minor indexes are M {(4, 6, 8); (1, 5, 7)}, and the new degrees are (2, 2, 2) and (2, 1, 3), which represents the reduced minor c 0 e 0 f g . (6) h 0 i
can be expanded in an LED shown in Fig. 2. We see that the two symbols ‘e’ and ‘h’ on the two paths a-e-h-d and c-h-e-b are in opposite order. But clearly, it does not affect the purpose for symbolic term representation and evaluation. a
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Maintaining the minor indexes in the Minor Hash Table also greatly simplifies the vertex sign determination. For example, the sign of element ‘a’ in the minor given in (5) is determined simply by its row and column positions relative to its underlying minor, which is (−1)1+2 . Hence, all the DDD vertex signs have been fixed by the time a DDD is constructed, which makes the extra sign determination step (Step 4 of the traditional flow) unnecessary. We point out that saving the row/column degrees with a minor object also simplifies the identification of a singular minor. A minor with one row (or column) degree zero is considered singular. A singular minor is not expanded anymore and the element who generates a singular minor is terminated at NULL by its next-layer pointer. When a LED is converted to a DDD, such a NULL pointer is substituted by a solid arrow terminated at the zero vertex. All such zero-terminated vertices (by a solid arrow) are zero-suppressed later.
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B. Minor Hash Table In LED construction, the minors are expanded by row or by column, whose order could be determined by a heuristic based on the min-degree. As a consequence of this treatment, the Remainder operation defined [2] becomes implicit in LED. That is, there is no need to explicitly place a zero in a minor after a Remainder operation is applied, because the elements in a selected row or column are expanded successively one after another. This fact brings us a good side effect. When each element in a selected row (or column) (i.e., a sibling group) is expanded, the same minor where the row (or column) comes can be referenced for minor reduction. More specifically, we only need to preserve one unique minor in the Minor Hash Table for all sibling elements. Since the minor contents can be looked up from the original determinant, it is only necessary to save the minor row and column indexes in the hash table. Furthermore, it is only necessary to create a link from a unique minor in the hash table to the associated leading element of a sibling group in implementation. When any unique minor is hashed, the linked leading element is returned for sharing. Suppose we use a row/column degree based heuristic for an expansion order, the row and column degrees of a minor also can be stored with a minor object in the Minor Hash Table. As soon as a reduced minor is obtained by deleting
C. The LED Construction Procedure The LED construction procedure is summarized below: Input: A determinant. Output: A Layered Expansion Diagram (LED). 01 02 03 04 05 06 07 08 09 10 11 12 13
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Create queue Q(0) and enqueue a selected row or column to Q(0); k := 0; While (True), do While (Dequeue element x in Q(k)), do Expand the minor at x; Hash the reduced minor; If (Not hashed) Enqueue elements to Q(k + 1); End of while; If (Q(k + 1) is nonempty) k := k + 1; continue; Else Quit the loop; End of while;
In line 04, if the reduced minor is singular, then the element x is pointed to NULL. In line 07, the enqueued elements are from the row or column selected for the next expansion. A good heuristic for the selection is by the min-degree heuristic. In line 11, if no elements are enqueued in the next queue, it simply implies that the expansion is finished. In case Q(k) is empty at k < n − 1, it means that the original determinant is symbolically singular.
Simulator II was used for obtaining the DDD sizes with the symbols ordered by the Greedy-Labeling algorithm [2]. Both simulators used a minor-based hash table, without using any BDD package. To ease experimentation, both DDD simulators were implemented to be able to run on either matrices or circuits. The correctness of the simulators were verified by the calculated determinant values, the number of terms compared to the known values, and the AC analysis results compared to HSPICE results. The C++ programs were compiled by gcc 3.4.4 coming with the CYGWIN (a Linux emulator) and were run on a Windows XP machine with Intel Duo 2.26GHz CPU and 2GB memory (about 1G is available for application programs.) The first part of performance evaluation was on a set of full matrices, which was done in [8] as well. Such a test is believed to be reflective of the combined performance effects of construction and ordering. The LED simulator (Simulator I) was used to expand a set of full matrices by the natural rowwise order, meanwhile for the purpose of comparison, Simulator II was used to analyze the matrices using the order of Greedy-Labeling. Listed in Table II (next page) are the sizes∗ of the DDDs constructed by Simulator I together with the sizes of the DDDs constructed by Simulator II using the Greedy order. We see the progressively increasing differences between the two sizes; the size by the Greedy order exceeds 30 times over the size by LED for the 18 × 18 full matrix. For a visual comparison, the DDD sizes by LED and by Greedy are plotted in Fig. 3(a), where the Greedy ordering exhibits apparently faster exponential growth. Plotted in Fig. 3(b) are the same curves with the y-axis plotted in the log-scale, from which we see a clear gap between the two growth rates. The recent work by the same author has proven that the rowwise order for full matrices of dimension n is an optimal order for which the optimal DDD size is discovered to be (n · 2n−1 ) [11]. The CPU times of running the LED simulator for the full matrices are summarized in Table III, where those matrices with appreciable runtime are selected. The data is plotted in Fig. 4 in the log-scale of CPU time.
IV. E XPERIMENTAL RESULTS The LED-based DDD construction procedure was implemented and compared to the traditional implementations. To make a fair comparison, two key components that could make great runtime difference should be mentioned; namely, the choice of a DDD construction methodology and the choice of a symbol ordering scheme. On the other hand, two factors regarding the construction methodology directly affect the construction efficiency; namely, a problem formulation and a hash scheme. Two problem formulations exist so far; namely, the expansion-based formulation ([2] and this work) and the logic synthesis formulation [8]. On the other hand, two types of hash mechanism can be used; one by hashing BDD vertex-triples (inherited from a BDD package and used in both [2] and [8]), the other by hashing minors (this work). The work [2] used a minor-based cache, however, its contribution to the overall efficiency is limited. While a good construction methodology can make a great difference in efficiency, a good symbol order can make another great difference in efficiency as well due to the nature of BDDbased problem solving. For this reason, a fair comparison between different implementations should take into account of these critical factors mentioned. Table I categorizes four types of implementation with their corresponding critical components for performance evaluation. TABLE I F OUR TYPES OF DDD IMPLEMENTATION . Order (good) Order (bad)
Construction (good) I III
Construction (bad) II IV
TABLE III CPU TIMES BY LED FOR FULL MATRICES .
For example, the Fig. 4 given in [8] shows a comparison between type-I and type-II on full matrices (without zero element). It tells us that, given the same ordering by GreedyLabeling, the logic synthesis implementation [8] outperforms the expansion-based implementation [2]. The experimental results reported in this section mainly examine the performance of the LED-based implementation achieved by both a new construction method and a new ordering scheme. In this sense, we are making efforts on developing a type-I DDD. Two versions of DDD simulator have been implemented; both are in C++. The first version (named Simulator I) implemented the Layered Expansion Diagram method where no a priori symbol ordering is required. The second version (named Simulator II) implemented a traditional Ordered BDD, where the matrix elements were ordered first before expansion.
Matrix size CPU time (s)
12 0.4
13 0.6
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17 21.0
18 88
The work [8] reported a test result of DDD construction by using logic synthesis with the Greedy ordering. It did not provide the DDD sizes for the full matrices, but provided a plot of runtime (see Fig. 4 in [8]). That plot shows that the runtime reaches 104 seconds for the 16 × 16 full matrix (the largest reported there), while the corresponding runtime for the same full matrix by LED is only 6.9 seconds (see Table III), the runtime difference exceeds 1,000 times, although the DDD size difference for the 16 × 16 full matrix is only about 16 times between LED and Greedy according to Table II. (Note that the machine we used for testing is by no means superior ∗ The
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two terminal vertices one and zero are excluded.
TABLE II C OMPARISON OF THE DDD SIZES CONSTRUCTED BY LED AND Greedy-Labeling FOR FULL MATRICES . Matrix size |DDD| (LED) |DDD| (Greedy) Matrix size |DDD| (LED) |DDD| (Greedy) Matrix size |DDD| (LED) |DDD| (Greedy)
2 4 4 9 2,304 7,535 16 524,288 8,529,668
3 12 13 10 5,120 20,828 17 1,114,112 23,030,492
4 32 40 11 11,264 57,266 18 2,359,296 62,072,002
5 80 118 12 24,576 156,764
6 192 340 13 53,248 427,571
7 448 965 14 114,688 1,162,580
8 1,024 2,708 15 245,760 3,152,681
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in DDD, with which several determinant expansions should be carried out, depending on the number of unknowns to be solved [2]. The simulators developed in this work take the following unified approach. Let xu be the variable for the input and xv be the unknown for the output. Then we have xu = eTu A−1 b and xv = eTv A−1 b, where ek denotes the kth basis vector in the n-dimensional Euclidean space. Let X be the input-output transfer function. Then the input-output relation xv = Xxu is just the expression eTv A−1 b = XeTu A−1 b, which can be written equivalently in a homogeneous determinant T A T b = 0. (7) ev − Xeu 0
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(b) Fig. 3. (a) Comparison of the DDD sizes created by LED and Greedy for full matrices. (b) Replotted with the y-axis in log scale.
With the input-output relation X viewed as a symbol, only one DDD construction for the determinant in (7) is required. The resulting product terms are sorted in the following form
to that used in [8].) Moreover, the CPU times by LED (shown in Fig. 4) has a growth rate much lower than that displayed in Fig. 4 of [8]. It can be concluded that: 1) the Greedy-Labeling order is not suitable for full matrices, and 2) the logic synthesis approach to DDD construction [8] is of limited efficiency. The second part of performance evaluation was done on some representative op-amp circuits that are often used as benchmarks for testing symbolic circuit simulators ([2], [8]). Before presenting the experimental results, we discuss slightly on a minor modification to the solving method so that the Cramer’s rule is not needed. As most circuit simulators do, a symbolic simulator parses a circuit to a linear equation Ax = b, then solves the unknown x = A−1 b analytically. Traditionally, the Cramer’s rule is used
D · (−X) + N = 0,
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where D subsumes all terms multiplied by (−X) and N the rest of terms. The transfer function is determined simply by X = N/D. It is not hard to extend the one-dimensional augmentation (by adding one row and one column) to the case of multiple-input single-output (MISO) networks. In simulator development, the form of matrix in (7) can be established by directly stamping the input-output as a dependent source (the details are omitted.) For all circuit problems reported in this paper, the matrices are formulated in this special form, hence the matrix sizes and the numbers
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TABLE IV C OMPARISON OF CPU TIMES FOR SOLVING THE REPRESENTATIVE OP - AMP CIRCUITS .
Circuit
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CMOS op-amp μa741 μa725
22 (MOS) 20 (BJT) 26 (BJT)
15 × 15 25 × 25 34 × 34
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|DDD| 2,507 13,722 115,590
LED CPU time§ 0.2s 0.6s 5.4s
Greedy‡ |DDD| CPU time§ 1,178 0.5s 19,572 6.6s 38,997 8.1s
# Terms 2.9914e+4 4.203232e+06 1.280604e+08
The MNA matrices are augmented by one dimension. The unknown symbol is ordered first. § Including DDD construction time and AC analysis for ten points. ‡
of symbols should be referred to the form of matrix given in (7). To ease the transfer function derivation, the unknown symbol X is processed first in both simulators in that for the LED construction the row with X is expanded first while for the Greedy ordering the unknown symbol X is removed before passing the MNA matrix to the Greedy-Labeling routine and placed back to the first place preceding all other ordered symbols. The slight modification of the Greedy ordering in Simulator II is named the Greedy to differentiate it from the traditional Greedy ordering where no symbol is treated specially. It is noted that this slight modification to the Greedy ordering could possibly change the DDD sizes drastically. Reported in Table IV are the test results on three typical opamp circuits of different sizes simulated by the two simulators. The LED simulator used the min-degree expansion order; that is, whenever a new minor is generated, its row and column degrees are updated and a row (or column) with the minimum degree is selected for the next expansion (either a row or a column is chosen upon a tie.) The circuit CMOS op-amp has 22 MOS transistors. Its augmented MNA matrix is relatively small, 15 × 15, which was solved quickly by both LED and Greedy simulators. The two simulators also solved the other two bipolar opamp circuits, μa741 (containing 20 bipolar transistors) and μa725 (containing 26 bipolar transistors), in a few seconds. It is worth noting that, for the μa741 op-amp, the LED simulator (Simulator I) constructed a smaller DDD than that by Simulator II (with the Greedy order), while, for the μa725 op-amp, the LED simulator constructed a larger DDD than that by Simulator II. However, for the μa725 op-amp, although the DDD size by Simulator I is much larger, its runtime is actually less than that by Simulator II. It simply tells us that the LED based DDD construction is really very fast. So far, the only published work that solved the μa725 op-amp exactly was by a hierarchical method [7]. Finally, we simply mention that the LED simulator performed efficiently over a set of RC(L) networks, including ladder circuits, tree circuits, and mesh circuits etc. of scales comparable to those reported in [8]. Since such passive circuits usually have massive scales in practice and are challenging for full-scale symbolic analysis, an experimental report on smallscale passive circuits is omitted. A symbolic moment approach to large-scale RCL networks has been addressed in the recent work [12].
V. C ONCLUSION A simple yet efficient implementation of Determinant Decision Diagram is presented. While the art of symbolic circuit analysis is full of potential applications for analog integrated circuit design, wide deployment of such tools in design practice has not become reality. Promotion of the art of symbolic analysis for analog design automation calls for more researchers to participate in this field. The original DDD implementation requires sophisticated expertise on the art of Binary Decision Diagram, which might have shied away some potential researchers. It is hoped that a simple DDD implementation as developed in this work has demystified DDD. More advanced research on promoting this appealing technology is expected in the near future. R EFERENCES [1] L. W. Nagel, “SPICE2: A computer program to simulate semicoductor circuits,” Ph.D. dissertation, University of California, Berkeley, CA, May 1975. [2] C. J. R. Shi and X. D. Tan, “Canonical symbolic analysis of large analog circuits with determinant decision diagrams,” IEEE Trans. on ComputerAided Design of Integrated Circuits and Systems, vol. 19, no. 1, pp. 1–18, January 2000. [3] R. E. Bryant, “Graph-based algorithms for boolean function manipulation,” IEEE Trans. on Computers, vol. C-35, no. 8, pp. 677–691, 1986. [4] X. D. Tan and C. J. R. Shi, “Hierarchical symbolic analysis of analog integrated circuits via determinant decision diagrams,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 19, no. 4, pp. 401–412, April 2000. [5] W. Verhaegen and G. E. Gielen, “Efficient DDD-based symbolic analysis of linear analog circuits,” IEEE Trans. on Circuits and Systems – II: Analog and Digital Signal Processing, vol. 49, no. 7, pp. 474–487, 2002. [6] S. X. D. Tan and C. J. R. Shi, “Efficient approximation of symbolic expressions for analog behavioral modeling and analysis,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 23, no. 6, pp. 907–918, June 2004. [7] S. X. D. Tan, W. Guo, and Z. Qi, “Hierarchical approach to exact symbolic analysis of large analog circuits,” in Proc. Design Automation Conference, 2004, pp. 860–863. [8] S. X. D. Tan, “Symbolic analysis of analog integrated circuits by boolean logic operations,” IEEE Trans. on Circuits and Systems - II: Express Briefs, vol. 53, no. 11, pp. 1313–1317, Nov. 2006. [9] S. Minato, “Zero-suppressed BDD’s for set manipulation in combinatorial problems,” in Proc. 30th IEEE/ACM Design Automation Conf., Dallas, TX, 1993, pp. 272–277. [10] K. S. Brace, R. L. Rudell, and R. E. Bryant, “Efficient implementation of a BDD package,” in Proc. 27th ACM/IEEE Design Automation Conference, Orlando, FL, 1990, pp. 40–45. [11] G. Shi, “A computational complexity analysis of determinant decision diagram,” IEEE Trans. on Circuits and Systems - II: Express Briefs, 2010, accepted for publication. [12] Z. Hao and G. Shi, “A fast symbolic computation approach to statistical analysis of mesh networks with multiple sources,” in Proc. Asia SouthPacific Design Automation Conference (ASPDAC), Taiwan, China, Jan. 2010, pp. 383–388.
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