A simple subcircuit extension of the BSIM3v3 ... - Semantic Scholar

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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 35, NO. 4, APRIL 2000

A Simple Subcircuit Extension of the BSIM3v3 Model for CMOS RF Design Suet Fong Tin, Ashraf A. Osman, Kartikeya Mayaram, Senior Member, IEEE, and Chenming Hu, Fellow, IEEE

Abstract—An accurate and simple lumped-element extension of the BSIM3v3 MOSFET model for small-signal radio-frequency circuit simulation is proposed and investigated. Detailed comparisons of the small-signal and parameters with both two-dimensional device simulations and measurement data are presented. A procedure is developed to extract the values of two lumped resistors—the only added elements. The non-quasi-static and substrate effects can be modeled with these two resistors to significantly improve the model accuracy up to a frequency of 10 GHz, which is of the 0.5- m NMOS transistor. about 70% of the Index Terms—BSIM3v3 RF model, CMOS RF, lumped-element model, MOSFET RF modeling, parameter extraction, small-signal model. Fig. 1. A gate resistance non-quasi-static operation.

I. INTRODUCTION

T

HE RAPID pace of development in the communication circuits market is driving IC designs to higher levels of integration and circuitry that operates at higher frequencies and low voltages. IC designers rely on circuit simulators and accurate models for design verification before committing a design to silicon; thus model accuracy is a significant concern for radio-frequency (RF) applications [1]. Since CMOS is the preferred technology for integrating systems on a chip, MOSFET models such as BSIM3v3 [2] must provide accurate simulation of CMOS RF circuits. The BSIM3v3 model is an industry standard MOSFET model for deep submicrometer applications and has been sufficiently validated for digital applications at hundreds of megahertz. However, not much attention has been paid to radio-frequency modeling. Recent papers [3]–[6] have started addressing the suitability of BSIM3v3 for RF applications and the development of new MOSFET models and parameter extraction for RF circuit simulation [7]–[10]. At high frequencies the MOSFET behaves as a distributed device. Therefore, the effects that must be modeled are: 1) distributed channel or the non-quasi-static (NQS) effect; 2) distributed gate resistance in wide geometry transistors; 3) distributed substrate resistance. Manuscript received August 13, 1999; revised December 20, 1999. This work was supported in part by the National Science Foundation (NSF) Center for the Design of Analog/Digital Integrated Circuits r and by the National Science Foundation under Grant CCR-9702292. The UTMOST parameter extractor was made available under NSF Grant DUE-651416. S. F. Tin is with Cypress Semiconductor, Woodinville, WA 98072 USA. A. A. Osman is with Level One Communications, Inc., Sacramento, CA 95827 USA. K. Mayaram is with the Department of Electrical and Computer Engineering, Oregon State University, Corvallis, OR 97331 USA. C. Hu is with the Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA 94720 USA. Publisher Item Identifier S 0018-9200(00)02654-8.

R

in series with the MOSFET gate models

This work differs from previous efforts in several ways. First, we examine the minimum circuit-level modifications to BSIM3v3 that are required to improve the accuracy of this model. It is shown that only two lumped resistors need to be added to represent all distributed effects. Previous studies have used up to six additional circuit elements. Second, we have demonstrated good accuracy for small-signal RF circuit simulation for a frequency range up to 70% of the transistor . Third, the model is compared with results from two-dimensional (2-D) physical device simulation, which are accurate for high-frequency applications, and measurement data. Fourth, based on the insight gained from device simulations and the simplicity of the proposed circuit model, a parameter extraction procedure is derived. Although the use of the lumped resistors has been evaluated only for BSIM3v3, the technique is general and simple so that it can be applied to other MOSFET models. This paper is organized in the following manner. In Section II, a brief overview of the previous work in high-frequency MOSFET modeling is described. A new simple and accurate substrate model is presented and analyzed in Section III. The device-simulation based verification methodology is presented in Section IV. Comparisons of the small-signal circuit models with experimental data are presented in Section V. The main conclusions are summarized in Section VI. II. AN OVERVIEW OF RF MOSFET MODELING In this section, MOSFET modeling approaches for high-frequency applications are examined. Most of the approaches for large-signal analysis result in complex models that are available only in special simulators. These techniques cannot be used in the context of a standard model such as BSIM3v3. Simple lumped-element equivalent circuit extensions are desirable since they can be incorporated with any MOSFET model. The

0018–9200/00$10.00 © 2000 IEEE

TIN et al.: SIMPLE SUBCIRCUIT EXTENSION OF BSIM3v3 MODEL

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Fig. 2. Magnitude and phase of y and y as a function of frequency from device simulations for two transistor structures, one for which the substrate effects are important (Sub) and the other for which the substrate effects have been minimized (without Sub). W=L = 500=0:6 and W=L = 500=1:2 at V = 0:8 V and V = 3:0 V.

emphasis here is on small-signal models for the MOSFET at high frequencies. A. NQS Modeling NQS effects are important for high-frequency applications [11] and have been experimentally demonstrated in MOSFET’s by on-wafer -parameter measurements [12]. They have been incorporated in circuit simulators using a solution of the current continuity equation [13]–[22]. Most of these models are extremely complex and valid only for long-channel MOSFET’s. An alternate approach, as suggested in [11] and [23], is to model the distributed nature of the MOSFET by using a lumpedsectional model. Here several MOSFET sections are used to represent the distributed channel. Although the MOSFET model is generally believed to be accurate, the computational cost increases because of an increase in the number of MOSFET’s that have to be evaluated.

In BSIM3v3 the NQS effect is accounted for by a first-order model based on the Elmore delay [24]. When the nonquasistatic model option is selected (NQSMOD ), the ELM parameter controls the value of the Elmore delay. Alternatively, a similar behavior can be introduced by use of an external resistance in series with the gate terminal as in [3] and [5] and as shown in Fig. 1. The external series gate resistance solution is the most attractive since this resistance models not only the NQS effect but also the gate-induced thermal noise [25]. Furthermore, this resistance can be combined with an effective gate resistance to include the effect of the distributed resistance of the gate electrode, as described in Section II-B [26]. B. Distributed Gate Resistance Modeling The effect of the distributed gate resistance becomes important in MOSFET’s at high frequencies, particularly so for wide geometry transistors [27]. Although this effect can be

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(a)

Fig. 5. The simulation and verification methodology. The device simulator is used to generate the data for the parameter extractor and also for verifying the accuracy of y parameters.

(b) Fig. 3.

(a) Substrate network model of [5]. (b) Substrate network model of [4].

Fig. 4. The new substrate network models the substrate as a single resistor. MOSFET capacitances are shown with dashed lines.

minimized by using multifinger transistors, its modeling is important for circuit simulation. A detailed model derived from a transmission-line analysis is available in [28]. However, simple lumped element equivalent circuits are accurate in modeling the distributed gate resistance effect and are also well suited for hand calculations [29], [30]. The effect of the distributed gate resistance is modeled in [29] by a lumped resistance of value , where is the gate sheet resistance and (1/3) and are the transistor width and length, respectively. This simple model has been compared to the detailed analysis of [28] for various technologies in [30]. Furthermore, a significant improvement to the model of [29] is also demonstrated in [30] for predicting the distributed gate resistance effect on the parameters and noise. C. Distributed Substrate Modeling The distributed substrate resistance also plays an important role in high-frequency applications. However, even a recent

Fig. 6. Simulated g and g from the BSIM3v3 model and the device simulator for NMOSFET with W=L = 500=0:6. A reasonable agreement is seen between the simulated data and the BSIM3v3 model.

overview paper on high-frequency MOS device physics [26] has not considered the influence of the substrate on the MOSFET characteristics at high frequencies. Its effect on transistor noise has been investigated in [31] and more recently in [32]. The influence of the substrate on the high-frequency characteristics of the MOSFET can be easily demonstrated with physical device simulations from the 2-D device simulator MEDICI [33]. A low-resistivity substrate is considered here, and similar data can be obtained for a high-resistivity substrate. Two transistor structures are considered: 1) a regular transistor in which the substrate effects are important and 2) a transistor for which the substrate effects have been minimized. The regular transistor is an NMOSFET structure for which the -substrate is 8 m


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TABLE I REAL AND IMAGINARY PARTS OF THE y PARAMETERS FOR THE NEW SUBSTRATE MODEL

TABLE II REAL

AND IMAGINARY PARTS OF THE y PARAMETERS FOR THE SIMPLE SUBSTRATE MODEL

thick. The substrate is heavily doped at a concentration of approximately 10 /cm and has an epilayer in which the transistor is fabricated. A contact is provided at the bottom of the substrate. The transistor structure in which the substrate effects have been minimized has a substrate thickness of 0.8 m and a bottom substrate contact. and are shown in The device simulation results for Fig. 2 for the two transistor structures, one in which the substrate effects are important and the other for which the substrate effects and remain virtually unaffected have been minimized. and have not been shown. From Fig. 2, it is seen that the phase of and is changed due to the presence of the substrate. both a small peaking is observed. In fact, for Recent small-signal BSIM3v3 extensions for RF have incorporated the effect of the substrate as an external network with the BSIM3v3 model [4]–[6]. A substrate coupling network has also been used in the model of [10]. These network approaches are summarized in Fig. 3. The substrate models of [5] and [6] are similar with the exception of additional capacitances in parallel for the model of [6]. The substrate model of [10] is with is used. Hence, similar to that of [4] in that only a single

TABLE III CHANNEL LENGTH AND GATE BIAS DEPENDENCE OF PARAMETERS R ELM FOR DEVICE SIMULATION DATA AT V = 3:0 V

AND

TABLE IV CHANNEL LENGTH AND DRAIN BIAS DEPENDENCE OF PARAMETERS R ELM FOR DEVICE SIMULATION DATA AT V = 1:5 V

AND

our focus will only be on the substrate networks of [4] and [5]. The substrate model of [4] [Fig. 3(b)] is a more complicated than that of [5] [Fig. 3(a)] and requires a complex parameter extracin the network of Fig. 3(b), then tion procedure. If this model also reduces to that of Fig. 3(a). One common feature in both of these models is the use of extrinsic capacitances to account for the drain/source bulk junction capacitances. The MOSFET model junction diode capacitances are not used, as they are set to zero and a different model is required for high frequencies. Therefore, the drawback is that a single model cannot be used from low frequencies to frequencies in the gigahertz regime. III. SUBSTRATE NETWORK MODELING In this section, a new, simple, and accurate substrate network is presented that works consistently with the p-n junction diode capacitances included in the MOSFET model. Since the bias dependence is captured in the diode capacitance model, no separate capacitance extractions are required for each bias point. Furthermore, one single model can be used from low to high frequencies. An analysis of this new substrate model and parameter extraction are also described.

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Magnitude and phase of y as a function of frequency for W=L = Fig. 8. Magnitude and phase of y as a function of frequency for W=L = 500=0:6, V = 0:8 V, and V = 3:0 V with ELM = 24 and R = 500=0:6, V = 0:8 V, and V = 3:0 V. y is accurately modeled even with NQSMOD = 0. 0:85 . The same ELM and R are used in Figs. 7–10. The phase rolloff in y is accurately modeled by NQSMOD = 1 or by the use of R . Fig. 7.

A. New Substrate Model The silicon substrate acts like a distributed resistive network in the low gigahertz regime [34] and as a distributed RC network for higher frequencies. Our experience and that of others [4], [5], [10], indicates that a resistive network is adequate for frequencies up to 10 GHz. Therefore, the substrate can be modeled by a lumped resistor as in Fig. 4. Here, an external substrate resistance is added at the bulk node. This model is a simplification of that in Fig. 3(b) in that no external capacitances are required . and only one lumped resistor is used, i.e., B. Analysis for New Substrate Model The new substrate model is analyzed in terms of two-port parameters in this section. This analysis provides the basis for and in conjunction with the core BSIM3v3 extracting model parameters. The MOSFET circuit of Fig. 4 is analyzed as a two-port device with the input being at the gate and the output at the drain, and both the source and substrate terminals are grounded. From a small-signal analysis of the circuit in Fig. 4 we obtain

(1)

where and and are much larger than Since both approximation can be made:

. the following (2)

whereby (3) were zero The above result is identical to that obtained if does not affect . in Fig. 4. This clearly indicates that can be extracted from the phase of indepenTherefore, . dent of By use of the approximation made in (2) we have

(4) and influence . Since It should be noted that both (based on typical values), the effect of the substrate resistance is observed at lower frequencies compared with the gate resistance. In the frequency range we can simplify the expression for to be (5)


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Fig. 9. Magnitude and phase of y as a function of frequency for W=L = 500mu=0:6, V = 0:8 V, and V = 3:0 V. The phase rolloff in y is qualitatively modeled only by R . NQSMOD = 1 has no effect.

Similarly

(6) that includes is significantly more An analysis for is observed at much complex. However, since the effect of ashigher frequencies, we have derived the expression for is zero. In this case suming

(7) From the above expressions, the real and imaginary parts of each of the parameters can be determined, and these quantities are summarized in Table I. The parameters for the simple substrate network of [5] are given in Table II. These parame, , and ters are obtained from those of Table I by setting to zero. From these tables, it is clear that both and are important and that a simple model does not accurately capture the effect of the substrate. Furthermore, it is also seen that has a significant effect on , and this property is used to . extract an appropriate value for The above analysis also indicates that the models of [5] and [6] [Fig. 3(a)] do not allow coupling of the gate signal to the

Fig. 10. Magnitude and phase of y as a function of frequency for W=L = = 0:8 V, and V = 3:0 V. y is accurately modeled even with NQSMOD = 0.

500=0:6, V

drain, and vice versa, through the substrate ( ) and . This and at high frequencies coupling is important for both and is accounted for in the networks of Figs. 3(b) and 4. Also, for the simple network, the output circuit includes only a single time constant, and there are difficulties in matching the phase of . IV. DEVICE-SIMULATION-BASED VERIFICATION METHODOLOGY In this section, we validate the gate and substrate resistance extensions of the BSIM3v3 model using the device simulator MEDICI [33]. The focus is on modeling of the non-quasi-static and substrate effects. The distributed gate resistance can be modeled as described in Section II-B and is, therefore, not considered here. The methodology used to verify the BSIM3v3 model is shown in Fig. 5. MEDICI was used to determine the I–V characteristics, capacitances, and parameters for a MOSFET based on the doping profiles of a 0.5- m CMOS process. From the device simulation results, the model parameters were extracted using the parameter extractor UTMOST and [35]. Two NMOS transistors of have been used in this comparison. Both the dc and ac parameters of the BSIM3v3 model for each device were extracted from the characteristics obtained from the MEDICI device simulator. The fit of the simulated conductance/voltage characteristics from BSIM3v3 to the device simulator data is shown in Fig. 6. The discrepancies in this data

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(a)

(b)

(c)

(d)

Fig. 11. Simulated s parameters from the device simulator (open symbols) and the BSIM3v3 model: R (dash lines), NQSMOD = 1 (dotted lines) for a frequency range of 100 kHz–10 GHz with W=L = 500=0:6. (a) V = 0:8 V, V = 3 V, ELM = 26, R = 0:65 , and R = 106 ; (b) V = 1:5 V, V = 2 V, ELM = 7.8, R = 0:53 , and R = 130 ; (c) V = 2 V, V = 3 V, ELM = 5.6, R = 0:49 , and R = 120 ; and (d) V = 3 V, V = 3 V, ELM = 3.6, R = 0:46 , and R = 135 .

appear as inaccuracies in the low-frequency comparisons. Once the BSIM3v3 parameters were extracted, SPICE3 was used to determine the parameters at different biases, using different options for high-frequency modeling. The parameters were also computed using the device simulator and compared with the parameters obtained from the circuit simulations. For all BSIM3v3 circuit simulations, the default 40/60 channel-charge partitioning was used since this is the most physical model [2]. A. Model Verification with Substrate Excluded For this verification, we examine devices in which the influence of the substrate has been minimized as explained in Section II-C. The results for the following cases are presented: 1) , i.e., the quasi-static model; 2) NQSMOD NQSMOD and ELM adjusted to give the correct phase for ; 3) external , with NQSMOD and the value of gate resistance

determined from the phase of ; and 4) the simulated device data from MEDICI for the transistor in which substrate effects have been minimized. Additional results and comparisons are available in [36] and [37]. Device and circuit simulation data for PMOSFET’s are also compared in [37]. It should be noted that this is the first comparison of the NQSMOD option of BSIM3v3 for small-signal RF applications. The parameters extracted from the device data are compared with the circuit-level simulations for different biases and were frequencies up to 10 GHz. The parameters ELM and found to be dependent on both the channel length and the bias, as summarized in Tables III and IV. It is seen that there is a dependence on the gate bias but almost no dependence on the drain bias. The parameters for the 0.6- m device for two bias conditions are shown in Figs. 7–10. From the simulated results it is seen that for all four cases, a very good agreement is obtained in


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TABLE V BIAS DEPENDENCE OF PARAMETERS ELM, R , AND R FOR MEASURED TRANSISTOR DATA WITH W=L = 405=0:6

TABLE VI VALUE OF f OBTAINED FROM MEASUREMENT AND SPICE SIMULATIONS FOR

Fig. 12.

W=L = 405=0:6

Photomicrograph of test chip.

the magnitudes of the parameters, whereas there is a disagreement in the phase for some of the cases described above. The following conclusions can be derived from these figures. At low the disagreement in and is due frequencies and low and during parameter exto the lack of a proper fit for traction. This difference also translates into discrepancies in the increases bephase. At high frequencies, the magnitude of cause of the gate-drain overlap capacitance, which could not be eliminated in the device simulations. The parameter NQSMOD , and use of NQSMOD gives affects only the phase of an incorrect phase. The use of a series gate resistance for incorporating the high-frequency rolloff produces results similar to . However, NQSMOD is qualitathose for NQSMOD phase, whereas tively incorrect in predicting the rolloff in the gate resistance model is significantly better. In summary, for a device in which the substrate effects are , , can be obtained for smallnegligible, a match to signal analyses by use of the NQSMOD flag in BSIM3v3 and a proper value of the ELM parameter. The same behavior is reproduced by use of an external resistance in series with the . Both gate, which also accurately models the phase rolloff of are gate-bias and channel-length dependent. These ELM and comparisons indicate that the core BSIM3v3 model with a series gate resistance can account for non-quasi-static operation. B. Model Verification with Substrate Included The effect of the substrate network is now considered in the model verification. The results for the following cases are prewith external substrate resistance sented: 1) NQSMOD , where the values of ELM and are extracted to give and , respectively; 2) external gate the correct phase for and , with NQSMOD and substrate resistances (Fig. 4), where the values of and are extracted to give and , respectively; and 3) the simthe correct phase for ulated device data from MEDICI for the regular transistor. The parameters from the network of Fig. 4 using the MOSFET junction diode models are in good agreement with device simulations for several different bias conditions, as shown in Fig. 11. are bias dependent as shown The values of ELM, , and

in the figure caption. Thus, the original BSIM3v3 model with an external substrate resistance can be also used to account for the effect of the substrate. This combined with the external gate resistance then gives a complete RF MOSFET model that is validated with experimental data in Section V. V. VALIDATION WITH MEASURED DATA In this section, we compare the BSIM3v3 model incorporating the gate and substrate networks with experimental transistor data from a 0.5- m CMOS process from MOSIS. Again the emphasis is on modeling of the non-quasi-static and substrate effects. The data for a transistor with are used. This transistor has an interdigitated layout with 50 fingers to minimize the gate resistance and eight dummy fingers to minimize edge-related etching effects. In the absence of dummy transistors, boundary-dependent overetching can occur, leading to poor matching and significant deviation from the predicted performance. A photomicrograph of the test structure is shown in Fig. 12. One of the goals of this validation process is to demonstrate that the BSIM3v3 model can be extended to RF applications and in simply by extracting appropriate values for Fig. 4. We have made use of the dc and capacitance parameters for the test run from MOSIS. Since the output conductance was not accurately modeled by this parameter set, we re-extracted the dc model parameters from the current/voltage characteristics of the twelve transistors for dc characterization on the test chip. For the drain/source bulk capacitances, the diode depletion region capacitance model from MOSIS was used without any modifications. The first set of validations include a comparison of the BSIM3v3 model and the new substrate network of Fig. 4 with measured data. The non-quasi-static operation was included by or NQSMOD . The values use of a series gate resistance and ELM were extracted from the phase rolloff of , for was determined from a nonlinear least squares fit and . These values are summarized in Table V for the phase of for different bias conditions. In this case, we see that is independent of the bias and that ELM and are bias

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Fig. 13. Magnitude and phase of y , y , y , and y data at V = 0:8 V and V = 3 V.


as a function of frequency for W=L = 405=0:6 for the new substrate network model and measured

dependent. A comparison of the measured and simulated is summarized in Table VI and a good agreement is obtained. The parameters for different bias conditions are compared in Fig. 13. From this figure we see that a reasonable agreement is obtained between the BSIM3v3 model and the measured data for frequencies up to 10 GHz. It should be noted that any disagreement in the low-frequency data is due to the lack of an exact fit to the low-frequency device characteristics. This also translates into discrepancies at high frequencies. The model

with has a better agreement than that with NQSMOD . , NQSMOD predicts an incorrect trend in the In fact, for phase. This problem was also observed in the comparisons with the device simulation data. In addition, there is a disagreement with NQSMOD for higher frein the magnitude of quencies. Thus, for RF applications, improved accuracy can be obtained only with an external gate resistance. The NQSMOD option when used with the substrate network results in a loss in accuracy.


Fig. 14.

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Magnitude and phase of y parameters as a function of frequency for W=L = 405=0:6 for the three substrate models and measured data at V = 3:0 V.

0:8 V and V

The second set of validations include a comparison of all the substrate network models with measurements. For each and/or were exof the substrate models [4], [5], . The values for tracted to obtain a match in the phase of were extracted from the phase rolloff of . The parameters with the three substrate networks are compared in Fig. 14. From these figures, the following conclusions can be made. All networks give the proper magnitude for all of and indicates the parameters. An examination of that the substrate models of Figs. 3(b) and 4 accurately pre-

=

dict the phase variation over frequency. However, we were unable to obtain this behavior with the model of Fig. 3(a). This is not surprising since similar conclusions were derived from the analysis. Last, the parameters obtained from the BSIM3v3 model incorporating the gate and substrate resistances as in Fig. 4 are compared with measured data in Fig. 15 for two different NMOS transistors and one PMOS transistor. This demonstrates that the simple substrate network can accurately model transistor behavior at high frequencies.

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(a)

(b)

(c) Fig. 15. s parameters from measurement (open symbols) and the BSIM3v3 model with R and R (solid lines) for a frequency range of 100 MHz–10 GHz: (a) NMOSFET with W=L = 405=0:6, V = 1:0 V, and V = 3:0 V, (b) NMOSFET with W=L = 405=1:2, V = 1:0 V, and V = 3:0 V, and (c) PMOSFET with W=L = 405=0:6, V = 2:0 V, and V = 2:0 V.

VI. CONCLUSIONS This paper examines MOSFET modeling accuracy for smallsignal RF circuit simulation using the BSIM3v3 model. Extensive comparisons have been made with device simulations and measured data. It is demonstrated that two external lumped resistors are adequate for modeling the non-quasi-static effect and the substrate network. The resistance values can be readily extracted from high-frequency parameter data in conjunction with the low-frequency transistor parameters. When these resistors are combined with the BSIM3v3 model, accurate smallsignal analyses can be performed for frequencies up to 10 GHz. However, the external resistors are bias dependent and are suitable only for small-signal analyses. Physical modeling of these resistors is needed in order to develop an accurate large-signal MOSFET model for RF applications. Such an approach has been demonstrated in [25] for modeling of the gate resistance. Although the lumped resistor modeling approach has been ver-

ified for the BSIM3v3 model in this paper, it is general and can also be used with other compact MOSFET models. ACKNOWLEDGMENT The authors would like to thank Prof. T. Fiez, Dr. W. Liu, J. J. Ou, and X. Jing for several helpful discussions and Avant! TMA for providing the device simulation tools. X. Ouyang’s help with the low-frequency measurements and P. Upadhyaya’s help with parameter extraction is highly appreciated. REFERENCES [1] B. A. A. Antao, “Trends in CAD of analog IC’s,” IEEE Circuits Devices Mag., pp. 31–41, Sept. 1996. [2] BSIM3 Version 3.0 Manual, Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA, 1996. [3] M. C. Ho, K. Green, R. Culbertson, J. Y. Yang, D. Ladwig, and P. Ehnis, “A physical large signal Si MOSFET model for RF circuit design,” in 1997 IEEE MTT-S Dig., June 1997, pp. 391–394.


[4] W. Liu, R. Gharpurey, M. C. Chang, U. Erdogan, R. Aggarwal, and J. P. Mattia, “R.F. MOSFET modeling accounting for distributed substrate and channel resistances with emphasis on the BSIM3v3 SPICE model,” in Dig. Tech. Papers IEDM-97, Dec. 1997, pp. 309–312. [5] J.-J. Ou, X. Jin, I. Ma, C. Hu, and P. Gray, “CMOS RF modeling for GHz communication IC’s,” in 1998 VLSI Technology Symp., June 1998, pp. 94–95. [6] D. R. Pehlke, M. Schroter, A. Burstein, M. Matloubian, and M. F. Chang, “High-frequency application of MOS compact models and their development for scalable RF model libraries,” in 1998 Proc. CICC, May 1998, pp. 219–222. [7] R. Sung, P. Bendix, and M. B. Das, “Extraction of high-frequency equivalent circuit parameters of submicron gate-length MOSFET’s,” IEEE Trans. Electron Devices, vol. 45, pp. 1769–1775, Aug. 1998. [8] Y.-J. Chan, C.-H. Huang, C.-C. Weng, and B.-K. Liew, “Characteristics of deep-submicrometer MOSFET and its empirical nonlinear RF model,” IEEE Trans. Microwave Theory Tech., vol. 46, pp. 611–615, May 1998. [9] C. E. Biber, M. L. Schmatz, T. Morf, U. Lott, and W. Bachtold, “A nonlinear microwave MOSFET model for Spice simulators,” IEEE Trans. Microwave Theory Tech., vol. 46, pp. 604–610, May 1998. [10] S. H.-M. Jen, C. C. Enz, D. R. Pehlke, M. Schroter, and B. J. Sheu, “Accurate modeling and parameter extraction for MOS transistors valid up to 10 GHz,” IEEE Trans. Electron Devices, vol. 46, pp. 2217–2227, Nov. 1999. [11] Y. P. Tsividis, Operation and Modeling of the MOS Transistor. New York: McGraw-Hill, 1987. [12] R. Singh, A. Juge, R. Joly, and G. Morin, “An investigation into the nonquasi-static effects in MOS devices with on-wafer s-parameter techniques,” in Proc. IEEE ICMTS, 1993, pp. 21–25. [13] M. Bagheri and Y. Tsividis, “A small signal dc-to-high-frequency nonquasistatic model for the four-terminal MOSFET valid in all regions of operation,” IEEE Trans. Electron Devices, vol. 32, pp. 2383–2391, Nov. 1985. [14] C. Turchetti, P. Mancini, and G. Masetti, “A CAD-oriented nonquasistatic approach for transient analysis of MOS IC’s,” IEEE J. Solid-State Circuits, vol. SC-21, pp. 827–835, Oct. 1986. [15] H. J. Park, P. K. Ko, and C. Hu, “A nonquasi-static MOSFET model for SPICE-transient analysis,” IEEE Trans. Electron Devices, vol. 36, pp. 561–576, Mar. 1989. [16] P. J. V. Vandeloo and W. M. C. Sansen, “Modeling of the MOS transistor for high frequency analog design,” IEEE Trans. Computer-Aided Design, vol. 8, pp. 713–723, July 1989. [17] K.-W. Chai and J. J. Paulos, “Unified nonquasi-static modeling of the long- channel four-terminal MOSFET for large- and small-signal analyses in all operating ranges,” IEEE Trans. Electron Devices, vol. 36, pp. 2513–2520, Nov. 1989. [18] H. J. Park, P. K. Ko, and C. Hu, “A charge conserving nonquasi-static (NQS) model for SPICE transient analysis,” IEEE Trans. ComputerAided Design, vol. 10, pp. 629–642, May 1991. , “A nonquasi-static MOSFET model for SPICE-AC analysis,” [19] IEEE Trans. Computer-Aided Design, vol. 11, pp. 1247–1257, Oct. 1992. [20] T. Smedes and F. M. Klaassen, “An analytical model for the nonquasi-static small-signal behaviour of submicron MOSFET’s,” Solid-State Electron., vol. 38, pp. 121–130, 1995. [21] E. Dubois and E. Robilliart, “Efficient nonquasi-static MOSFET’s model for circuit simulation,” in Dig. Tech. Papers IEDM-95, Dec 1995, pp. 945–948. [22] W. Liu, C. Bowen, and M. C. Chang, “A CAD-compatible nonquasistatic MOSFET model,” in Dig. Tech. Papers IEDM-96, Dec. 1996, pp. 151–154. [23] Y. P. Tsividis and K. Suyama, “MOSFET modeling for analog circuit CAD: Problems and prospects,” IEEE J. Solid-State Circuits, vol. 29, pp. 210–216, Mar. 1994. [24] M. Chan, K. Y. Hui, C. Hu, and P. K. Ko, “A robust and physical BSIM3 nonquasi-static transient and AC small-signal model for circuit simulation,” IEEE Trans. Electron Devices, vol. 45, pp. 834–841, Apr. 1998. [25] X. Jin, J. J. Ou, C. H. Chen, W. Liu, M. J. Deen, P. R. Gray, and C. Hu, “An effective gate resistance model for CMOS RF and noise modeling,” in Dig. Tech. Papers IEDM-98, Dec. 1998, pp. 961–964. [26] T. Manku, “Microwave CMOS—Device physics and design,” IEEE J. Solid-State Circuits, vol. 34, pp. 277–285, Mar. 1999. [27] R. P. Jindal, “Noise associated with distributed resistance of MOSFET gate structures in integrated,” IEEE Trans. Electron Devices, vol. ED-31, pp. 1505–1509, Oct. 1984.

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[28] E. Abou-Allam and T. Manku, “A small-signal MOSFET model for radio frequency IC applications,” IEEE Trans. Computer-Aided Design, vol. 16, pp. 437–447, May 1997. [29] B. Razavi, R. H. Yan, and K. F. Lee, “Impact of distributed gate resistance on the performance of MOS devices,” IEEE Trans. Circuits Syst. I, vol. 41, pp. 750–754, Nov. 1994. [30] S. F. Tin, A. A. Osman, and K. Mayaram, “Comments on ‘A small-signal MOSFET model for radio frequency IC applications’,” IEEE Trans. Computer-Aided Design, vol. 17, pp. 372–374, Apr. 1998. [31] R. P. Jindal, “Distributed substrate resistance noise in fine-line NMOS field-effect transistors,” IEEE Trans. Electron Devices, vol. ED-32, pp. 2450–2453, Nov. 1985. [32] S. V. Kishore, G. Chang, G. Asmanis, C. Hull, and F. Stubbe, “Substrateinduced high-frequency noise in deep sub-micron MOSFET’s for RF applications,” in 1999 Proc. CICC, May 1999, pp. 365–368. [33] Technology Modeling Associates, Medici, 1997. [34] N. K. Verghese and D. J. Allstot, “Computer aided design considerations for mixed-signal coupling in RF integrated circuits,” IEEE J. Solid-State Circuits, vol. 33, pp. 314–323, Mar. 1998. [35] Silvaco International, Silvaco Toolset, 1995. [36] S. F. Tin, A. A. Osman, K. Mayaram, and C. Hu, “BSIM3 MOSFET model accuracy for RF circuit simulation,” in Proc. Radio Wireless Conf., Aug. 1998, pp. 351–354. [37] S. F. Tin, “High frequency MOSFET modeling for circuit simulation,” M. S. thesis, Washington State University, Pullman, Dec. 1998.

Suet Fong Tin received the B.S and M.S. degrees in electrical engineering from Washington State University, Pullman, in 1996 and 1998, respectively. She joined the Timing Technology Division of Cypress Semiconductor, Woodinville, WA, in 1999 as a Product Engineer, where she is responsible for the characterization and qualification of motherboard clocks.

Ashraf A. Osman received the B.S. degree from the University of Khartoum, Khartoum, Sudan, in 1991 and the M.S. degree from Washington State University, Pullman, in 1994, both in electrical engineering. He is currently pursuing the Ph.D. degree in electrical engineering at Washington State University. He joined the Analog & Mixed-Signal Design Methods group at Level One Communications, an Intel company, in January 1999, where he is working on SPICE model extractions, testing, and verification. His research interests are SOI and bulk MOSFET modeling for mixed-signal and RF applications.

Kartikeya Mayaram (S’82–M’89–SM’99) received the B.E. (Hons.) degree from the Birla Institute of Technology and Science, Pilani, India, in 1981, the M.S. degree from the State University of New York, Stony Brook, in 1982, and the Ph.D. degree from the University of California, Berkeley, in 1988, all in electrical engineering. From 1988 to 1992, he was a Member of Technical Staff in the Semiconductor Process and Design Center of Texas Instruments, Dallas. From 1992 to 1996, he was a Member of Technical Staff at Bell Labs, Allentown, PA. He was an Associate Professor in the School of Electrical Engineering and Computer Science, Washington State University, Pullman, from 1996 to 1999. Since January 2000, he has been an Associate Professor in the Electrical and Computer Engineering Department of Oregon State University, Corvallis. His research interests are in the areas of circuit simulation, device simulation and modeling, integrated simulation environments, and analog/RF design. Prof. Mayaram received the National Science Foundation CAREER Award in 1997. He is an Associate Editor of IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS.

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Chenming Hu (S’71–M’76–SM’83–F’90) received the B.S. degree from National Taiwan University, Taiwan, R.O.C., and the M.S. and the Ph.D. degrees in electrical engineering from the University of California (UC), Berkeley. Currently, he is Chancellor’s Professor of Electrical Engineering and Computer Sciences at UC Berkeley. Previously, he was an Assistant Professor at the Massachusetts Institute of Technology, Cambridge. He is the Board Chairman of BTA Technology, Inc., and of the East San Francisco Bay Chinese School. He is a frequent Advisor to industry and educational institutions. His present research areas include microelectronic devices, thin dielectrics, circuit reliability simulation, and nonvolatile memories. He is an author or coauthor of four books and more than 600 research papers, and he has supervised 60 doctoral students. Prof. Hu is a member of the U.S. National Academy of Engineering and a Life Honorary Professor of the Chinese Academy of Science. In 1991, he received the Excellence in Design Award from Design News and the Inaugural Semiconductor Research Corporation Technical Excellence Award for leading the research of IC reliability simulator, BERT. He received the SRC Outstanding Inventor Award in 1993 and 1994. He leads the development of the MOSFET model BSIM3v3 that has been chosen as the first industry standard model for IC simulation by the Electronics Industry Alliance Compact Model Council and given an R&D 100 Award in 1996 as one of the 100 most technologically significant new products of the year. He received the 1997 Jack A. Morton Award from the IEEE for his contributions to the physics and modeling of MOSFET reliability. Also in 1997, he received UC Berkeley’s highest honor for teaching, the Distinguished Teaching Award. In 1998, he received the Monie A. Ferst Award of Sigma Xi for encouragement of research through education. He received the Pan Wen Yuan Foundation Award for outstanding research in electronics in 1999.
