A Simplified Spice Based IGBT Model for Power Electronics Modules ...

A Simplified Spice Based IGBT Model for Power Electronics Modules Evaluation F. Chimento

N. Mora

M. Bellini, I. Stevanovic

S. Tomarchio

IEEE Member ABB AB Corporate Research Forskargränd 8 721 78, Västerås, Sweden [email protected]

University of Parma DII Viale G.P. Usberti 181/A, 43100, Parma, Italy [email protected]

IEEE Members ABB Ltd. Corporate Research, Dättwil, 5405 Switzerland [email protected]

University of Catania DIEEI Viale A. Doria 6, 95125 Catania, Italy [email protected]

Abstract -- The paper deals with the evaluation of a suitable model for power IGBTs targeted for use in power electronic modules. The main issue for the developed model is the possibility of creating a circuital based structure starting from the device physical equations. The model is implemented in a circuital simulation environment with the aim of evaluating the performance of high voltage, high current modules. In those a key factor is the possibility of having computation times fitting with the necessity of parasitic elements estimation. The implementation of the model is described together with the validation of it by comparison with experimental results. Index Terms – IGBT model, lumped charge.

I. qpi qni QB ipij inij vij uij tt

NOMENCLATURE

Hole charge lumped into node i Electron charge lumped into node i Ionized background dopers in base Hole current flowing from node i to j Electron current flowing from node i to j Voltage drop between nodes i and j Voltage drop between nodes i and j normalized to thermal voltage Vth Base transit time II.

INTRODUCTION

In parallel to the research to scale up the Insulated Gate Bipolar Transistor’s (IGBT) power handling limits, extensive studies were made to model the device behaviour. Many different types of IGBT models exist and, basing on the modeling method used, they can be divided into 5 different groups [1]. Numerical models rely on Finite Element Method (FEM) and they are tailored specifically to model several advanced physical effects. Due to their complex nature, these models trade computation times for accuracy. Seminumerical models attempt to mitigate the computational efforts by only modeling a specific critical region of the device and using other types of models for the remaining ones. These approaches usually require complex and costly parameter extraction procedures, thus their use is mainly intended for device manufacturers rather than application engineers. On the opposite side are the Behavioral models, which attempt to emulate the device with empirical relations, resulting from a fitting on the characteristics, regardless of the physical underlying mechanisms. On the other hand, Mathematical models describe the physical equations that govern the device’s electrical behaviour. Semimathematical

978-1-61284-971-3/11/$26.00 ©2011 IEEE

models are more oriented towards simulation speed and describe the device by means of existing models, while retaining several specific physical equations. Several analytical, physics based models have been proposed in the past for the IGBT. One of the first models which proved good accuracy and reliability was the one developed by Hefner [2]-[3]. With the introduction of a “redistribution current”, Non Quasi Static (NQS) effects were modelled for the carriers distribution in the base region. The model, originally purely equation based, was implemented in Saber [4], and later adapted for use in Spice environments [5]. A simplified version of the model, implemented in PSpice, can also be found in Raciti et al. [6]. From the same authors, another PT-IGBT model is presented in [7]. Kraus et al. developed models for power semiconductor devices in [8], based on combining user defined blocks and existing models. A different modelling technique, known as the Lumped Charge [9], was firstly introduced by Lauritzen and Ma, based on Linvill’s Lumped Parameter approach and the standard charge control method. This modelling approach consists in the discretization of the device into several critical regions, each one being responsible to describe the carrier behaviour and concentration as if they were all lumped into a point. The discretized regions are then connected to each other by means of a set of equations derived from the device physics and circuit theory. The Lumped Charge technique was successfully employed for the development of many power device models: diode [10]-[11], SCR [12], GTO [13], MCT [14], MOSFET [15], BJT [16], and the IGBT [17]. The aim of this work is to build up a compact model for the evaluation of power electronics modules. The possibility of implementing these models in widespread circuit simulators, such as PSpice, is of major interest because it allows designers to maintain a reasonable ease of use for more complex applications design. As far as the performance of the model is concerned, it should exhibit contained computation times but yet maintain a reasonable accuracy while capturing the basic physical phenomena of the device. The target of this model is, in fact, to offer the designer a quick, flexible platform to estimate the performance of the switch without ending up in costly and time consuming experimental procedures. In this sense, the parameter extraction procedure complexity plays a crucial role too. A ranked list of the main quantities to be optimized in the model was considered. Those are, namely: switching losses

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(with particular remark on the current tail at turn-off), driving requirements and external circuit impact on the di/dt and dv/dt, capability of fitting different current and voltage levels, current peaks at turn-on (diode reverse recovery), voltage overshoot at turn-off (stray inductances). All the factors described above led to the choice of the Lumped Charge approach for the intended IGBT model [17]. In addition, PSpice was chosen as the main platform for the implementation of the model. Its nature requires, though, a sub-circuit based approach in modelling the device equations. This results in several issues that must be addressed. Among all, convergence and computation efficiency are the most challenging ones. III.

PHYSICAL MODEL DESCRIPTION

The Lumped charge technique can be applied systematically to the modelling of power semiconductors by following these steps. At first the device structure is discretized into several critical regions, each one being characterized by constant doping and/or constant carrier lifetimes. To each region is then assigned one charge storage node and up to two connection nodes. Then, the hole and electron charge values are obtained by multiplying the carrier concentration and its critical volume. Finally, the charge nodes are linked to each other by means of the following six equations, derived from device physics and circuit theory: (i) Current Density Equations; (ii) Current Continuity Equations; (iii) Charge Neutrality Equations; (iv) Boltzmann’s Relations (p-n Junction Equations); (v) Poisson’s Equations; (vi) KCL and KVL laws; Equations (i) through (v) describe the carrier distribution and transport between charge nodes, the last one relates the internal variables to the terminals of the device. This systematic approach can be followed since all power semiconductor devices can be viewed as a combination of the following representative structures: · p+n- structure (or n+p-) · n-n+ structure (or p-p+) · MOS structure The IGBT model reported in [17] is based on the same Lumped Charge approach as described above. However, in order to keep the model relatively simple, the internal base charges are calculated only at the edges of the internal base region. In addition, the bipolar portion of the IGBT is modeled with physics based equations, while the MOSFET part is described by means of empirical equations. The physical phenomena described by that model include: base region charge storage and recombination, base transport equation for low and high level injection, junction emitter efficiency, base width modulation limited by punch through at high collector voltages, collector gate and collector emitter capacitance variation, emitter parasitic resistance and inductance. The gate emitter capacitance is held constant. The list of the 17 model parameters can be found in [17]. The complete equation set, instead, is reported in Table 1 and

Table 2 of the Appendix: for further information the reader can refer to [17]. Equations (A.1), (A.2), (A.5) and (A.7) are KVLs, while (A.12)-(A.15) represent KCLs. Equations (A.16), (A.17), (A.18) and (A.20) account for the device’s capacitances. In particular, the gate-collector capacitive current, (A.18), is based on the moderate depletion model of the charge under the gate-drain overlap region [15], as expressed in (A.21). Equations (A.9) and (A.10) account for end region recombination. Particularly important in the calculation of the bipolar gain is the emitter injection efficiency, represented in (A.9) as the electron current injected into the emitter (explicitly dependent on the parameter ta). Equation (A.6) results from the application of the non equilibrium mass action law across the injecting junction (where Qi is the total intrinsic concentration in base). Charge neutrality is assumed in the base, so that the electron charge qn4 is equal to the hole charge qp4 plus the ionized background donors QB. E/K

G

vgki

ig

Lk vki

iK rk

Cgk

iCgk

iCag

vox 6

id

5

v45

ip46

v45

+

+

ip34 - ip46

ip46 v34 4

vdep

in56

iCak

-

iCag

+

in45

ip34

iCab

in34

+

3

.. .

C/A

Charge equations blocks

ip34-ip46

d ( q p4 × y )

q p4 - Q pB

dt

t

y

b

Fig. 1: Proposed equivalent circuit and lumped charge nodes location superimposed to the IGBT half-cell. Equation (A.4) accounts for the potential drop in the conductivity modulated base region. Discretization of the electron and hole currents in the base gives: i n 45 =

q p5 - q p4

i p 46 =

tt

+

q p 4 - q p5 tt

q p4 + QB tt

+

q p4 tt

(1)

u 45

(2)

u 45

Summing (1) and (2) and solving for u45 result in equation (A.4). Equation (A.27) can be derived by substituting (A.4) into (2). This yields the quadratic equation:

[ (

)

]

(

)

2 q p 4 2 + q p 4 tt in 45 - i p 46 - 2q p 5 + QB - QB q p 5 + tt i p 46 = 0

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(3)

in which the terms bq and cqm of (A.25) and (A.26) are easily identifiable. Equation (A.19) is the current hole continuity equation applied to the base charge qp4. A final remark on the variable base width calculation is that even though the model has been developed for a PT-IGBT, the device is described as a properly modified NPT-IGBT. In fact, charge storage phenomena are only considered for qp4, as shown in the continuity equation (A.19). Thus, at turn-off, the current exponential decay is dictated only by this lumped charge contribution, instead of considering separately the charge stored in the drift layer and in the buffer layer. As a consequence, the minority carrier lifetime parameter represents an averaged lifetime. In order to emulate a punchthrough behaviour, the smoothing function (A.28) is introduced, which modifies the width of the depletion layer ((A.29) in conjunction with (A.30)) to account for the presence of the buffer layer. IV.

PSPICE IMPLEMENTATION

Having introduced the model equations, the next step towards the final implementation is to identify an equivalent circuit capable of representing them. Fig. 1 shows a schematization of such a circuit, along with the lumped charge nodes used, superimposed to an IGBT half cell. All the equations involving currents and voltages have been implemented as controlled sources by means of the PSpice Analog Behavioral Modeling (ABM) feature. This allows a particular current (or voltage) to be represented as an analytical function of other controlling quantities, both currents and voltages. Some model equations, namely the KCL and KVL ones, are then fulfilled by proper interconnection of these ABM blocks. The model requires also to calculate several other quantities which are not currents or voltages, i.e. the lumped charges and the base transit time. Nevertheless they can be treated as the other ones if we represent them, for example, as net voltages. The ABM feature also offers some kind of programming capability. It is possible, in fact, to implement conditional statements with the built-in logic function IF(condition,x,y). This feature is particularly useful to implement the MOSFET current equation and for the charge equations (where the behavior is dependent on the bias). Nevertheless, if on the one hand this feature is extremely flexible, on the other hand it may cause severe convergence problems due to possible discontinuities. Another interesting feature of ABM is the built-in time derivative function DDT(). This allows the definition of displacement currents in the expression of a controlled source, without need to use dedicated sub-circuits. However, as in the previous case of conditional statements, this function has to be used with particular care. It is possible, in fact, that these blocks, at the beginning of a transient analysis, force unphysical initial conditions into the circuit. In order to prevent that, the derivatives should be initially held to zero for a small time interval. This can be performed by multiplying the derivatives by a suitable step function, which

in PSpice is defined as STP(TIME-t0), where t0 is the initial null time interval. When implementing models with the ABM feature, many convergence issues can arise [19]-[20]. The complexity of the system, in terms of hard nonlinearities and multiple cross references between blocks, makes mandatory the use of high value resistors to be placed across each ABM block to ensure a DC path capable of handling the overall circuit bias and preventing a hard nonlinearity to take the next iteration of the Newton-Raphson algorithm far from the final solution. These resistors (not shown in Fig. 1) must be sized big enough in order to affect negligibly the circuit. It is also possible to aid convergence in bias point calculation at the onset of a transient analysis by providing an appropriate initial guess for a certain node. This is particularly useful for highly nonlinear devices (and also in cases where multiple bias points are possible). Other convergence issues can arise if too sharp transitions are applied to the circuit. This can lead to a situation where maximum simulation thresholds are exceeded or result in discontinuities, since the time step cannot be made indefinitely small. Normalizing the values also helps obtaining better performance since, in general, it leads to a reduction of the dynamic range in which the simulator has to obtain the required precision and also prevents exceeding the absolute magnitude limits. Proper selection of PSpice options and simulation parameters according to [20] is mandatory to obtain convergence. As an example of application of the described techniques that improve convergence, let us consider the representation of the equation (A.6) used to calculate the voltage drop across the injecting junction (v34, referring to Fig. 1): 2 q p 4 × (q p 4 + QB ) = Qi × exp (q × v 34 kT ) (4) Since the term Qi2 depends on the exponential of the ratio -vjunction/vthermal, it can easily reach, even at room temperature, extremely small values, well beyond 10-30. This leads to numerical problems related to the machine finite precision. In fact, if we solve analytically this equation for v34 and straightforwardly implement it with a simple controlled voltage source, the solution is (a) not guaranteed (possible overflows) and (b) dependent on the order in which the operations are performed (remember that the precision is finite and thus floating point operation can lead to coarse rounding errors if operands are extremely different). In order to overcome this difficulty, (4) was firstly reformulated:

(

q p4 × q p4 + QB

)

= (G sc × Qi ) exp (q × v 34 kT ), (5) (Qi Gsc ) Where Gsc is a suitable scaling factor, used to ensure that the quantities are kept within the maximum limits. Then, (5) can be implemented as a dedicated sub-circuit, consisting of a controlled current source representing the left side of the equation and a current source controlled by v34 representing the right side. In addition, a big resistor is placed in parallel to the last source in order to avoid floating node errors.

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MODEL VALIDATION Different load conditions were imposed to check the model stability and reliability: Fig. 4 through Fig. 9 show some of the comparisons between simulated and experimental data. It is important to stress that the parameter set in each test is the same: in this way we can evaluate the adaptability of the model to different conditions. Switching waveforms: Turn-on 2500

I - PSpice C

I - Exp. C

2000

- Exp.

[V] CE

0

1

1.5

2

2.5

3

3.5

4

4.5

Time [s]

5 -6

x 10

Fig. 4: IC-VCE turn-on waveforms comparison for the 1800 V, 600 A case (IC: 500 A/div, Turn-off VCE: 500 V/div). Switching waveforms: 2500

2000

3500

I - PSpice C

I - Exp. C

V 1000

V

VGE= 13 V

3000

- PSpice

500

IC [A] VCE [V]

4000

VGE= 15 V

CE

1000

1500

PSpice SIMetrix Exp. (data sheet)

4500

CE

1500

5000

I C [A]

V V

IC [A]

In order to obtain a more realistic operation when the model is embedded in practical applications, the diode reverse recovery at turn-on must be included. In general, in fact, the reverse recovery cannot be neglected, especially since it can affect noticeably the switching losses. Thus, a diode model is needed to perform a full switching simulation. Keeping in mind the requirements for the model, and in order to maintain a coherent approach, the Lumped Charge technique was chosen to implement a basic diode model with reverse recovery, as indicated in [21]. In order to validate the IGBT model, first the static IC-VCE characteristic has been extracted and compared to the data obtained from the device datasheet. A further comparison was made with a Verilog-A implementation of the model (SIMetrix as software platform), in order to check the independency of the model with respect to the simulation platform. As it is shown in Fig. 2, the agreement is good for middle-high current levels (above 10% of nominal device current). The displacement of the simulated characteristics with the experimental ones is mainly due to the nature of the model and to the extraction parameters procedure. Moreover the simplifications intrinsic to the model are such that in the condition VBE < threshold voltage, the base-emitter junction of the bipolar part of the device takes the whole of the voltage drop until the voltage overtakes the direct bias threshold. In this way the MOSFET part does not have the sufficient voltage to start conducting thus leading to a step in the function of IC.

V

V.

CE CE

- PSpice - Exp.

2500

500

2000

VGE= 11 V

1500 1000

0

500

VGE= 9 V

1.95

2

2.05

2.1

0

1

2

3

4

5

VCE [V]

6

7

8

2.15

2.2

2.25

2.3

2.35

Time [s]

0 9

10

2.4 -5

x 10

Fig. 5: IC-VCE turn-off waveforms comparison for the 1800 V, 600 A case (IC: 500 A/div, VCE: 500 V/div).

Fig. 2: Static DC IC-VCE characteristic (IC: 500 A/div, VCE: 1 V/div).

3000

I - PSpice C

IC - Exp.

2500

Subsequently, to evaluate the dynamic performance of the model, a clamped inductive load switching circuit was used as a test bench, as shown in Fig. 3.

V V

[V] CE

C

CE

- PSpice - Exp.

1500

V

I [A]

2000

CE

1000

500

0

1

1.5

2

2.5

3

Time [s]

3.5

4

4.5

5 -6

x 10

Fig. 6: IC-VCE turn-on waveforms comparison for the 1800 V, 1200 A case (IC: 500 A/div, VCE: 500 V/div).

Fig. 3: Schematic of the experimental test bench.

1099

2500

2000

IC - PSpice IC - Exp.

IC [A]

VCE [V]

1500

VCE - PSpice 1000

VCE - Exp.

500

0

1.95

2

2.05

2.1

2.15

2.2

2.25

2.3

2.35

Time [s]

2.4 -5

x 10

Fig. 7: IC-VCE turn-off waveforms comparison for the 1800 V, 1200 A case (IC: 500 A/div, VCE: 500 V/div). Integrated Losses

Losses [J]

2

0 -1

APPENDIX: THE COMPLETE MODEL EQUATION SET In the following tables, the model equations are listed. Cathegory/Expression Voltage Equations

Relative error = +9.31%

1

implementation of the model, in order to check the independency of the model with respect to the simulation platform. Results show a good agreement in the mid-high current range. Finally, the dynamic performance of the model was evaluated by performing clamped inductive load switching simulations. In order to obtain more realistic results, a simple diode model with reverse recovery was implemented, following the same Lumped Charge approach used for the IGBT. Simulations of the IGBT and diode model together were then performed to extract the switching waveforms. Comparison with the experimental data shows a reasonable agreement in terms of total switching losses, especially at mid-high current levels.

v gki = v ( g ) - v ( k ) - vki

PSpice Exp. 0

0.5

1

1.5

(A.1) (A.2) (A.3) (A.4) (A.5) (A.6) (A.7) (A.8)

u5 g = u5ki - u gki 2

Time [s]

uox = q AG (Cox × Vth ) u45 = tt × (in 45 + i p 46 ) /( 2 × q p 4 + QB )

2.5

u5 g = udep + u ox

-5

x 10

Fig. 8: Switching losses comparison for the

q p 4 × ( q p 4 + QB ) = Qi 2 exp( u34 )

1800V, 600A case (500 mJ/div).

uak = u34 + u45 + u5ki + uki vki = ik * rk + d ( Lk × ik ) dt

Current Equations

in34 = I AS × [exp(u34 ) - 1] in56 = -I KS × [exp(-u5ki ) - 1]

ì0 ï id = í k p ï2 î

Fig. 9: Switching losses comparison for the 1800V,1200A case (1J/div).

if v gki £ VT

b

æ k ×v æ v gki ö çç - 1÷÷ tanhç v 5ki ç v gki - VT ø è VT è

ö ÷ ÷ ø

else

in 45 = iCak + id + iCag + in 56

i p 34 = i A - in 34 - iCab iK = i A - iCag + iCgk

iCak = d (q56 ) / dt iCab = d ( q34 ) / dt iCag = d (q AG ) / dt i p34 - i p 46 =

q p 4 - Q pB

tb

y+

(A.11) (A.12) (A.13) (A.14) (A.15) (A.16) (A.17) (A.18)

i A = i p 46 + in 45

VI. CONCLUSIONS A physics based model for the Insulated Gate Bipolar Transistor has been implemented in PSpice. The Lumped Charge modelling approach was followed, since it provides a good trade off between accuracy and simulation speed. The model, developed for the evaluation of high voltage, high current power modules, offers reasonable computation times, thus allowing the inclusion of complex parasitics. Moreover, the extraction of the model parameters is relatively fast and simple. During the model development, several convergence issues were encountered and addressed. The final PSpice realization is stable over multiple loading conditions and for different parametric sets. In order to validate the model, first the static IC-VCE characteristic has been extracted and compared with the experimental one, derived from the device data sheet. A further comparison was made with a Verilog-A

(A.9) (A.10)

d (q p 4 × y) dt

iCgk = d (C gk 0 × vgki ) / dt

(A.19) (A.20)

Charge Equations ìq ag 0 × ABS[exp( -u dep ) + u dep - 1] ï q AG = í ï- qag 0 × ABS[exp( -u dep ) + u dep - 1] î

ìQ ak 0 × 1 + u 5 ki u j ï q56 = í ïQ ak 0 + u 5ki × Q ak1 - u 5ki 2 × Q ak 2 î

1100

if u dep ³ 0 else

if u 5 ki ³ 0 else

(A.21) (A.22)

q34 = Vth × Cab0 × u34 q p 5 = Q pB × exp(-u5ki )

(A.23) (A.24)

D

bq = tt × (in 45 - i p 46 ) + QB - 2 × q p 5 D

cqm = QB × (q p 5 + tt × i p 46 )

q p4

2 × cqm ì ï bq + ABS[bq 2 + 8cqm] ïï =í ï - bq + ABS[bq 2 + 8cqm] ï ïî 4

(A.25) (A.26)

if bq 2 > 100 × cqm

(A.27) else

Terminal Currents i (a ) = i A i ( g ) = -iCag + iCgk

i( k ) = -iK

Variable Base Width Calculation é æu öù ulim = exp ê 40 × ç 5ki - 0.87 ÷ú çu ÷ú øû ëê è pt u j + u5ki + 0.9 × ulim u pt + (i p 46 - id ) × ruh yu = 1 + ulim

ì y = í1 - yu î1

if yu ³ 0 else

(A.28) (A.29) (A.30)

tt = T0 × y

(A.31) Table 1: The complete model equation set. Internal Parmeter Value 2 × C ak 0 Cab0 k (T + 273) q Vth C ox × g × Vth qag0 2 × T0 × I LH QB Q exp(u j ) Qi B 2 Qi × Qi Qi Qi 2 QB QpB tk ta 2 IAS Qi (QB × t a ) 2 Qi (QB × t k ) IKS 2 × C ak 0 × V j Qak0 C ak 0 × Vth Qak1 C ak 0 × Vth (4 × u j ) Qak2 Table 2: Internal parameters recalled in the equations.

REFERENCES [1] K. Sheng, W. Williams, S.J. Finney, “A Review of IGBT Models”, in IEEE Trans Pwr. Elec., vol. 15, pp.1250-1266, Nov. 2000. [2] A. R. Hefner, “An Improved Understanding for the Transient Operation of the Power Insulated Gate Bipolar Transistor (IGBT),” in Conf. Rec,. IEEE Power Electronics Specialists Conf, 1989; also in IEEE Trans. Power Electron., vol. 5, p. 459, 1990.

[3] A. R. Hefner, “An Investigation of the Drive Circuit Requirements for the Power Insulated Gate Bipolar Transistor (IGBT),” in Conf. Rec,. IEEE Power Electronics Specialists Conf, 1990; also in IEEE Trans. Power Electron., vol. 6, p. 208. 1991. [4] A. R. Hefner, “An Experimentally Verified IGBT Model Implemented in the Saber Circuit Simulator,” in Conf. Rec,. IEEE Power Electronics Specialists Conf, 1991. [5] C. S. Mitter, A.R. Hefner, D. Y. Chen, F. C. Lee, “Insulated Gate Bipolar Transistor (IGBT) Modeling Using IG-Spice” in IEEE Transactions on Industry Applications, vol. 30, no. 1, January/February 1993. [6] F. Frisina., C. Leonardi, A. Raciti, S. Torrisi, “Physics based model of punch through IGBTs simulated by PSpice,” in Computers in Power Electronics, 1998. 6th Workshop on, pp.27-35, 1998. [7] F. Frisna, R. Letor, S. Musumeci, A. Raciti, M. Sardo, “PTIGBT PSpice Model with New Parameter Extraction for LifeTime and Epy Dependent Behaviour Simulation,” in Conf Rec. of IEEE Power Electronics Specialists Conference PESC’96, pp. 1682-1688, Jun. 1996. [8] R. Kraus, P. Turkes, J. Sigg, “Physics-Based Models of Power Semiconductor Devices for the Circuit Simulator Spice,” in Power Electronics Specialists Conf. PESC’98, vol. 2, pp. 17261731, May 1998. [9] C. L. Ma, P. O. Lauritzen, P.Y. Lin, I. Budihardjo, “A Systematic Approach to Modeling Power Semiconductor Devices Based on Charge Control Principle,” in IEEE PESC ’94 Record., vol. 1, pp.31-37, Jun. 1994. [10] C. L. Ma, P. O. Lauritzen, “A Simple Power Diode Model with Forward and Reverse Recovery,” in IEEE Trans. Power Electron., vol.8, no. 4, pp.342-346, 1993. [11] C. L. Ma, P. O. Lauritzen, J. Sigg, “Modeling of Power Diodes with the Lumped-Charge Modeling Technique,” in IEEE Trans. Power Electron., vol. 12, no. 3, pp. 398-405, May 1997. [12] C. L. Ma, P. O. Lauritzen, J. Sigg, “Modeling of High-Power Thyristors Using the Lumped-Charge Modeling Technique,” in 6th European Conf. on Power Electronics and Applications, 1995. [13] C. L. Ma, P. O. Lauritzen, J. Sigg, “A Physics-Based GTO Model for Circuit Simulation,” in IEEE Power Electronics Specialists Conf., pp. 872-878, 1995. [14] Z. Hossain et al. “A Physics-Based MCT Model Using the Lumped-Charge Modeling Technique,” in IEEE Power Electronics Specialists Conf, pp. 23-28, 1996. [15] I. Budihardjo, P. O. Lauritzen, “The Lumped-Charge Power MOSFET Model, Including Parameter Extraction,” in IEEE Trans. Power Electron., vol. 10, no. 3, pp. 379-387, 1995. [16] N. Talwalkar, P. O. Lauritzen, B. Fatemizadeh, D. Perlman, C. L. Ma, “A Power BJT Model for Circuit Simulation,” in IEEE Power Electronics Specialists Conf, PESC ’96 Record., vol. 1, pp. 50-55, 1996. [17] P. O. Lauritzen, G. K. Andersen, and M. Helsper, “A basic IGBT model with easy parameter extraction,” in Proc. IEEE PESC’01 Conf., vol. 4, 2001, pp. 2160–2165. [18] B. J. Baliga, “Fundamentals of Power Semiconductor Devices,” Springer. [19] A. Maxim, D. Andreu, J. Boucher, “The Analog Behavioral Spice Macromodeling – A Novel Method of Power Semiconductor Devices Modeling,” in IECON’98, vol. 1, pp. 375-380, Sept. 19 [20] PSpice User’s Guide. [21] P. O. Lauritzen, C. L. Ma, “A simple diode model with reverse recovery," in IEEE Trans. Pwr. Elec., Vol. 6, No. 2, pp. 188191, April 1991.

1101