A SoC test strategy based on a non-scan DFT method - Test

A SoC Test Strategy Based on a Non-Scan DFT Method Hiroshi Date, Toshinori Hosokawa and Michiaki Muraoka Design Technology Development Department, Semiconductor Technology Academic Research Center (STARC) 5F Yusen Shin Yokohama Bldg, 3-17-2,Shin Yokohama, Kohoku-ku, Yokohama, 222-0033, Japan { date, hosokawa, muraoka}@starc.or.jp TEL:+81-45-478-3222 / FAX:+81-45-478-3299 Abstract This paper proposes a System-on-a-Chip (SoC) test strategy based on a non-scan DFT method. Especially, we evaluate a basic DFT method, called NS-DFT, comparing with a full scan DFT method. The experimental results for practical circuits and benchmark circuits demonstrate the efficiency of the NS-DFT. Keywords : SoC test, non-scan DFT, high level design and test

application time. The second is to optimize the test cost that includes area overhead for test, test application time, test quality, power consumption for test, fault efficiency, and so on. The third is to improve the quality of test pattern generation for SoC. These issues depend on the utilized DFT (Design for Test) method for SoC. The test system inputs circuit specification at the architecture level, and outputs the RTL circuit with DFT to obtain high fault efficiency. System specification

1. Introduction With the progress of the semiconductor process technology, the gate count of SoC is increasing as large as one hundred million gates through the use of 100 nm process design rule toward 2010. As the size of the SoC is getting larger, the reduction of the design power and power consumption will be the most important issues. For these reasons, design productivity and power consumption will cause the new design crisis in the electronics industry. The technologies that solve these issues are the design reuse methodology and design automation at the high-level design phase. The research and development of these technologies will be the most important to innovate the SoC design methodology. The VCDS (VCore Based Design System) has been proposed as the next generation EDA system based on VCores, VCores are reusable cores that can be used in the high-level design phase such as system level and architecture level to solve the design crisis [1]. The key technologies of the VCDS are the VCore-based design methodology and the design automation technology, shown in Figure 1. To accelerate the productivity of SoC design, the re-use methodology has to be shifted to the higher level from RT level and the automation technology has to be developed to improve the use of VCores. As for a testing system in VCDS, there are three aims of its methodology. The first aim is to shorten its test

Proceedings of the 11 th Asian Test Symposium(ATS’02) 1081-7735/02 $17.00 © 2002 IEEE

Architecture generation

Interface synthesis

Software generation

SoC test architecture generation

Hardware generation

Hard VCore DFT (BIST, external test)

Figure 1 Key technologies in VCDS The scan design method [2, 3] at the gate level is one of the most popular DFT methods. However, it has the following disadvantages. (1) Test circuits cause a degradation of performance and/or area due to the DFT application at the gate level after logic synthesis. (2) The test length is very long [4]. (3) At-speed functional testing is not applicable.

In order to solve the above-mentioned disadvantages, some non-scan DFT methods [5-9] for RTL design circuits have been proposed. RTL design circuits consist of a data path part and a controller part. As for RTL data path circuits, disadvantage (1) is solved, because RTL DFT can absorb area and delay overhead during logic synthesis. A design based on the concept of strong testability [7] for RTL data path circuits has been proposed in order to solve disadvantages (2) and (3). A data path circuit is strongly testable [7] if and only if there exists a test plan for each hardware element M that enables the application of any test pattern to M and the observation of any response of M. 100% fault efficiency is achieved for RTL data path circuits with strong testability as each M is a small combinational circuit and M is completely controllable and observable. However, the test length for data path circuits with strong testability becomes drastically longer as the number of combinational modules and the number of gates in a combinational module increase, because testing is sequentially performed for a single combinational module in the data path circuits. To shorten the test length, we proposed a test generation method using a compacted test table and a test generation method using a compacted test plan table for data path circuits with strong testability [10]. Also, when we apply a non-scan DFT [7], we have to realize the thru function of modules in data path. We proposed the functional information so as to ease adding the thru function of non-scan DFT to operational modules using high-level synthesis technology [11]. However, it is not clear that the difference in area overhead, test length and fault efficiency between a full scan DFT and a nonscan DFT [10, 11]. In this paper, we propose a SoC test strategy based on a non-scan DFT method. Also, we evaluate our approach by comparing with a full scan DFT method. This paper is organized as follows. In section 2, a SoC test strategy based on a non-scan DFT method is proposed. In section 3, experimental results by applying the proposed DFT methods to some RTL circuits are shown. Finally, section 4 concludes this paper.

result, the quality of test patterns is improved. Also, test application time is drastically reduced because a scan shift operation is not necessary. An estimation technology of a test cost for each VCore gives test circuit area, test application time, test quality, power consumption for test, fault efficiency and so on corresponding to a DFT method. A generation technology of test architecture takes the clock speed and the test quality of each core into consideration. Then it realizes an adaptive test quality using a low cost tester. If the requirement for the test quality of a core is not so strict, it adopts a scan design as a DFT. Also, our SoC test strategy covers a scheduling for the combination of BIST (Built in self test) and external test. However, we focus on a DFT for the external test in this paper.

2.1 External test Figure 2 shows a design flow of our DFT and ATPG for the external test. NS-DFT denotes a program implementing our non-scan DFT technology for the external test. NS-ATPG denotes a program for generating a test pattern for each VCore at the gate level. First, a specification description of a hard VCore is given. Then, it is synthesized using a high-level synthesis tool. Here, we denote the RTL circuit generated by a high-level synthesis tool, a standard RTL-DFT-IF format. NS-DFT is applied to the generated RTL circuit and generates an RTL circuit with DFT. Next, a logic synthesis tool generates a logic circuit with DFT. Finally, NS-ATPG generates a test pattern for the given hard VCore.

Hard VCore High-level synthesis RTL Circuit

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DFT Library

NS-DFT RTL Circuit With DFT (Verilog-HDL)

2. SoC test strategy based on non-scan DFT The basic technology of a SoC test strategy based on a non-scan DFT method in VCDS includes (1) a DFT technology of each VCore based on a non-scan DFT method, (2) an estimation technology of a test cost for each VCore corresponding to various DFT methods, (3) a generation technology of test architecture for SoC. A non-scan DFT enables the use of at-speed test for each VCore, and raises the probability of detection for various potential faults using a stuck-at fault model. As a

Standard RTL-DFT-IF format (Verilog-HDL)

Equivalence checker

Reports

Logic synthesis

Compacted test plan table

State Traversing sequence

Test mode file

Logic Circuit with DFT (Verilog-HDL) NS-ATPG

Test pattern (WGL)

Figure 2 A flow of our DFT and ATPG

2.2 NS-DFT Figure 3 shows a flow of NS-DFT. The function and input/output of each program module is as follows. DFT Library

RTL (Verilog-HDL)

Parser

(5) All DFT (A-DFT) Function: DFT to test an entire SoC Input: Data path graph with strong testability, testable FSM, test controller, and a block netlist Output: RTL circuit with DFT written in Verilog-HDL (Figure 4 shows an circuit with A-DFT. A test controller and some multiplexers for DFT are added to an original circuit.) Test controller

Data path graph

FSM graph

D-DFT Test plan

Block netlist

Data path with strong testability

Testable FSM

Test controller

PO A-DFT

RTL with DFT (Verilog-HDL)

Test mode file

State traversing sequence

Figure 3 A flow of NS-DFT (1) Parser Function: Parsing Input: RTL circuit with standard RTL-DFT-IF format Output: Data path graph, FSM (Finite State Machine) graph, and block netlist. (2) Data path DFT (D-DFT) [7, 11] Function: DFT to test each combinational module hierarchically Input: Data path graph and DFT library (DFT library is a file including an implementation of thru function and the number of test patterns for each combinational module (operational module). See Figure 5.) Output: Data path graph with strong testability and test plan for each combinational module (3) Controller DFT (C-DFT) [12] Function: DFT to utilize combinational ATPG Input: FSM graph Output: Testable FSM and the state traversing sequence that is a sequence to transit to a state, which is necessary for test of FSM (4) Test controller DFT (T-DFT) [8, 10] Function: DFT to test combinational modules concurrently Input: Test plan and DFT library Output: Compacted test plan table and test controller

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PI

Controller with DFT

T-DFT

Compacted test plan table

TPG

PI

C-DFT

Data path with DFT

PO Figure 4 A circuit after A-DFT

2.3 DFT library DFT library is composed of an information table and RTL operational modules with thru function, shown in Figure 5. A user registers, inspects and deletes them using an entry tool, a browser, and the API (Application Programming Interface). (1) Information table The information table includes fault efficiency, test circuit area, the number of test patterns, power consumption for test, and constraints and so on for each operational module. (2) RTL operational module with thru function Corresponding to each operational module in the information table, RTL operational modules with thru function are registering. The bit width of each operational module with DFT is parameterized. DFT Library

D-DFT

Entry tool Information table A

Browser

RTL operational module with thru function (Verilog-HDL)

P I Test cost estimation tool

Figure 5 DFT library

Table 1 Characteristic of circuits Controller Data path Area #PI # PO #State #Status #Control Area #PI # PO |Bit| #Reg #Mod Area gcd 1188 0 0 5 3 7 55 32 16 16 3 8 1133 lwf 2762 0 0 5 0 8 41 32 32 16 5 8 2721 4thiir 6092 *** *** *** *** *** *** 16 16 16 12 8 6092 paulin 4555 0 0 6 0 16 51 32 32 16 7 15 4504 jwf 5522 0 0 9 0 39 83 80 80 16 14 28 5439 risc 39881 0 2 11 54 13 359 32 96 32 47 115 39522 mpeg 35722 2 0 163 0 271 989 56 128 8 241 368 34733 * “4thiir” does not have controller.

3. Experimental results Table 1 shows the characteristic of the controller part and the data path part in RTL circuits. “risc” and “mpeg” are practical circuits. The others are benchmark circuits. “Area” is the number of gates, which is calculated relatively when the value of an inverter is one. “#PI”, “#PO”, “#State”, “#Status” and “#Control” are the number of primary inputs, the number of primary outputs, the number of states, the number of status signals, and the number of control signals, respectively. Also, “|Bit|”, “#Reg”, and “#Mod” represent the bit width of signals in data path, the number of registers, (which is not equal to the number of FFs (flip-flops), and the number of combinational modules, respectively. Here, we discuss the area overhead, test length and fault efficiency. Table 2 summarizes the results for our DFT (NS-DFT) and full scan DFT. “Normal” means an original circuit before DFT. (1) Area overhead Here, we discuss the area overhead of DFT methods. We call the ratio of test area for a whole circuit area, “area overhead”. In the case of full scan DFT, the area overhead ranges from 22% to 88%. The area overhead of NS-DFT ranges from 9% to 84%. Here, we consider the area overhead from the viewpoint of circuit feature. For small sized benchmark circuits, the area overhead of NS-DFT ranges from 9% to 25%, and that of full scan DFT ranges from 22% to 88%. Also, the area overhead of NS-DFT is smaller than that of full scan DFT in all cases. In full scan designs, the test area depends on the number of FFs. In “lwf” and “paulin”, the ratio of registers to the whole circuit area is large; the consequent area overhead ranges 76% to 88%. Also, for practical circuits, “risc”, and “mpeg”, the area overhead of NS-DFT depends on the circuit characteristic. For “mpeg”, the area overhead of NS-DFT exceeds that of full scan DFT.

Proceedings of the 11 th Asian Test Symposium(ATS’02) 1081-7735/02 $17.00 © 2002 IEEE

Table 2 Experimental results for area, test length and fault efficiency gcd Normal FullScan NS-DFT lwf Normal FullScan NS-DFT 4thiir Normal FullScan NS-DFT paulin Normal FullScan NS-DFT jwf Normal FullScan NS-DFT risc Normal FullScan NS-DFT mpeg Normal FullScan NS-DFT

(area overhead) Area 1188 (30%) 1545 (25%) 1486

(reduction ratio) Test length *** 4107 (5%) 217

Fault efficiency *** 100.00% 100.00%

(area overhead) Area 2762 (76%) 4869 (14%) 3150

(reduction ratio) Test length *** 3779 (9%) 355

Fault efficiency *** 100.00% 100.00%

(area overhead) Area 6092 (22%) 7436 (9%) 6610

(reduction ratio) Test length *** 4631 (16%) 749

Fault efficiency *** 100.00% 100.00%

(area overhead) Area 4555 (88%) 8556 (18%) 5380

(reduction ratio) Test length *** 6263 (9%) 554

Fault efficiency *** 100.00% 100.00%

(area overhead) Area 5522 (59%) 8647 (16%) 6428

(reduction ratio) Test length *** 12365 (4%) 447

Fault efficiency *** 100.00% 100.00%

(area overhead) Area 39881 (26%) 50153 (22%) 48544

(reduction ratio) Test length *** 409914 (0.8%) 3149

Fault efficiency *** 99.66% 100.00%

(area overhead) Area 35722 (33%) 47374 (84%) 65563

(reduction ratio) Test length *** 268133 (27%) 73413

Fault efficiency *** 100.00% 100.00%

* “Area” is calculated relatively when the value of an inverter is one.

Table 3 Additional areas for NS-DFT gcd lwf 4thiir paulin jwf risc mpeg

ALL Controller Data path Test controller Top 298 (8%) 23 (15%) 45 (50%) 149 (27%) 81 388 (5%) 19 (9%) 33 (55%) 214 (31%) 122 518 (0%) 0 (41%) 212 (48%) 247 (11%) 59 825 (2%) 17 (36%)299 (44%) 363 (18%) 146 906 (4%) 33 (11%) 97 (46%) 417 (40%) 359 8663 (4%) 381 (44%) 3823 (46%) 3967 (6%) 492 29841 (1%) 296 (29%) 8751 (66%) 19595 (4%) 1199

Table 3 shows the details of the area overhead for NSDFT. In the table, “ALL”, “Controller”, “Data path”, “Test Controller”, and “Top” represent the additional area for a whole circuit after DFT, the additional area of controller with DFT, the additional area of data path with DFT, the area of test controller, and the area of multiplexers inserted at the top level of RTL, respectively. In NS-DFT for “risc” and “mpeg”, the ratio of area overhead of each part is as follows; controller (from 1% to 4%), data path (from 29% to 44%), test controller (from 46% to 66%), top (from 4% to 6%). That is, most of the area overhead stems from the data path and test controller. Additionally, the practical circuits are synthesized under the condition of low clock speed using a high-level synthesis tool. Therefore the chaining of combinational modules occurs between registers. Also, the chaining part has reconvergent structure. As a result, many registers and multiplexers for test need to be inserted. (2) Test length The reduction ratio of test length for NS-DFT ranges from 0.8% to 27% in comparing with full scan DFT. Assuming that the speed of test clock for NS-DFT is five times faster than that for full scan DFT, the results for “mpeg” show that the test application time is reduced about one hundred times. (3) Fault efficiency For benchmark circuits, 100% of fault efficiency is attained in both cases of NS-DFT and full scan DFT. As for “mpeg” and “risc”, NS-DFT attains 100 %, but the fault efficiency of full scan DFT for “risc” is 99.66%. The reason for its degradation is that the chaining of combinational modules makes it difficult for the ATPG tool to generate test pattern. Also, the test generation time for full scan DFT ranges from 300 times to 1300 times as that for NS-DFT.

5. Conclusion This paper proposed a SoC test strategy based on a nonscan DFT method, especially, external testing. Also, we compared our non-scan DFT with full scan DFT with relation to area overhead, test length, and fault efficiency for some benchmark circuits. The experimental results

Proceedings of the 11 th Asian Test Symposium(ATS’02) 1081-7735/02 $17.00 © 2002 IEEE

show that our non-scan DFT is advantages in terms of following issues: (1) test application time, (2) test generation time (fault efficiency). The area overhead of NS-DFT is smaller than that of full scan DFT, except for “mpeg” circuit. Future work includes: (1) reducing the area overhead of NS-DFT, (2) extending the proposed method to real RTL circuits with various widths signal, and (3) evaluating the test quality.

Acknowledgements This work was sponsored by NEDO (New Energy and Industrial Technology Development Organization) as VCDS Project (SoC advanced design technology development project). The authors would like to thank Professor Hideo Fujiwara, Professor Michiko Inoue, and Professor Satoshi Ohtake of Nara Institute of Science and Technology for their valuable discussion and comments.

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based on fixed-control testability,” Proc. IEEE/ACM Asia and South Pacific Design Automation Conf. 2000, pp.331-334, Jan. 2001. [9] I. Ghosh, A. Raghunathan, and N.K. Jha, “A design for testability for RTL circuits using control/dataflow extraction,” Proc. IEEE/ACM Int. Conf. on CAD, pp.329-336, Nov. 1996. [10] T. Hosokawa, H. Date, and M. Muraoka, “A Test Generation Method Using a Compacted Test Table and a Test Generation Method Using a compacted Test Plan Table for RTL

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Data Path Circuits”, in Proc. of VTS, pp.328-335, Monterey, April 2002. [11] H. Date, T. Hosokawa and M. Muraoka, “A Non-scan DFT Method using Functional Information of Operational Modules”, in Proc. of WRTLT, Nara, November 2001. [12] S. Ohtake, T. Masuzawa, and H. Fujiwara, “A non-scan DFT method for controllers to achieve complete fault efficiency”, in Proc. 7th Asian Test Symposium (ATS'98), pp.204-211, December 1998.