A Study of Crack Propagation in PbFree Solder Joints ... - IEEE Xplore

A Study of Crack Propagation in Pb-free Solder Joints under Drop Impact J.F.J.M.Caers(1), E.H.Wong(2,3), S.K.W. Seah(3), X. J. Zhao(1), C.S.Selvanayagam(3), W.D.van Driel(4), N. Owens(5), M.Leoni(5), L.C. Tan(5), P.L. Eu(5), Yi-Shao Lai(6), Chang-Lin Yeh(6), (1) Philips Applied Technologies, Eindhoven, The Netherlands (2) SIMTech, Singapore (3) IME, Singapore (4) NXP, Nijmegen, The Netherlands (5) Freescale, Singapore (6) Central Labs,ASE, Inc Contact: Jo Caers, [email protected], tel.: +31 4027 48920

Abstract The higher stiffness of Pb-free SAC solders makes Pb-free assemblies more sensitive to drop impact. In order to be able to optimise the drop test performance, it is necessary to have better insight into the crack propagation in the Pb-free solder joints. This study combines on-line resistance measurements of a solder joint during drop testing and high speed bend testing, failure analysis of the assembly with dye-and-pry method and with cross-sections ， and electrical FE simulation. The result is a fingerprint of the crack propagation during consecutive loading cycles. The carrier in the study is BGA’s, a critical component family for drop impact. Combinations of solder alloys and pad finishes, SnPb on OSP, SAC305 on ENIG, SAC101 on OSP and SAC101(d) on ENIG are studied regarding the failure mode and crack propagation. This study demonstrates that for the large majority of Pb-free solder joints, there is a negligible initiation period; cracks start forming at the first PCB bending cycle. The presence of large cracks, especially at both sides can increase the compliance of the joint and slow down crack growth. Even if large cracks are present, the resistance increase is less than 1 mΩ per interconnect, which is far from the 100Ω that is often taken as a failure criterion. Brittle joints as found with SAC305 on ENIG have erratic propagation rates while ductile joints are much more predictable. Therefore, the way to optimise the drop test performance of a Pb-free BGA assembly, is to prolong the crack propagation within the ductile solder material. Introduction A lot of studies[6-10] show an increased incidence of brittle interfacial fracture for Pb-free solders, eg SAC305, compared to SnPb solder, especially under impact loading. This explains why some portable products with Pb-free solder joints have a lower reliability during drop or shock impact than those devices with traditional Pb containing solder joints. However, it is still a questionmark about how to control the brittle failure to improve the drop performance of Pb-free products. Many efforts / interest have been paid in selecting Pb-free solder alloys, interposer finish to get a strong interface. But seldomly, we can find some studies about how the interconnect react to drop impact or how the crack is initiated and propogated in the Pb-free interconnect over several drops. To understand this will provide a wider capacity for optimizing the drop resistance. A R&D

978-1-4244-2231-9/08/$25.00 ©2008 IEEE

consortium project was organized by IME, together with Philips, NXP, Freescale and ASE, to study the reliability of solder joints to mechanical drop-shock. Study on the crack propogation in Pb-free solder joints under drop impact is one part of this project. Where the traditional SnPb interconnect is concerned, a fatigue crack growth along the bulk solder under a cyclic thermal loading is often the critical issue for the solder joint reliability. The failure mode, in essence, is often predictable by some standard measurement and failure analysis like cross section. However, when looking at the reliability of a Pb-free interconnect, a fatigue crack growth under drop impact is the critical issue and the crack is often related to a brittle fracture or mixed with a ductile fracture. This issue is caused by many factors and the failure mode is more complex. Therefore, the fatigue life prediction is more difficult. This study investigates the characteristics of fatigue crack growth in solder joints having different failure modes under shock and dynamic cyclic bending. The solder joints are tested with two methods, the standard drop test and a high speed cyclic bending test. The crack growth in solder joints are captured by on-line resistance measurement; crack size/shape measurement is performed using the dye-and-pry technique, and electrical resistance as a function of crack shape is determined using FE modeling. The study is an important part in building a model for predicting solder joint life under drop or shock impact. Test methods In the effort to address solder interconnect reliability under mechanical drop impact, one of the concerns of the industry is the test methods for qualifying designs/materials and for quality assurance during manufacturing [1-8]. The JEDEC standard drop test is currently used extensively for the purpose, but it is costly in terms of material set and time required to run the test. Earlier findings [1, 7-8] showed that the major cause of solder joint damage under drop impact is the differential flexing between PCB and package, rather than the inertia loading typical for shock tests. In any case, the rapid motion of the PCB during dynamic flexing is the main cause of inertial loading [6]. The JEDEC drop test can in fact be viewed as a bend test method, although the bending is induced in an indirect manner using a shock pulse. Therefore, it makes sense to explore the possibility to replace the drop test by a cyclic bending test. Current hydraulic conventional universal testers, however, are limited to frequencies of at

1166 2008 Electronic Components and Technology Conference

most 50 Hz at very low amplitudes. This is far away from the board vibration frequency up to 500Hz and the acceleration at local points of PCB exceeding 1000G’s during drop impact of a portable electronic product. Knowing that material properties are strain rate dependant, testing at 50Hz is not representative for what happens during an actual drop. In this study, a special high-speed 4-point bend tester is developed to perform displacement-controlled bend tests of board assemblies at the high flexing frequencies of drop impact (see figure 1). The cyclic frequency can be changed from 1 Hz to 300 Hz while the PCB deflection ranges from 0.5 to 5 mm. The tester delivers discrete sinusoidal pulses to the board assembly, as shown in the bottom part of figure 1. For this study, the bending frequency was controlled at 100 Hz while the PCB strain amplitude was controlled at 1800 micro strain.

shown in figure 3. With such a design, the joint stresses in any corner joint are not affected by failure at other corners. In the test packages, the solder ball diameter is 0.4mm, the pad diameter is 0.3mm, both at board and component side, the component thickness is 0.8mm. For both of the tests, a series of solder alloys are used, including Sn37Pb, Sn3.5Ag, SAC101, Ni/In-doped SAC101, SAC305 and Ni-doped SAC305. Pad finish covers ENIG and OSP. Among them, SnPb on OSP, SAC305 on ENIG, SAC101 on OSP, and SAC101(doped) on ENIG are selected to study the crack propagation. 140 mm

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Figure 3 Figure 1 Four-point high-speed bend test setup [3]. Drop testing is also done for a correlation study between the board level drop test and the board level high speed bend test in terms of performance ranking and failure mode. A halfsine pulse of 0.5ms with acceleration of 800g was used and measured at the drop table. The test is repeated to failure. 20 boards were dropped for each type of assembly. The test set up is shown in figure 2. The same test vehicle was used for drop test and the bending test enabling a consistent comparison and correlation. To assure accurate resistance measurement and minimize the random failure, a four-corner design board was applied which ensures the first failure occurring at the corner joints, as

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Online resistance and crack measurement To monitor the crack growth, a combination of experimental techniques has been used. During the drop and cyclic bending test, the contact resistance change is measured. To capture what happens during the drop or cyclic bend test, a measuring frequency of higher than 1000Hz is required. A dedicated test structure allowing a 4-wire resistance measurement of 2 interconnects is used; one is a critical corner bump, where most damage is expected, the other is a bump at a non-critical location. To realize the required high measuring resolution, a stable current source and either a 6.5digit DMM (at 1000Hz) or a 16-bit oscilloscope are used. Voltage is measured at a current level of 200mA. This is a


compromise between enough measuring resolution and Joule heating of the interconnect. To eliminate a possible temperature effect on the contact resistance measurement, the actual test starts only after the voltage is stabilized. A schematic view of the test structure and test set-up is shown in figure 4. In this figure, also the bumps that are used for the 4wire resistance measurements are indicated.

Examples of stained surfaces, with and without prebending during immersion, showing clearly the effect of prebending are given in figure 7.

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Schematics of the contact resistance measurement.

Typical examples of the resistance measurements during a drop test are shown in figure 5. During the drop, there is a momentary sharp increase in resistance occurring over 200ms, caused by crack opening due to the board flexing. Afterwards, when the board flexing has damped out, the crack tends to close again partially, leaving some residual damage. From figure 5, it can be seen that in the example shown, damage is accumulated in each cycle and starts already from the first drop.

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Effect of pre-bending.

After dye and pry, the components are removed using a shock impact from the backside of the test board as is illustrated in figure 8. This is a preferred method over the separation by bend-and-pull as it avoids deformation of the solder joint and hence the distortion of the fractured surfaces. In most cases, the main crack is at the PCB-side and the solder balls still stick to the component. To get access to the ball to component interface and reveal the possible damage at the component side, the solder balls are sheared off. Typical cracks with main crack at the PCB-side and a minor crack at the component side are shown in figure 9 and 10 (crosssection).

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At different intervals, samples are taken out and crack initiation and growth is evaluated using the dye-and-pry method. Dykem Steel Red / Steel Blue used as dye. The immersion time is 5 minutes. Then, baking is done at 150°C for 15 minutes to ensure complete evaporation of the dye solvents. To enhance the staining of the surfaces, the test boards may also be pre-bended during the immersion into the liquid as is illustrated in figure 6. In this study, pre-bending is done at a level of 1500µ-strain, which is below the strain level during the drop test.

Main crack (PCB side)

Component-side crack (after ball shear)

Figure 9 Typical crack path at PCB-side (main crack) and component side shown after dye and pry. Component

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Figure 10 Typical crack formation in drop and cyclic bend test.


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Figure 13 Resistance change vs. crack area at PCB side. Besides the cracks on the PCB side, smaller cracks often form on the component side, as is shown in figure 10. When taking both crack types into account in the electrical model, it is found that the increase in resistance due to component-side cracks is exponential in nature, just like the increases due to the PCB-side crack, see figure 14. TR = % of component-side crack to PCB-side crack

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FE electrical simulation Crack size measurements through dye-and-pry method give a clear picture about how the cracks propagate along the fracture interface. However, to repeat the measurement on many joints is tedious and costly and requires an interruption of the crack propagation process. Therefore, it is necessary to be able to describe the correlation between the resistance measurement and crack area in a more easy and uniform way. For this objective a FE electrical simulation was done: to predict the crack area based on electrical resistance measurement. Another objective of the simulation is to investigate the effect of multiple cracks at both PCB and component sides, and of the crack orientation, on the experimental measurements. In the electrical model, solder joints, Cu pads and local Cu traces are simulated based on their geometry and electrical resistivity, see figure 11. Intermetallic layers are ignored in view of their negligible thickness. Cracks are simulated as a seam, and cracks are modeled to have similar area and shape as observed in dye-and-pry tests. A specific relationship between crack length and crack area are assumed as obtained from experimental observation. The crack front is assumed to be an arc of a circle which translates and expands as the crack progresses. This geometric relation is an empirical fit to the observation from the dye-and-pry tests. As in the electrical resistance measurement, the source current is set at 200mA.

Current output 0.2A Reference potential (V = 0mV) Current Input 0.2A

Figure 11 Electrical model of solder joint and local traces.

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Figure 12 Crack areas indicated by dye staining from multiple SnPb-OSP samples subjected to partial joint failures.

When simulating the crack with the same area but with different orientation, it is found that cracks forming adjacent to the traces result in slightly higher measured voltage changes. This is shown in figure 15. Normalized resistance (%)

The crack shape is modeled based on typical progression seen in dye-and-pry tests as in figure 12. From the simulation, it is found that the resistance increases exponentially with crack area (see figure 13). For a crack area of 90%, the resistance change is only ≈ 1 mΩ. Because of the exponential increase, care must be taken in measuring and modeling the larger crack sizes.

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Figure 14 Resistance change vs. PCB-side crack area for various component-side cracks.

Figure 15 Resistance change vs. orientation of cracks


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Figure 16 Typical crack propagation patterns. Ductile failure in Sn-Pb and SAC101(doped) For Sn-Pb on Cu-OSP and Ni/In-doped SAC101 on CuOSP and on ENIG, crack growth typically is very gradual and fairly consistent. The resistance change is illustrated in figure 17 for Ni/In-doped SAC101 on ENIG. Cross-sections show that this resistance pattern is characteristic for fracture through the bulk solder.

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Results of electrical simulation and resistance measurements for several crack sizes are calibrated and validated as shown in Table 1. The difference between FE prediction and actual electrical measurement ranges from 2% to 30%, which is deemed to be acceptable.

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Fatigue Crack propagation in Solder Joints Electrical resistance measurement is used to study the crack propagation in different solder alloys. The electrical resistance change is converted into an assumed crack length based on the relationship between crack size and resistance obtained from the FE model, as described above; one major crack is assumed. A typical crack propagation pattern obtained this way is shown in figure 16. Two different regimes can be distinguished: an initial part with a stable crack, where no crack growth is observed and a second regime with a fast increasing crack length. Details in the crack grow pattern indicate cracks to open and temporarily close again during reverse bending. These details correspond to the sinusoidal bending pulses shown in figure 1. Sometimes, after an initially steep increase of the resistance, crack growth slows down. This may be due to a shift in crack mode from brittle to ductile or to an increase in compliance from crack formation.

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Figure 17 Crack propagation for ductile fracture (Ni/In-doped SAC101 on ENIG). Brittle & Mixed failure in SAC305& SAC101 SAC305 and SAC101 on Cu-OSP and ENIG tend to exhibit a brittle to a mixed ductile/brittle failure mode. For this type of failure modes, the crack growth is much more unpredictable, as is shown in figure 18 for SAC305 on ENIG.


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Cross-sections reveal that fracture is predominantly brittle in nature and occurs at the interface between the solder ball and the PCB. Very often, a mixed fracture mode is observed, and the crack path switches from bulk to interface. In figurer 18 only sample 2 shows ductile fracture. Sample 3 shows that much of the solder joint life can be spent propagating a small (ductile) crack. After about 10% crack length, the joint fails rapidly in a brittle way.

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Figure 19 Cumulative failure distributions for the cyclic bending test. Sample 3 Main crack

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Crack propagation for predominantly brittle fracture (SAC305 on ENIG).

Figure 19 shows the cumulative failure distributions for SnPb on Cu-OSP, undoped SAC101 on Cu-OSP, Ni/In-doped SAC101 on ENIG and SAC305 on ENIG. A Weibull distribution is assumed. The cumulative distributions indicate that except for the SnPb on Cu-OSP, the other material combinations have multiple failure modes, the intrinsic part, however, being comparable for all. The multiple failure modes result in a lower observed effective β. As Sn-Pb on Cu-OSP shows ductile fracture through the solder bulk, this means most likely that the intrinsic part of the curves stands for ductile failure and the lower part of the distributions stands for brittle failure or a mixed ductile/brittle failure mode. This illustrates again the importance of having failures through the bulk solder in order to have a predictable situation. If this can not be realized, major focus to improve the robustness under shock loading, should therefore be on strengthening the interface.

Conclusions An experimental procedure has been developed to study the crack propagation in Pb-free solder joints in drop and cyclic bending tests. Resistance measurements have been combined with electrical simulations and dye-and-pry staining of the fracture interface. BGA assemblies with different solder ball compositions were used and assembled on CuOSP or ENIG. For the large majority of solder joints, there is a negligible initiation period for cracks. Cracks start forming at the first drop or bending cycle. Presence of large cracks, especially at both sides, can increase the compliance of the joint and slow down crack growth. Much of the solder joint life can be spent propagating a small (ductile) crack. In a predominantly brittle fracture mode, the eventual life time under shock or cyclic bending load is determined by the point where the crack shifts from the bulk into the brittle interface. As a result, predominantly brittle failures are erratic and impossible to predict. Ductile fractures behave fairly consistent. Using resistance measurements, cracks on the component side can confuse the analysis. Cross-sections have limitations because only one plane is seen and the actual fracture is 3-dimensional. Future work will explore the use of fracture surfaces to better understand crack growth.


Acknowledgements The authors would like to acknowledge the contributions of Ranjan Rajoo of IME and advice provided by D. Frear of Freescale. References 1. Wong E.H. et al, “Drop Impact: Fundamentals and impact characterisation of solder joints”, Proc. 55th ECTC, Lake Buena Vista, Fl, May 31-June 3, 2005, pp1202-12 09. 2. Owens N. et al, “Second Level interconnect Mechanical Robustness”, Proc. 4th Int. Conf. and Exhibition on Device Packaging (IMAPS), Scottdale, Arizona, March 17-20. 3. Wong E.H. et al, “Recent Advances in Drop-Impact Reliability”, Proc. EuroSimE 2008, Freiburg, Germany, 20-23 April. 4. JEDEC Standard JESD22-B111 (2003), “Board level drop test method of components for handheld electronic products”. 5. Newman K. et al, “BGA brittle fracture – alternative solder joint integrity test methods”, Proc. 55th ECTC, Lake Buena Vista, Fl, May 31-June 3, 2005, pp11941201. 6. Seah S.K.W. et al, “High-Speed Bend Test Method and Failure Prediction for Drop Impact Reliability”, Proc. 56th ECTC, San Diego, CA, May 30-June 3, 2006, pp10031007. 7. Wong E.H. et al, “Drop Impact Test – Mechanics and Physics of Failure”, Proc. 4th Electronic Packaging Technology Conference, 2002, pp. 327-333. 8. Seah S.K.W., et al, “Understanding and Testing for Drop Impact Failure,” Proc ASME InterPACK ’05, 2005, IPACK2005-73047, pp 1-6. 9. Date M., et al, “Impact reliability of solder joints”, Proc. 54 th ECTC Conf., 2004, Las Vegas, NV, June 1-4 2004, pp668-674. 10. Masazumi Amagai et al “High drop test reliability: leadfree solders”, Proc. 54th ECTC Conf., 2004, Las Vegas, NV, June 1-4, pp1304-1309.
