Venable's K-factor method is a systematic procedure that allows designers to ... slightly different algorithm to Venable's original version is proposed, tailored to ...
A Systematic Approach to Frequency Compensation of the Voltage Loop in Boost PFC Pre- regulators. Claudio Adragna, STMicroelectronics, Italy
Abstract Venable’s K-factor method is a systematic procedure that allows designers to compensate the error amplifier in feedback loops of control systems to achieve the desired bandwidth and phase margin. This approach is of general use and can be applied to PFC pre-regulators as well. In this paper, a slightly different algorithm to Venable’s original version is proposed, tailored to the particular characteristics of PFC pre-regulators.
1. Introduction Venable’s K-factor method [1] defines an algorithm allowing power supply designers to determine the frequency compensation components needed to achieve the desired control goal. Starting from the control-to-output transfer function of the converter, an appropriate structure for the output-to-control transfer function is selected and then gain and pole/zero locations are chosen so that the gain of the resulting open-loop transfer function crosses over the 0 dB axis at a given frequency, while its phase lag at that frequency is such that the specified phase margin is obtained. In other words, in Venable’s method, the control goal is expressed in terms of dynamic accuracy, response speed and degree of stability. The reader will certainly recall that the open-loop crossover frequency is related to the closed-loop settling time of the step-change response, while phase margin affects both the settling time and the damping ratio of the response. When one applies K-factor method to PFC preregulators, using phase margin as part of the control goal makes definitely sense. System stability and the tendency to be more or less prone to ringing are of primary importance. However, the characteristics of the PFC preregulator render crossover frequency goal of little use. It does not provide much insight concerning the trade-off between good pre-regulator performance (low total harmonic distortion of the input current and high power factor) and acceptable dynamic behavior. A more appropriate approach is suggested in [2], where the level of harmonic distortion introduced by the compensated error amplifier in the input current is taken into consideration. In the following sections the control goal will be formulated in a more convenient way following
the approach given in [2], and Venable’s K-factor method will be adapted accordingly. The modified algorithm will be entirely developed and lead to the following result: PFC stages with input feed-forward can be compensated so that they exhibit a preset phase margin and a preset distortion level for any operating condition; those without input feed forward can be compensated so that their phase margin is kept above a minimum value for any operating condition, with a distortion not exceeding a maximum preset level.
2. Input current distortion and voltage loop compensation There are two major sources of distortion in the input current of a PFC pre-regulator. The first is the so-called “crossover distortion”, which appears as a small plateau next to the zero-crossings of the line voltage. Essentially, it stems from the power stage’s inability to transfer energy effectively in that zone and is unrelated to voltage loop compensation. The second contributor is the distortion of the current reference generated by the control IC, which equally impacts the input current from the mains. Unlike the first, this second contributor is heavily dependent on the way the voltage loop is compensated. The current reference is obtained by multiplying the properly scaled-down rectified line voltage with the error signal (Vc) of the voltage control loop (the output of the error amplifier, E/A, of the control IC). With a perfectly sinusoidal line voltage, an undistorted current reference can be obtained if, and only if, the error signal is a dc voltage. Any ac component would introduce higher order harmonic components. Actually, the output voltage of a PFC stage has a nearly sinusoidal ripple at the second harmonic
of the line frequency (2·fL) superimposed on the dc regulated value Vo; its peak amplitude ∆VO is essentially related to the reactance of the output capacitor at f = 2·fL: Po , (1) ∆Vo = 4 π fL Vo Co where Po is the output power and Co the output capacitance. The error amplifier has a non-zero gain (H2f) at that frequency, and therefore, a voltage ripple with peak amplitude equal to ∆Vc = H 2f ∆Vo (2) will appear at the E/A output, superimposed on the dc value Vc. Vc depends on the operating conditions (input voltage and output current), as well as the control technique and the characteristics of the control IC. It is possible to show that the ripple ∆Vc contributes an additional component at the fundamental frequency and a third-harmonic component in the current reference, both with peak amplitude equal to ∆Vc / 2., The third-harmonic distortion of the current reference and input current is given, with good approximation, by: 1 ∆Vc , (3) D3 ≈ 2 Vc − Vc 0 where Vc0 is the “zero-power” level of the control voltage. Table 1 shows the “effective control voltage” Vc-Vc0 for some commercially available PFC controllers.
conditions can be taken from Table 1 and the peak output voltage ripple derived from (1). Given the maximum specified level of thirdharmonic distortion D3, with (3) it is possible to find the maximum output ripple ∆Vc of the E/A and, from (2), the E/A gain at f = 2·fL, H2f: Vc − Vc 0 ∆Vc H 2f = = 2 D3 . (4) ∆Vo ∆Vo
3. PFC small-signal model Once a constraint on the E/A gain has been determined, voltage loop stability and dynamic performance need to be addressed. To do so, as in any closed-loop control problem, the starting point is the transfer function of what in control theory terminology is called “the plant”, in the present case the small-signal control-to-output transfer function of the PFC pre-regulator. The discussion will be focused on pre-regulators powering a downstream dc-dc converter. It is well known [3] that a regulated dc-dc converter represents a constant power load to the PFC pre-regulator and that, as shown in Fig. 1, the small-signal model of such a system is given by a controlled current generator which drives the output capacitor Co. ^ Io
Part #
Control method
Feedfwd
Vc - Vc0
L6561 L6562
Transition Mode
No
2 Pi Rs KM KP Vi2
L6563
Transition Mode
Yes
L4981
Fixed Freq. Avg. CM
Yes
4
KP Rs Pi KM
KFF Rs Pi K M K P Ri
NOTES: KM : multiplier gain (refer to IC datasheet) KP: multiplier input divider ratio (L656x); reciprocal of multiplier input bias resistor (L4981) KFF: feed-forward circuit gain (L4981) Rs: current sense resistor Ri: current gain programming resistor (L4981) Pi: input power to the PFC stage (=Po/η, η = efficiency) Vi: line voltage (rms value)
Table 1. Effective control voltage in different control ICs. Once the power stage has been defined, the control voltage Vc under assigned operating
Co
^ Vo
Fig. 1 Small-signal model of a PFC stage with a constant-power load (dc-dc converter).
The generator îo is controlled by the small-signal ac control voltage vc. This system behaves as a pure integrator and the resulting control-to-output transfer function is: vˆ o G = G( jω) = 0 , (5) vˆ c jω where the unity gain factor G0 is given by Po , (6) G0 = Vo ( Vc − Vc 0 ) C 0 regardless of the control method and the characteristics of the control IC [3]. The transfer function then presents just one pole at the origin. As illustrated in Fig. 2, the gain falls at -1 slope (-20 dB/decade) and the phase shift is -90º (i.e. +90º phase lag) at all frequencies.
Observing the values of Vc-Vc0 in Table 1 and equation (6), G0 is essentially independent of the load. Additionally, with input voltage feed-forward it does not depend on the line voltage either. Without input voltage feed-forward, rather, G0 is proportional to Vi2. G( j ω )
100
w FFWD
dB
50 0
w/o FFWD min. to max. line
50 100
G( j ω )
0.1
1
10 f
100
1 .10
3
89
underdamped the system will be (faster rise and settling times but with larger overshoots and ringing). A well-known rule of thumb in servo systems suggests 45º as the optimum phase margin. This ensures fast transient response with an acceptable level of ringing. In SMPS it is not uncommon to specify higher phase margins (even 75º or more) to account for very large spreads in line, load and temperature changes as well as manufacturing tolerances, or to fulfill special requirements. For example, to achieve a flat closed-loop frequency response and minimize peaking of the output impedance, which could result in poor rejection of periodic disturbances, it is necessary to have Φm ≥ ≈66º. To achieve a critically damped step response it should be Φm > ≈76º. 0
H( jω)
fB
90
dB
deg
20 40
fZ =
60 0.1
1
10 f
100
1 .10
3
Fig. 2. Bode plots of the control-to-output transfer function G(jω) (eq. 5).
In a typical wide-range mains application there is a 3:1 ratio between the maximum and the minimum line voltage. This means that without input voltage feed-forward G0 is 9 times (≈19 dB) higher at maximum line than at minimum line.
4. Phase margin and K-factor As previously stated, the priorities in designing a control loop are its closed-loop stability and its dynamic behavior. Phase margin plays a key role in both of these aspects. The characteristics of a closed-loop system can be inferred from its open-loop properties. Stability, in particular, is related to the so-called “phase margin” (Φm), defined as the difference between 180º and the actual phase lag at the frequency where the open-loop gain is unity. Phase margin, however, is also related to the dynamic behavior of the closed-loop controlled system. Qualitatively, it is possible to state that the higher the phase margin, the more overdamped the system will be (longer rise and settling times and smaller overshoots); conversely, the lower the phase margin, the more
80
H( jω)
deg
91
0.1
1
fB K
fP = KfB
10 f
100
1 .10
3
100
1 .10
3
0
50
-90 100
ΦB
0.1
1
10 f
Fig. 3. Bode plots of a Type 2 amplifier’s transfer function H(jω) (eq. 7).
As with many power conversion systems, in PFC pre-regulators, additional E/A gain requirements arise from the need to ensure both good line and load regulation (which requires maximizing the low frequency gain) and switching frequency noise rejection (which requires minimizing the high frequency gain). In PFC pre-regulators, as shown in Section 2, a limit on the gain at the second harmonic of the line frequency ensures that the input current does not exceed a specified distortion level. All of these requirements can be fulfilled by what in Venable’s approach is called a Type 2 amplifier.
Its transfer function H(jω) includes one pole at the origin and a zero-pole pair: ω 1+ j H0 2 π fZ . (7) H( jω) = ω jω 1+ j 2 π fP Its Bode plots and circuit implementation are shown in Fig. 3 and Fig. 4 respectively. CFP RFS Vo
R1
CFS Vc
R2
VREF
+
Fig. 4. Schematic diagram of a Type 2 amplifier.
The relations between the component values in Fig. 4 and the parameters of (7) are listed below: fZ 1 1 C FP = fP H 0 R1 fP − f z C FP . (8) C FS = fZ 1 1 R FS = 2π f C Z FS The zero-pole pair creates a region of frequencies where the gain flattens and the phase lag is reduced. The maximum phase lag reduction ΦB, called “phase boost”, depends on the zero-pole frequency spread K2 = fP/fZ and occurs at the frequency:
fB =
f Z fP . (9)
The quantity: K=
fP f Z
(10)
is the so-called K-factor and is related to the phase boost ΦB: 1 Φ B = tan −1 (K ) − tan −1 , (11) K which, solved for K, provides the following relationship: 1 + sin Φ B K= . (12) cos Φ B Note that the phase shift is symmetrical to fB, which means that for any positive real number λ the following equality holds true: H( j 2πfB / λ ) =
H( j λ 2πfB ) . (13)
5. Calculation method In Venable’s original approach, fB coincides with the crossover frequency of |F(jω)| = |G(jω)|·|H(jω)| fc. Zero and pole are placed symmetrically around it at fB/K and at K·fB respectively, with K derived from (12) to achieve the phase boost ΦB necessary for the specified phase margin. Unlike the original formulation, in this context the condition fB = fc is replaced by the equivalent constraint (4) on the E/A gain at f = 2·fL. The second harmonic of the line frequency 2·fL is typically 3-4 times fP and much larger than fZ. Thereby, starting from (7) and taking (10) into account, with good approximation we have: H0 H 2f = H( j 2π 2fL ) ≈ K 2 , (14) 4 π fL which will be solved for the unity gain factor H0: H H 0 = 4 π fL 2f . (15). K2 In this equality, H2f is calculated from (4) but K still needs to be found. To calculate K, it is necessary to treat the cases of PFC pre-regulators with and without input feed-forward separately. For the derivations that follow it is useful to rewrite (7) in terms of fB and K: ω 1+ j K H0 2 π fB . (16) H( jω) = ω jω 1+ j 2 π fB K
5.1. Systems with feed-forward In systems with feed-forward the unity gain factor of the control-to-output transfer function G0 is a constant. Since the pre-regulator’s operating conditions do not affect the voltage loop, a specific “design setpoint” is not needed and fB can be selected to be the open-loop crossover frequency as in Venable’s original approach. In order for fB to be the crossover frequency of the open-loop gain |F(jω)| = |G(jω)|·|H(jω)|, the following condition must be met: G0 H( j2πfB ) = 1 , (17) 2π fB which, combined with (16), becomes: G 0 H0 K = 1. (18) (2π fB )2 This equation can be solved for fB ( = fc): 1 fB = G 0 H 0 K ; (19) 2π subsequently, fZ and fB are determined by dividing and multiplying fB by K, respectively:
)
]
5.2 Systems without feed-forward In systems without feed-forward the unity gain factor of the control-to-output transfer function G0 is proportional to Vi2. The pre-regulator’s operating conditions will affect the voltage loop’s characteristics considerably and the algorithm given in the previous section would achieve the specified third-harmonic distortion level and phase margin at a specific line voltage only. Here a different approach is proposed that allows the design of the voltage loop such that the thirdharmonic distortion level will always be lower than a specified value and the phase margin always higher than a specified value. If (Vimin, Vimax) is the line voltage range, it is convenient to consider the quantity Λ as: Vi Λ = max . (22) Vi min As stated in section 3, the unity gain factor G0 of (5) will change with Vi2. If G0 = G0x at Vi = Vimax, it will be G0 = G0x/Λ2 at Vi = Vimin. This will affect the open-loop crossover frequency: its value will be in a range (fcmin, fcmax) that will clearly depend on Λ and on how H(jω) is designed. We define: fc α 2 = max . (23) fc min The algorithm is based on the key idea of placing the frequency fB at the geometric mean of what the resulting (fcmin, fcmax) range will be. Conse-
fc max =
1 1 + α 2K 2 G 0 x H0K . (27) 2π α2 + K2
100
F( jω)
@ Max. Line 0
dB
[(
Φm = 180o − 90o − ΦB + 90o = ΦB ; (21) K will then be calculated from (12) with ΦB = Φm. To summarize, the design algorithm can be outlined in seven steps starting from the following data: fL, Vo, Po, η, KM, Vc0, KP, Rs, Co. 1) Calculate the output voltage ripple from (1) and the effective control voltage with the aid of Table 1; use full load conditions. 2) Calculate the E/A gain H2f from the specified third-harmonic distortion level D3 using (4). 3) Calculate G0 from (6). 4) Substitute the specified phase margin Φm in ΦB in (12) and calculate K. 5) Calculate H0 from (15). 6) Calculate fZ and fP from (20). 7) Determine the component values of Fig. 4 from (8). R1 can be either selected arbitrarily or determined based on other requirements.
quently, the phase shift and the resulting phase margin will have the same minimum value at fcmin and fcmax by virtue of (13). Additionally, from (23): f fc min = B ; fc max = α fB . (24) α This concept is illustrated in Fig. 5. Starting from (16) and (24), it is possible to write the expression H(j2πfcmax) as follows: H 0 1 + j αK . (25) H( j2πfc max ) = α j 2παfB 1+ j K In order for fcmax to be the crossover frequency at Vi = Vimax, the following condition must be met: G0x H( j2πfc max ) = 1 . (26) 2π fc max Considering (25) and (24), equation (26) solved for fcmax, provides:
@ Min. Line
100
200
120
0.1
1
fB/α = fcmin
10 f
fB
100
3
1 .10
αfB = fcmax
F ( j ω)
140 deg
1 G 0 H0 K fP = G 0 H0 K . (20) 2π K 2π Finally, to find K, note that as the transfer function (5) features a fixed 90º phase lag, the phase boost ΦB equals the phase margin Φm. In fact, being fB the crossover frequency, by definition: fZ =
Φm
160
180
0.1
1
10 f
100
3
1 .10
Fig. 5. fB placed symmetrically to (fcmin, fcmax) ensures the same Φm at Vi=Vimin, Vi=Vimax.
Using a similar method it is possible to find fcmin: 1 1 α2 + K2 G 0 x H0K . (28) 2π Λ 1 + α 2K 2 Finally, dividing (27) by (28) and by virtue of (23): fc min =
α2 = Λ
1 + α 2K 2 α2 + K2
. (29)
Similar to the previous case, K will be derived from the condition on the phase shift necessary to achieve the specified phase margin Φm. In this case, however, the concept expressed in (21) has to be slightly modified: Φm will be equal to the phase lag reduction at f = fcmax (which equals that at f = fcmin, by assumption). Then, from (25): α Φ m = tan −1(α K ) − tan −1 . (30) K This equation, solved for K, yields: K=
) [tan (Φ )(1 + α )]
(
tan (Φm ) 1 + α 2 +
2
m
2
+ 4α 2
2α
. (31)
Equations (29) and (31) must be solved simultaneously to find the value of K that provides the same phase margin Φm at both f = fcmax and f = fcmin, with fcmax/fcmin = α2. The analytic solution is difficult to find and it is preferable to use either calculation software or a numerical method. The solution is presented in Table 2, which shows the values of α and K corresponding to some typical values that can be specified for Φm and Λ (Λ = 1.5 is for single mains, Λ = 3 for widerange mains applications). Λ = 1.5
Φm [º]
α
K
Λ=3 ΦB [º]
α
K
ΦB [º]
30
1.311 1.764
30.9
2.115 1.995
36.8
35
1.330 1.966
36.1
2.206 2.297
43.0
40
1.350 2.207
41.3
2.302 2.671
48.9
45
1.370 2.500
46.4
2.403 3.138
54.6
50
1.391 2.864
51.5
2.505 3.729
60.0
55
1.412 3.328
56.6
2.605 4.491
64.9
60
1.432 3.943
61.5
2.699 5.499
69.4
Table 2. Numerical solution of system (29) & (31).
Table 2 shows also the phase boost ΦB, which is the maximum phase margin that will be achieved when the input voltage is such that fc = fB. Frequency fB can be easily obtained by either dividing (27) by α or multiplying (28) by α. A simpler expression for fB can be obtained by multiplying (27) by (28) and recalling that it is the geometric mean of fcmin and fcmax; the result is: 1 G 0 x H0 K . (32) 2π Λ The locations of fZ and fB can be found by dividing and multiplying fB by K, respectively: fB =
fZ =
1 2π
G 0 x H0 KΛ
fP =
K 2π
G 0 x H0 K . Λ
(33)
In the above equations, H0 will be computed from (15). Since the value G0x of G0 at maximum line voltage Vimax has been used, H2f will be determined evaluating (4) at maximum line voltage. The design algorithm can be outlined again in seven steps, if the following data are available: fL, Vimin, Vimax, Vo, Po, η, KM, Vc0, KP, Rs, Co. 1) Calculate the output voltage ripple from (1) and the effective control voltage with the aid of Table 1 at Vi = Vimax and full load. 2) Calculate the E/A gain H2f from the specified third-harmonic distortion level D3 using (4). 3) Calculate G0 = G0x from (6). 4) Calculate the ratio Λ = Vimax/Vimin, substitute the specified Φm in (31) and solve the system (29), (31); use Table 2 if possible. 5) Calculate H0 from (15). 6) Calculate fZ and fP from (33). 7) Determine the component values of Fig. 4 from (8). R1 can be either selected arbitrarily or determined based on other requirements.
6. Conclusions The control goal of PFC pre-regulators has been formulated in terms of maximum third-harmonic distortion level and phase margin. A modified version of Venable’s original K-factor method, where crossover frequency is not previously specified, has been used to define the error frequency compensation of the amplifier. The algorithm has been derived considering two separate cases: PFC stages with and without input voltage feed-forward. In the former case, compensation is done such that the system exhibits a specified phase margin and a specified distortion level for any operating condition. In the latter case it is done so that the system exhibits a phase margin equal to or larger than a specified value, with a distortion level equal to or less than a specified level for any operating condition. In both cases a step-by-step algorithm has been provided.
7. References [1] D.H. Venable, “Optimum Feedback Amplifier Design for Control Systems”, Technical Paper #3, www.venable.biz [2] L. Dixon, “Optimizing the Design of a High Power Factor Switching Preregulator”, SLUP093, SEM700 [3] R. W. Erickson, D. Maksimović, “Fundamentals of Power Electronics”, 2nd Edition, 2001, ISBN 0-7923-7270-0
