A transitive closure based algorithm for test ... - Computer Science

A TRANSITIVE CLOSURE BASED ALGORITHM FOR TEST GENERATION Srimat T.Chakradhar NEC Research Institute,Princeton,NJ 08540 Vishwani D. Agrawal AT&T Bell Laboratories, Murray Hill, NJ 07974

ABSTRACT -We present a transitive closure (TC) based test generation algorithm. A test is obtained by determining signal values that satisfy a Boolean expression constructed from the circuit netlist and the fault. The algorithm is a sequence of two main steps that are repeatedly executed: TC computation and decisionmaking. To compute the TC of the circuit, we construct an imp& cation graph whose vertices are labeled as the true and false states of all signals. A directed edge (2, y) in this graph represents the controlling influence of the true state of signal z on the true state of signal that are connected through a wire or a gate. Since the implication graph only includes pairwise (or binary) relations, it is a partial representation of the netlist. The TC of the implication graph contains pairwfse logical relationships among all signals. When signal relationships describing fault activation and path sensitizationare included, TC determines signal fixationsand logical contradictions that directly identify many redundancies. Sensitization of physical and logical dominators, unique path sensitization, static and dynamic learning and other techniques that are useful in determining necessary signal assignmentsare hpllclt in the process. If signals thus determined satisfy the Boolean formula, we have a test. Otherwise, we use the decision-makingstep, fix an unassigned signal, and update the TC to find further logical consequences.

In spite of making extensive use of the circuit structure and function, most algorithms have several shortcomings. First, they do not guarantee the identification of all logical consequences of a partial set of signal assignments. In other words, local conditionsare easier to identify than the globalones. It is, however, desirable to identify all such consequences so that a branch-and-bound method can effectively avoid signal assignments that will not lead to a test vector. This may also result in an earlier detection of redundant faults. Second,they do not establish the complexity of determiningthe logicalconsequences and it is unclear if it is at all possible to determine all the consequences using reasonable amount of resources. Third, these techniques may not be easily parallelizable. We suggested the use of TC in a previous paper [3]. In the present work, we give a completetest generation algorithmentirely based on TC. The TC of the digital circuit is computed from the implication graph whose vertices are the true and complemented states of the signals. A directed edge (X , y) in this graph represents the controllinginfluence of the true state signal 2 on the false state of signal y. The variables z and y are associated with the same gate or signal net in the circuit. Since the implication graph includes only pairwise (or binary) relations, it is a partial representation of the netlist. The TC of the implication graph (IG) contains pairwise logical relationships among all signal-pairs. When signal relationships describing fault activation and path sensitization are included, TC determines signal fixations and logical contradictionsthat directly identify many redundancies. If signals thus determined satisfy the Boolean formula, we have a test. Otherwise, we enter the decision-making phase, fix an unassigned signal, and update the TC to determineall logical consequences of this decision. The TC computation is similar to matrix multiplication and, hence, easily parallelizable. Parallel computation of TC has been extensively studied and even constant-time algorithms have been proposed [141.

1. INTRODUCTION Some of the best known algorithmsfor test generation published to date use various types of analyses to speed up the basic branch-and-bound search process. For example, in the FAN algorithm, Fujiwara and Shimono [6] use multiple backtrace to quickly discover any possible conflicts. In the TOPS algorithm [9], Kirkland and Mercer rely on prior identification of dominators. In SOCRATES [13], Schulz et a1 employ static and dynamic learning largely based on local simulation. More recently, in the EST algorithm [7],Giraldi and Bushnell store groups of signal states for future use. Rajski and Cox use reduction lists to quickly determine necessary assignments [111. These algorithms solve two main problems: (1) they deter- 2. TRANSITIVE CLOSURE mine logicalconsequences of apartial set of signalassignments Given a directed graph G = (V,E) with vertex set V = and (2) they determine the order in which decisions on fixing {zl,. ..,z,,), and edge set E, we wish to find out whether there signals should be made. is a path in G from x i to zj for all Vertex pairs Z i , z j E V. The transitive closure (TC) [5] of G is defined as the graph Permission to copy without fee all or part of this material is granted provided that the copies are not made or distributed for direct commercial G*= (V,E*),whereE*= {(zi,z,):thereisapathfromveradvantage, the ACM copyright notice and the title of the publication and tex z i to vertex z j in G}. its date appear, and notice is given that copying is by permission of the Computing the TC is an important step in many parallel alAssociation for Computing Machinery. To copy otherwise, or to republish, requires a fee and/or specific permission. gorithms related to directed graphs [lo]. An important appli28th ACM/IEEE Design Automation Conference@

'1991ACM 0-89791-395-7/91/0006/0353 $1.50

Paper 22.3 353

cation of TC is in deriving all logical conclusions implied by a set of binary relations. It has many other applications. Finding the TC of a graph G having n vertices requires O(n 3 ) operations in the worst case [5]. This complexity could be reduced to O(n2.49) by exploiting the equivalence between matrix multiplicationand TC and using fast matrix multiplication methods. An alternative method for deriving all logical conclusions in linear expected-time complexity has also been proposed [8]. There are efficient algorithms for computing the TC of sparse graphs [51. The computation of TC can easily be accelerated through parallel processing since it belongs to class NC,a hierarchy of problems solvable by deterministic algorithms that operate in polylog time using a polynomial-bounded number of processors. If A is the adjacency-matrix of graph G, the TC of G can be obtained by squaring the adjacency matrix log, n times, where n is the number of vertices in graph G. It is known [51 that n x n matrix multiplication can be performed in O(log, n ) time using ~ ( n , . ~processors. ') Thus, transitive closure can be computed in polylog time using the same number of processors. If fewer processors are available, it is still possible to design an efficient parallel algorithm. Recently, a consfanttime algorithm has been proposed for computing TC on a processor array with reconfigurable bus system [141.

false function for a digital circuit is the logical OR of the false functions for all gates. It is convenient to represent the binary relations as a directed graph, also called an implication graph [2]. This graph for the NAND gate, as shown in Figure 2, contains vertices

FIGURE2: IG for NAND gate.

for true and false states of variables. Thus, the vertex set is { a , b, C , E, 6, E}. Equation ii E = 0 is expressible as binary relations ii +- c and -d e-a that are represented as arcs (ii,c) and (z, a), respectively. Similarly, 6 F = 0 adds the arcs (6, c) and (F,b) to the IG. The TC of this IG is shown by its adjacency matrix in Figure 3. It can be determined using standard grapha i i a 1 0 i i O l -bb O0 0O c 0 0 F l O

3. CIRCUIT REPRESENTATION We represent the digital circuit as a set of binary and ternary relations [4]. As an example, consider the NAND gate shown it is easy to see that the equation in Figure 1. Since c =

a,

FNAND=

@

c 0 l 0 l 1 0

F 0 0 0 O 0 1

FIGURE3: TC of the NAND gate.

theoretic techniques [5]. Incidentally, in this case, the IG also happens to be its own TC.

b FIGURE

b 6 0 0 O O 1 . 0 O l 0 0 1 0

4. A TEST GENERATION ALGORITHM

1: A NAND gate.

We illustrate our method by an example. Consider the circuit 3 = 0 is satisfied only by those values of a, b shown in Figure 4. We will derive a test for a s-a-0 fault on

and c that satisfy the NAND gate function. Here, @ denotes the signal C . logical exclusive-OR operation. We will refer to FNANDas the Booleanfalse function. An analogous Boolean truthfunction can also be used [4]. Using Boolean algebra, we can rewrite F N ~ N as D follows:

-

FNAND= i i Z ' + bE'+abc

(1)

where + denotes the logical OR operation. A similar formulation is possible for representing the NAND gate as an energy function where a, b and c were treated as arithmetic variables [2].The function FNANDassumes the value 0 only when all the three terms in Equation 1simultaneouslybecome 0. The term E E assumes the value 0 under any one of the following conditions: (1) a = 1, (2) ii = 1 and c = 1, (3) c = 1 or (4) F = 1 and a = 1. Conditions 1 and 2 are equivalent to the binary relation E +- C , where +- denotes logical implication. Conditions 3 and 4 are equivalent to the binary relation F +- a. The term 6 F similarly results in the binary relations 6 +- c and F +- b. The term abc does not produce any binary relations. However, if any one of the signals assumes a known value, this term will reduce to a binary relationship. A similar analysis can be performed for all other Boolean gates. The Paper 22.3

354

FIGURE 4: An example circuit.

First, we derive two types of constraints to be represented in the IG: (1) Functional constraints that depend upon the function of gates used in the circuit. (2) Structural constraints that depend on the specific interconnection topology of gates and are independent of the gate types used in the circuit. Functional constraints: Signals that lie on a path from the

fault site to a primary output may assume different values in the fault-free and faulty circuits. Therefore, additional binary variables are assigned to these signals. In our example, signals c and d lie on the path from the fault site to the primary output and we assign two binary variables C' and d', respectively. Conceptually, this can be visualized as construction of a faulty circuit copy, as shown in Figure 5. The Boolean false

c'n d'

3. Make a choice on an unassigned decision variable. This may cause some of the ternary relations to become binary relations. 4. Include the new binary relations in the TC and observe

any contradictions,identifications and fixations. If there is a contradiction, we backtrack to Step 3 and make an alternative choice. If the signal assignments satisfy the false function,we have a test. Otherwise,ternary relations that have been reduced to binary relations due to current set of signal assignments are added to the TC and we go to Step 2.

FIGURE5 : Modified circuit for fault on c.

function for the modified circuit is given by the logical OR of the false functions for the gates C , d and d' (we address a gate by the name of its output signal). Furthermore, signals c and C' are constrained to assume the logic values 1 and 0, respectively. All the functional constraints can be determined from the netlist of the circuit in time complexity that is linear in the number of signals. Structural constraints: We assign a binary variable, called the path variable, S+ to every signal x that lies on a path from the fault site to the primary output. This variable assumes the logic value 1 only when the fault on x is observable at the primary output. In our example, signals c and d are assigned the binary variables se and Sd. There are two types of structural constraints. Both can be derived from the netlist of the circuit in time complexity that is linear in the number of signals, First, an input fault on a gate is observable only if the gate outputfault is observable. Note that the converse need not be true. In our example, if S~ = 1, then Sd must assume the value 1. This constraint is expressed as follows: se & = 0. For a stem fault to be observable, the fault must propagate through one or more of the branches. This case is not applicable in the present example. Second, if the path variable associated with signal2 is true, then signal 3: must assume different values in the fault-freeand faulty circuits. If we denote the faulty circuit value as x', this constraint is expressed as follows: S + ( X X ' + FT') = 0. Notice that this conditioncannot be expressed as binary relations. For the fault to be observable, the path variables associated with the fault site and the primary output are constrained to be 1. Therefore, in our example, se = Sd = 1. In summary, thefunctionalconstraintsare: 7iE+6E+abc = 0, -b d + E ' ; i + b c d = O a n d 6 ~ + ~ ~ + b c ' d f = Thestructural 0. Constraints are: aC& = Sc(cc' + Zi?) = sd(dd' + 22') = 0. The logical OR of the functional and structural constraints is the Boolean false function for the circuit with fault. Test generation proceeds as follows: 1. Derive functionaland structural constraints for the fault.

2. Determine the TC of constraintsexpressibleas binary relations and identify contradictions,identifications and fixations (derivation of logical conclusions from the TC is described later). If a contradiction is detected, the fault is redundant. If signal values, thus determined, satisfy the false function, we have a test. Otherwise, a partial set of signal values determined thus far may reduce some of the ternary relations to binary relations. We include these relations in the TC and recompute fixations and contradictions. We continue this process until no ternary relation reduces to a binary relation.

Since we are deriving a test for the s-a-0 fault on signal C , = 1, C' = 0, se = 8 d = 1 and our constraint set reduces to: a b = O , x z + d b = O,z'+6z' = Oanddd'+2B = 0. All c

the terms can be expressed as binary relations. Let R denote the set of these binary relations. The IG is shown in Figure 6. It contains vertices for variables and their complements. Here,

R G W6: IG for circuit in Figure 5 .

the vertex set is {a,b,d,d',ii,6,2,2'}. The constraint ab = 0 is expressible as a pair of binary relations a s- 6 and b j ii that are represented as arcs (U,Z) and (b, Z), respectively. Arcs correspondingto the other terms are similarly derived. The TC of the IG is shown in Figure7. This can becomputed using standard graph-theoretic techniques [5]. The following a i b 6 d d d' d

-

a 7 i l l i 0 1 O l 0 1 O l O l 0 1 ' 0 1 F I G W 7:

b z d l l 0 0 l O 1 1 l l l O 1 0 1 1

' ; l 0 O 1 l O 0 1

i d ' l l 0 0 l l 1 1 l l l l 1 1 1 1

F l 0 0 1 1 O 0 1

TC of IG in Figure 6.

types of logical conclusions are implied by the relations in R and they can all be determined from the TC as follows: 1. Contradiction: A variable x must simultaneously assume 0 and 1 values when the TC consists of both arcs ( Z , Z ) and (57,~).If this situation occurs before the search process begins or after the search space has been implicitly exhausted, the fault is redundant. If a contradiction occurs during the search process, we must backtrack to the previous choice.

2. Idenfifrcufion:Certain pairs of literals must assume the

same value if the TC consists of the arcs (2,y) and (y ,Z), Paper 22.3 355

3. Fixation: A variable z can be fixed to the value 0 if the TC and justification will result in a = b = 1. This is implicitly consists of the arc (2,571 but not the arc ( 5 7 , ~ ) .Similarly, determined in the TC method: if the TC consists of the arc (E, Z) but not (&E), variable 1. Include the relation d = 0 into the IG of Figure 9 by adding zcanbefixedatl. the arc (d,a), The updated IG is shown in Figure 11. The Tc in Figure the arc (a,E) and, therefore, 2. Construct the TC of the implication graph. The a = 0. Similarly, b = d' = 1 and d = 0. Since all primary adjacency matrix of the updatedTC is shown inFigure 12. input signals have been determined, we do not need the search We can directly derive the updated transitiveclosure from phase. The vector = 0, b = 1 is a test for the fault c s-a-0. the TC shown in Figure 10as follows. The addition of the arc (d,a) will allow all ancestors of d to reach all descen5. FINDING NECESSARY ASSIGNMENTS dants of a. The ancestors of d, i.e., vertices E, 6 and 7, The techniques of implication, justification,static learning, are the vertices with a 1 in column d in Figure 10 and the dynamic learning and sensitization of dominators are implicit descendants of 2, i.e., vertices a, b and f, are the vertices in the TC method. Also, as we will explain,logical dominators with a in row a. For example, vertex (an ancestor of are implicitly sensitized. Furthermore, it is possible to detect d), that in Figure could only reach and e, can now difficult redundancies that may not be detectable using other also reach vertices a, b, 3 and f (see Figure 12). techniques. 3. Derive logical conclusions from the updated TC. In FigImplicit Implication and Justification: Consider the circuit ure 12, there is an arc (E, a) but there is no arc (a,E). Thus, shown in Figure 8. The Boolean false function for this cira = 1 is the only value that can satisfy the arc (E, a ) (note cuit, which is the logical OR of the false functions for gates that this arc can only result from the relation E = 0). Simd,-e-and f, consists of the following two-variable terms: ilarly, we can conclude that b = f = 1. E d, b d, b if, E T ,a 7 and i 7. The binary relations arising from

FIGURE 8: An example circuit.

these terms are represented in the IG shown in Figure 9. This graph also happens to be its own TC. The adjacency matrix of

a a 1 E l b O 6 1 c 0 E 0 d l ~ 1 e 0 z 0 f O ~ 1

FIGURE 9: IG of circuit in Figure 8.

the TC is shown in Figure 10. a E -bb c z d ~ e i -ff

a 1 0 0 O 0 0 O 1 0 f O O

E b 6 c Z d a e i 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 O O l O O l O l 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 1 O O O O O l O O 0 1 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 0 0 O O O O O O O O O O O O O l O l

5 0 0 0 O 0 0 O 0 0 1 O O

f 0 0 0 O 0 0 O 0 0 1 l O

7 0 0 0 O 0 0 O 1 0 0 O l

h 0 l O 0 0 0 O 0 0 0 O 0

b ~ c 0 0 0 0 1 0 0 0 l O O O 1 1 0 0 0 0 1 0 0 0 0 1 l O O O 1 0 0 0 0 0 0 1 0 1 0 O O O O 1 0 0

FIGW

E 0 1 O 1 0 0 l 0 0 0 O 0

d 0 1 O 1 0 0 l 0 0 0 O 1

= 0.

~ e i 0 0 0 0 0 0 1 0 O O O O 1 0 1 0 0 0 0 0 1 0 0 0 O O l O 1 0 0 1 1 0 0 0 0 1 1 0 O O l O 1 1 0 1

Z

0

1

12: TC of IG in Figure 11.

TC does more than Implication and Justification: Consider the

0

FIGURE10: TC ofIG in Figure 9.

Suppose d = 0, Forward implication will result in f = I Paper 22.3 356

FIGURE 11: 1G of circuit in Figure 8 with d

case when signal f in the circuit of Figure 8 is assigned the value 1. This results in the addition of the arc @, f) to the IG leading to Figure 13. The transitive closure method will fix signal b to logic value 1, as explained below. It is important to note that, given f = 1, conventional implication and justification procedures will not be able to conclude that signal b should be fixed at 1. If f = 1, the three-variable term def in the false function of the gate f reduces to de. Inclusion of the relations 7 = 0 and de = 0 will result in the addition of the following arcs

f

~

As an example of identification and sensitizationof logical dominators,considerthe case when signala is set to logic value 0. Since the fault on stem b cannot propagate to gate d, gate e becomes the logical dominator. Furthermore, signal c must be set to 1 to sensitize the logical dominator e. The identification of e as the logical dominator and the assignment c = 1 is implicitly determined by the TC method, even in the case when the circuit is part of a larger circuit and there are multiplepaths FIGURE 13: IG of circuit in Figure 8 with f = 1. from signal f to the primary output. To see this, we construct the Boolean false function for the circuit with fault. Concepto the IG of Figure 9: (T,f), (d,F) and ( e , x ) . The updated tually, we can visualize the circuit with fault as the modified IG is shown in Figure 13 and the correspondingTC adjacency circuit shown in Figure 15. By including the functional and matrix is given in Figure 14.As explained earlier, we can also construct the updated TC by incrementally changing the TC shown in Figure 10. a E b $ c Z d z e F f T a 1 0 0 0 0 0 0 0 0 0 0 0 E 0 1 1 0 1 0 1 0 0 1 1 0 -bb 0l 0O 1l 0l 0l 0O 0l 0l 0l 0l 0l 0O c

0

0

0

0

E d z e i f j

1 O 1 1 F O l

0 O 0 0 0 O O

1 l 1 1 0 O l

0 O 0 0 1 O 0

1

0

0

0 1 0 l O l 0 0 0 0 0 0 0 1 0 0 O O O l O l

0

0

0

0

0

1 O 1 1 0 O l

1 O 0 1 0 O l

0 l 0 0 1 O l

1 l 1 1 1 l l

0 O 0 0 0 O l

FIGURE 14:TC of IG in Figure 13.

FQGW 15: Modified circuit for fault b s-a-0 in Figure 8. structuralconstraintsin the Boolean false functionof the faulty circuit, and by computing the TC of the binary relations,we see thats, = 1 andc= 1.

Redundancy Identification: Consider the circuit shown in Figure 16.By simulatingthe circuit for all possible combinations

Notice that the updated TC (Figure 14)has a 1 in row and column b. Thus, g implies b. But b does not imply 6. The arc (i,b), therefore, indicates the relation i = 0. Hence, b must be fixed at 1 as a consequence of originally fixing f = 1. Implicit Sensitizationof Physicaland Logical Dominators: Dom-

inators are gates through which the fault must propagate in order to be observable [9]. We refer to such gates as physical dominators. As an example, consider the fault b s-a-0 in the circuit of Figure 8. It is easy to see that the fault must propagate through gate f to be observable at the output of the circuit and thus f is identified as a physical dominator. When signal a is assigned the value 0, the fault must propagate through gate e to reach an output. Gate e is now a logical dominator. The TC method implicitly identifies and sensitizes many physicaland logicaldominators. We illustratethesefeatures by an example. The physical dominators of fault b s-a-0 are determined purely from the structural constraints, as expressed by these path variables: so Fd = 0,sce; = 0,S d Tf = 0, se Tt = 0 and 8 b z d ; , = 0,The last constraintensures that the stem fault on b propagates to either signal d or e or both in order to be observable at the primary output. Initially, 8 b is set to 1 since we assume that the fault on stem b is observable. This will reduce , = 0 to the binary relation ;d ; , = 0. the ternary relation 8 b ?id ; It can easily be verified that the TC of these binary relations fixes 8f to 1. Therefore, gate f is a dominator. Note that f will be identified as a dominator of the fault even if this circuit was embedded in a larger circuit.

FIGURE 16: A circuit with redundant fault IC s-a-1. of a and b, it can be verified that the fault k s-a-1 is indeed redundant. Since the fault is on the primary output, we simply have to justify the value 0 on signal IC. The binary relations obtained from the Boolean false function of the circuit are listed in n b l e 1. The Boolean false functionfor gate IC is 7 + 7 since gate k contributes the relations = 0 and -jIC ==00.to Therefore, the Boolean false functionof the entire circuit. Binary relations contributedby other gates can be similarlyderived. If we represent these relations as an IG and compute the TC, both arcs (a,E) and ( E , a) will be present in the TC. This indicates a contradictionand, therefore, no assignment of signal values will satisfy the Boolean false function for the circuit

Paper 22.3 357

TAELE1: Binary relations for circuit in Figure 16 (IC = 0).

Gate C

d e

f 9

h i

j k

TABLE 2: Experimentalresults.

I circuit

I

c30

Total Faults Random vectors Hard faults

I

c432

I

generation with several advantages. First, the TC is a single tool that replaces the entire bag of tricks used to speed up branch and bound search. Second, our technique determines all logical consequences based on pairwise signalrelationships for a partial set of signal assignments and provides a good framework for reasoning about signal relationships in the circuit. Third, transitive closure computation is easily parallelizable. Therefore, it can be effectively used to identify necessary assignments in parallel test generation methods. Also, in conventionaltest generation methods, implicationand justification are carried out in a series of steps. TC integrates many steps in a global sense. Thus, conflicts are quickly discovered. We have indicated the applicationof TC in redundancy identification. While we have presented a new algorithm, the TC may also be included in any existing test generation algorithm. Acknowledgments: The authors thank Steve Rothweiler for programming assistance and Mike Bushnell for suggesting the example in Figure 16. REFERENCES [l]

F. Brglez and H. Fujiwara. A Neutral Netlist of 10 Combinatorial Benchmark Circuits and a Target Translator in FORTRAN. In Proc. IEEE Infl. Symp. on Circ. andsyst., pages 663-698. June 1985.

[2]

S.T. Chakradhar. Neural Nehvork Models and OptimizafionMethods for Digital Testing. PhD thesis, Dept. of Computer Science. Rutgers

524

4

University, New Bwswick, NJ. DCS-TR-269, Oct. 1990.

with IC = 0. We conclude that the fault is redundant.

[3]

S. T. Chakradhar. V. D. Agrawal, and M. L. Bushnell. Automatic Test Generation Using Quadratic 0-1 Programming. In Proc. 27th ACMIIEEE Design Automat. Conf., pages 654-659. June 1990.

[4]

S.T. Chakradhar, V. D. Agrawal, and M. L. Bushnell. Neural Net and Boolean Satisliability Models of Logic Circuits. IEEE Design & Test of Comput.,7. Oct. 1990.

6. EXPERIMENTAL RESULTS

T. H. Comen. C. E. Leiserson, and R. L. Rivest. Introduction to AlgoA preliminaryversion of the test generation system was im- [SI rithms. McGraw Hill, New York, 1990. plemented in the C programming language and was run on a H. Fujiwara and T. Shimono. On the Acceleration of Test GeneraSUN Sparc 1+ workstation. Results on two combinationalcir- [6] tion Algorithms. IEEE Tram. on Comput., C-32(12):1137-1144, Dec. cuits are reported here. Circuit c30 is obtained by replacing 1983. all NOR gates by two-input XOR gates in the Schneider cir- [7] J. Giraldi and M. L. Bushnell. EST The New Frontier in Automatic Test-Pattern Generation. In Proc. 27th ACMIIEEE Design Automat. cuit [12]and circuit c432 belongs to the ISCAS 85 benchmark Conf., pages 667-672, June 1990. set [l]. In both circuits, each two-input XOR gate was implemented by three gates. The program generated tests for all [8] P. Hansen, B. Jaumard,andM. Minoux. A Linear Expected-Time Algorithm for Deriving All Logical Conclusions Implied by a Set of Boolean testable faults in the two circuits. No fault simulationwas used Inequalities. Math. Programming, 34(2):223-231. March 1986. for either of the circuits. Furthermore, we did not include the T. Kirkland and M. R. Mercer. A Topological Search Algorithm For structural constraints (Section 4). [9] ATPG. In Proc. 24th ACMIIEEE Design Automat. Conf., pages 502Table 2 summarizes the results. Random vectors is the num508.June 1987. ber of test vectors generated in the random test generation [lo] S.R. Pawagi.P. S.Gopalakrishnan,and I. V.Ramakrishnan. Computing phase which terminates when 64 random vectors do not inDominators in Parallel. Inform.Process. Left.,24:217-221,1987. crease fault coverage. Hard faults is the number of faults re[ l l ] J. Rajski and H. Cox. A Method to CalculateNecessary Assignments maining undetected after this phase. Redundantfaults is the in Algorithmic Test Pattern Generation. In Proc. IEEE Infl.Test Conf., number of faults found to be redundantby the TC method. ATG pages 25-34. Sept. 1990. time is the test generation time for all Hardfaults and TC time R. Schneider. On the Necessity to Examine D-Chains in Diagnostic is the transitive closure computationtime in the entire run. All [12] €?Test Generation. I B M J . ofRes. & Dev., 11(1):114, Jan. 1967. redundant faults in both circuits were identified through con[13] M. H. Schulz and E. Auth. Improved Deterministic Test Pattern Genertradictions in the TC method. In the future, we plan to include ation with Applications to Redundancy Identification. IEEE Tram. on structuralconstraintsand generate tests for other circuits in the CAD,8(7):811-816.July 1989. benchmark set.

7. CONCLUSION We have applied the graph theoretic concept of TC to test Paper 22.3 358

[14] B. F. Wang and G. H. Chen. ConstantTime Algorithms for the Transitive Closure and Some Related Graph Problems on Processor Array with Reconfigurable Bus System. IEEE Tram. on Parallel and Distributed Syst.. 1:500-5W, Oct. 1990.