A Universal-Input High-Power-Factor PFC Preregulator without Electrolytic Capacitor for PWM Dimming LED Lighting Application Jih-Sheng(Jason) Lai2, Fellow, IEEE Quanyuan Feng1, Senior Member, IEEE Bo-Yuan Chen2,3, Student Member, IEEE
Hongbo Ma1, 2, Student Member, IEEE Wensong Yu2, Member, IEEE Cong Zheng2, Student Member, IEEE 1 2
School of Information Science & Technology, Southwest Jiaotong University, Chengdu, Sichuan, China
Future Energy Electronics Center, Bradley Department of Electrical and Computer Engineering, Virginia Polytechnic Institute and State University, Blacksburg, VA, USA 3
Center for Power Electronics Technology, National Taipei University of Technology, Taipei, Taiwan
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[email protected]. requires an ac-dc converter with high power factor and low harmonics to meet the standard such as IEC-61000-3-2[1-5]. Thus, the power supply for LED lighting must include the power factor correction (PFC). The PFC can be implemented by either two-stage or single-stage preregulators. In the general lighting applications because the power level is relatively low, single-stage PFC has been widely employed. The single-stage PFC has the advantages of simple circuit configuration, ease of control implementation and low cost [8-10].
Abstract—High brightness white LED has attracted a lot of attention for its high efficacy, simple to drive, environmentally friendly, long lifespan and small size. The power supply for LED lighting also requires long life while maintaining high efficiency, high power factor and low cost. However, a typical design employs electrolytic capacitor as storage capacitor, which is not only bulky, but also with short lifespan, thus hampering the entire LED lighting system. To prolong the lifespan of power supply, it has to use film capacitor with small capacitance to replace electrolytic capacitor. In this paper, a universal input high efficiency, high power factor LED driver is proposed based on the modified SEPIC converter. Along with a relatively large voltage ripple allowable in a PFC design, the proposal of LED lamp driver is able to eliminate the electrolytic capacitor while maintaining high power factor. To increase the efficiency of LED driver, the presented SEPIC-derived converter is modified further as the twin-bus output stage for matching ultra-high efficiency twin-bus LED current regulator. The operation principle and related analysis is described in detail. A 50-W prototype has been built and tested to verify the proposed LED Driver.
No matter what kind of PFC converter, to balance the difference between instantaneous input power and constant output power, storage capacitors with large capacitance have to be employed. Hence, electrolytic capacitor is often selected as storage capacitor for its advantages of high voltage and large capacitance [1-10]. Unfortunately, because of its liquid electrolyte, the lifetime of an electrolytic capacitor is only several thousand hours under rated operating conditions, which is much shorter than the lifetime of LEDs. In order to prolong the overall long lifetime of LED lighting products, it is necessary to reduce the storage capacitance and use other kind of capacitor instead of electrolytic capacitor [1, 4].
Key Words—Electrolytic capacitor; SEPIC-derived; multiple lighting LED lamps; universal input voltage; power factor correction (PFC); PWM dimming
I.
INTRODUCTION
The state-of-the-art LED power supplies often employ near-unity input power factor ac/dc pre-regulators, which normally involve with an ac-dc converter circuit such as two-stage PFC, Boost-Flyback[1], Buck-Flyback[5], SEPIC[2-3], Flyback[6] etc. However, an electrolytic capacitor is employed in these applications. Reference [4] proposed the method of injecting 3rd harmonic into the input current to reduce the storage capacitance of CCM boost PFC
The high brightness white light-Emitting diode (LED) as a solid-state lighting source has become popular in general lighting application. As a new lighting source, LEDs have the well-known advantages of high efficiency, long lifetime, environmental friendliness, smooth dimming and smaller size, safety improvements compared with conventional lighting devices [1-6]. For the LED power supply design, it This work was co-sponsored by the National Semiconductor Corporation, the National High Technology Research and Development Program (“863” Program) of China (under Grant No. 2009AA01Z230), and National Natural Science Foundation of China (under Grant No. 10876029).
978-1-4577-0541-0/11/$26.00 ©2011 IEEE
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The transformer T1 with twin-bus output stage is employed for increasing the total efficiency. Because the twin-bus output voltage can match the ultra-efficiency twin-bus buck current regulator, which is proposed by us in [8]. 3) In order to eliminate electrolytic capacitor, the idea of utilizing large voltage ripple with small capacitance for energy storage is adopted. 4) Snubber Dsn and Csn can avoid voltage spike over MOSFET. And that the energy stored in Csn can be recycled to power housekeeping circuit. Detailed operating principle and analysis is described in Section II and Section III, which also imply how to eliminate the electrolytic capacitor while maintaining high power factor. In Section IV, experimental results from a 50-W universal input voltage prototype are given to verify the effectiveness of the AC/DC LED driver. Finally, this paper is summarized.
and the corresponding implementation circuit. A PFC topology named BIFRED was introduced in [9]. Same topology is resulted in [10]. But the difference is the dc-dc converter in [10] operates in DCM. The resulting advantages over the BIFRED are: significantly lower harmonic distortion with the same voltage stress on the switches, a well regulated output voltage, and independent dc-bus capacitor voltage on output load. But, it still needs the large electrolytic capacitance to use as storage capacitor, which is unsuitable to the LED lighting application. In this paper, a high efficiency offline LED driver without electrolytic is proposed based on the developed topology in [10]. As shown in Fig.1. The proposed LED Driver has advantages over its origin as follows: 1) remove the inserting diode for saving power consumption, but the D1 and D2 must selected ultra-fast reverse recovery diode. 2)
Figure 1. The proposed offline LED Driver without electrolytic capacitor.
II.
corresponding equivalent circuits at different operation intervals are shown in Fig.3 (a)~(d). The converter analysis starts at the instant t0, when the switch Q is turned on.
OPERATION PRINCILPE
In order to make the analysis more transparent, the nonisolated version in Fig. 2 was considered. The relevant equations for isolated case can be derived from results obtained here. The analysis is based on the following assumptions: • The rectified input voltage, vrect=Vm|sin(ωlt)|, is an ideal sine wave, where Vm and ωl are the peak amplitude and the line angular frequency respectively. •
All components are ideal.
•
The switching frequency (fs) is much higher than the ac line frequency (fl), so that the input voltage can be considered constant during one switching period (Ts).
•
•
Interval [ t0, t1]: Prior to this interval, the currents through Lb and L0 are at zero level. When switch Q is turned on at t0, diodes D5 are reverse bias; the equivalent circuit is shown in Fig.3 (a). Hence, the currents iLb and iL0 begin to increase linearly as shown as Fig.4. This interval ends when switch Q is turned off, initiating the next interval. In this internal, the current of inductor Lb and L0 (iLb and iL0) and switch current iQ can be derived approximately as: vrect t Lb VC i L (t ) = 1 t 0 L0
iLb (t ) =
VC v iQ = iL (t ) + iL (t ) = ( rect + 1 )t 0 b Lb L0
Both capacitors C1 and C0 are big enough so that the voltages VC1 and V0 can be considered constant during Ts.
(1) (2) (3)
Interval [ t1, t2]: When the switch Q is turned off, diode D5 becomes forward biased, carrying the sum of iLb and iL0 . Thus, currents iLb and iL0 decrease linearly at rates proportional to (VC1+V0-vrect) and V0, respectively. The corresponding current waveforms are shown in D2TS of
Both inductors Lb and L0 operate in DCM. Furthermore, the inductor current iLb reaches zero level prior to the inductor current iL0
Fig.4. Fig.3 (b) shows the equivalent circuit at this interval. This interval is not ends until the current iLb reaches ground level. Similarly, the current of inductor Lb and L0 (iLb and iL0) and diode current iD5 can be described approximately as:
Based on the above assumptions, the schematics operations during one switching cycle can be divided into four distinct intervals. The main current waveforms during a switching period are plotted in Fig.4, while the
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(d) [t3, t4] interval Figure 3. The equivalent circuits of the proposed SEPIC-derived PFC converter.
Figure 2. The simplified topology of PFC Pre-regulator
vrect v − VC1 − V0 D1Ts + rect t Lb Lb VC V iL (t ) = 1 D1Ts − 0 t 0 L0 L0 Vrect VC1 Vrect − VC1 V0 V0 ) D1Ts + + iD5 (t ) = ( t − ( + )t Lb L0 Lb L0 Lb iLb (t ) =
(4) (5) (6)
Additionally, the snnuber circuit consisting of Dsn and Csn abort the spike of switch Q, which is produced by leakage inductance of transformer T1 Interval [ t2, t3]: In this interval, the current iL0 continues to decrease through the freewheeling diode D5. This interval ends when the current of D5 reaches zero. The corresponding equivalent circuit is plotted in Fig.3 (c). Figure 4. The main current waveforms of the proposed single-stage PFC topology in a switch cycle.
Interval [ t3, t4]:This interval is a resting stage where all semi-conductors are off and all branch currents are zero. The converter stays in this state until the switch is turned on again.
III.
ANALYSIS OF THE PROPOSED PFC PRE-REGULATOR
A. Calculation of Power Factor Value For simplicity, based on the same assumptions described in section II, the input voltage is defined as
vac = Vm sin ωt (7) Where Vm is the amplitude of the input voltage, is the angular frequency of the input voltage. Then the rectified voltage is
(a) [t0, t1] interval;
(8) Vrect = Vm sin(ω t ) Based on the current waveform of inductor Lb in a switching cycle when the converter operates at DCM, we know the inductor peak current in a switching cycle iLb_pk
Vm sin ωt Vrect D1Ts = D1Ts (9) Lb Lb Where D1 is the duty cycle and Ts is the switching cycle. In each switching cycle, the inductor has the volt-second balance, i.e.
(b) [t1, t2] interval
iLb _ pk =
Vrect DT 1 s = (VC1 + V0 − Vrect ) D2Ts (c) [t2, t3] interval;
(10)
Where Vo is the output voltage, D2 is the duty cycle corresponding to the reset time of the inductor current. From (10),
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D2 =
Vm sin ωt Vrect D1 D1 = VC1 + V0 − vrect VC1 + V0 − Vm sin ω t (11)
current is, thus the closer to sinussoidal shape the average inductor current in a switching cyclee is.
From (9) and (11), the average inducctor current in a switching cycle can be derived as iLb _ ave (t ) =
V D2 1 iLb _ pk
