A Virtual Logic Algorithm for Solving Satisfiability Problems Using Reconfigurable Hardware Miron Abramovici
Jose T. de Sousa
Bell Labs - Lucent Technologies Murray Hill, NJ 07974
[email protected]
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908-582-3562
Abstract Satisfiability (SAT) is a computationally expensive algorithm central to computer science. In this paper, we present a virtual logic algorithm that allows an FPGA based reconfigurable computing platform to process SAT solver circuits much larger than its available capacity. Our algorithm is based on decomposition techniques that create independent subproblems that fit the size of the available reconfigurable hardware.
1. Introduction The satisfiability (SAT) problem - given a boolean formula F (x 1, x 2 ,… ,x n) , find an assignment of binary values to (a subset of the) variables, so that F is set to 1, or prove that no such assignment exists - is a central computer science problem with a large number of important applications. This problem is NP-complete[4]. Typically F is expressed as a product-of-sums called conjunctive normal form (CNF). SAT applications include many problems in EDA such as timing verification [9], layout and routability analysis[5], automatic test generation[8], fault diagnosis[13], and logic synthesis[3]. Since speeding up SAT will result in improving the efficiency of many algorithms relying on SAT, SAT solvers based on reconfigurable hardware have been the object of many recent papers [1][2][10][11][14][20]. Unlike a hardware accelerator, where the same special-purpose hardware is used for every problem, a different satisfier is created for every given formula; of course, this is feasible only by using reconfigurable hardware. It has been demonstrated that reconfigurable hardware satisfiers can achieve several orders of magnitude speed-up compared to the best software solvers [1][10][14]. However, satisfiers for common problems are circuits that normally exceed the size of current reconfigurable logic platform. The ideal solution would be a virtual logic mechanism that allows a reconfigurable logic platform to process circuits much larger than its available capacity at the cost of some additional processing time (in the same way a virtual memory system can work with a logical address space much larger than its physical address space). In this way, platforms much cheaper than emulators could be used.
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2. Decomposition for Disjoint Partitioning One type of partitioning used in software SAT solvers is finding subsets of clauses that depend on disjoint subsets of variables. The resulting subproblems are independent and may be separately solved. If one subproblem is unsatisfiable, so is the original problem. The solution to the original problem is obtained by concatenating the individual solutions of all subproblems. A disjoint partition provides an exponential reduction of the worst-case search space of a SAT solver, but it is seldom found in practical problems. However, such partitions may be created dynamically, as a consequence of the formula simplifications caused by assignments to variables. We introduce a new decomposition technique, whose goal is to assign variables so that the resulting subproblems are disjoint. Our decomposition relies on a simple recursive clause bipartitioning algorithm. The algorithm works by creating two clause clusters that share as few common variables as possible. To separate these two clusters, we assign (at least some of) their common variables. The algorithm tries tentative formula simplifications for both 0 and 1 assignments to each common variable, and evaluates them based on the reduction obtained in the set of common variables. If there are no common variables, the process continues recursively with the two disjoint subformulas (both need be satisfied). The recursion terminates when the current formula fits into our reconfigurable logic platform. The algorithm just described has been implemented in C++. Our algorithm has similarities to a previous algorithm [van Gelder???]. However in [van Gelder] the subproblems are created by assigning all common variables, resulting in 2^(nc+1) subproblems, where nc is the number of common variables. In contrast, our algorithm assigns the common variables one at the time and computes the implications of each assignment. Since the common variables are chosen so that their assignment contributes to eliminate other common variables, in general we generate much fewer subproblems than 2^(nc+1).
3. Results We use examples extracted from the DIMACS set of SAT benchmarks[7]. The first 5 columns in Table 1 show the benchmark data: name, number of inputs #I, number of
clauses #C, number of literals #L, and a Yes/No indication of satisfiability. The following 4 columns show the number of subproblems) #Pdpobtained with decomposition for disjoint partitioning, the number of clock cycles #CK executed by the satisfier for the unpartitioned problem, the number of clock cycles #CKdp executed by all subproblems running in parallel, and the speed-up SUdp = #CK/#CKdp. The hardware cycles were obtained using the satisfier presented in [1], and composing the respective yes/no outcomes and solution vectors.
As we can see, decomposition produces a manageable number of subproblems, which, when run concurrently can easily reach 3 orders of magnitude speed-up. This is perfect for the virtual logic mechanism, since it means we can reuse the existing hardware to run batches of subproblems serially, without losing efficiency compared to the unpartitioned formula. Also, we need to discount the time used to execute the decomposition procedure itself. Our examples ran in a matter of seconds except dubois100 and hole8 which took 10 and 3 minutes respectively.
Table 1. Summary of results Example
#I
#C
#L
Sat #Pdp
dubois50
150 400
1200
N
dubois100
#CKdp
SUdp
46
>100,000,000
49,273
>2,029.5
300 800
2400
N
320
>100,000,000
25,083
>3,986.8
hole7
56 204
448
N
13
32,437
5,240
6.2
hole8
72 297
648
N
128
259,519
7,344
35.3
ii8a1
66 186
450
Y
3
32
12
2.7
par8-2-c
68 270
780
Y
10
121
13
9.3
par8-5-c
75 298
864
Y
1
69
9
7.7
pret60_25
60 160
480
N
64
28,519,626
4,501
6,336.3
pret60_40
60 160
480
N
64
28,519,626
4,501
6,336.3
4. Conclusions
[3] R. Brayton, G. Hachtel, C. McMullen, and A. Sangiovanni-Vincentelli, Logic Minimization Algorithms for VLSI Synthesis, Kluwer Academic Publishers, 1984 [4] S. A. Cook, “The Complexity of Theorem-Proving Procedures,” Proc. 3rd Annual ACM Symp. on Theory of Computation, pp. 151-158, 1971 [5] S. Devadas, “Optimal Layout Via Boolean Satisfiability,” Proc. Intn’l. Conf. on CAD, pp. 294-297, November 1989 [6] S. Devadas, K. Keutzer, S. Malik, and A. Wang, “Certified Timing Verification and the Transition Delay of a Logic Circuit,” Proc. Design Automation Conf., pp. 549-555, June, 1992 [7] DIMACS Challenge Benchmarks, ftp://dimacs.rutgers.edu/ pub/challenge/sat/benchmarks/cnf/ [8] T. Larrabee, “Test Pattern Generation Using Boolean Satisfiability,” IEEE Trans. on CAD, Vol. 11, No. 1, pp. 4-15, January, 1992 [9] P. C. McGeer et al., “Timing Analysis and Delay-Fault Test Generation Using Path Recursive Functions,” Proc. Intn’l. Conf. on CAD, pp. 180-183, November 1991 [10] M. Platzner and G. De Micheli, “Acceleration of Satisfiability Algorithms by Reconfigurable Hardware,” Proc. Intn’l. Workshop on Field-Programmable Logic and Applications, Sept., 1998 [11] T. Suyama, M. Yokoo, and H. Sawada, “Solving Satisfiability Problems on FPGAs,” Proc. Intn’l. Workshop on Field-Programmable Logic and Applications, 1996 [12] R.G. Wood and R.A. Rutenbar, “FPGA Routing and Routability Estimation Via Boolean Satisfiability”, Proc. Intn’l. Symp. on FPGAs, February 1997 [13] Y. Wu and S. Adham, “BIST Fault Diagnosis in Scan-Based VLSI Environments,” Proc. Intn’l. Test Conf., pp. 48-57, October 1996 [14] P. Zhong, M. Martonosi, P. Ashar, and S. Malik, “Accelerating Boolean Satisfiability with Configurable Hardware,” Proc. IEEE Symp. on Field-Programmable Custom Computing Machines, April, 1998
In this paper we have introduced a new virtual logic system for solving satisfiability problems using reconfigurable hardware, which we called decomposition for disjoint partition. This novel technique can effectively divide a formula into independent subproblems that fit the available reconfigurable hardware. Thus, a reconfigurable platform much simpler than an emulator can be used. Also, according to the architecture of reconfigurable hardware satisfier, smaller independent subproblems can be clocked faster than the original problem. The decomposition into independent subproblems is the key to our a virtual logic mechanism, that allows a reconfigurable logic platform to process circuits much larger than its available capacity. The set of generated subproblems can easily run 3 orders of magnitude faster than the original problem, which compensates for the time spent in decomposition. Combined with our fine-grain massively-parallel satisfier architecture described in [1], the virtual logic for SAT has the potential to offer a low-cost solution for solving computationally difficult problems in a wide variety of fields. Acknowledgment: We acknowledge useful discussions with Prof. D. Saab on early versions of these ideas. References [1] M. Abramovici, J. Sousa, and D. Saab, “A Massively-Parallel Easily-Scalable Satisfiability Solver Using Reconfigurable Hardware,” submitted to Design Automation Conf., 1999 [2] M. Abramovici and D. Saab, “Satisfiability On Reconfigurable Hardware,” Proc. Intn’l. Workshop on Field-Programmable Logic and Applications, Sept., 1997
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#CK
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