A VME RISC processor farm for third level triggering - Google Sites

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A VME RISC Processor Farm for Third Level Triggering P.Y.Duval, T.Geralis, F.Montanet CPPM IN2P3 et Universite dAix Marseille II, 163 av de Luminy, Case 907, F-13288 Marseille, France

C.P.Bee, L.E.Sacks CERN, PPE Division, CH-1211 Geneva 23, Switzerland tion in the calorimeter,Fig. 1. The processor proceeds through a number of stages, assessing the event in a cascade of trigger decisions (in time intervals from 6Ons to 25ps), thus miniThe need for very fast, compact, V M E based farms of pro- mizing dead time. The information accumulated in the trigger is made availcessors exists in many areas of experimentalphysics. Reported here is a development for such a farm targeted at the require- able to a readout system. This not only facilitates debugging ments of the online and trigger system of the CERN experi- but also allows the processing done on event reconstructionby ment PS 195 (CPLEAR ). The system is characterised as being the dedicated electronics (with a capacity of around 100 MIPS) VME based,and requiring small events (around 1KByte) to be to be further utilised for &'/E processing. The final level of the trigger works on neutral particles, processed at high rate (greater than 1KHz). The development was for a single chassis system, using the MIPS R3000 chip utilising information accumulated in the previous trigger processors to reconstruct Kos decaying to 22cOs. This work could mounted on a commercially available board. not be done using custom hardware and will be performed by a I. INTRODUCTION processing farm called HWP3/4 [3].

ABSTRACT

Developments in new technologies often benefit from being directed toward application in existing systems. Given below is a brief description of the trigger and data acquisition of CPLEAR into which a farm of RISC based processors will fit. This is followed by a description of the test bench set-up to assess the viability of current applications of this technology.

A. The CPLEAR Experiment

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The CPLEAR experiment[l] was designed to utilize the high production rate of neutral Kaons from proton anti-protron annihilation at rest. To do this, the experiment concentrates on the reactions:

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PP + K0K-a+ and PP + K K nHere, the two 'primary' charged tracks of the K-n+ are used, at the trigger level, to 'tag' the neutral kaon. This is done by reconstructing the missing mass, and taking advantage of Fig.1 Overall Trigger Sequence odd strangeness among the charged particles (i.e. just one charged Kaon). All events containing a neutral kaon are required for the measurement of the partial decay rates of the C. The Acquisition System kaon for the quantity E'/& and are written to a special acquisition stream. The decay products of the neutral Kaon are The acquisition system[4] has been constructed in VME. It assessed to select events for acquisition to the mainstream sys- takes data from the detector front end readout systems directly to IBM3480 compatible cartridges, Fig.2. Transfer of over tem for full offline event reconstruction. 900,2Kbyte events per second is possible, with minimum set B. The Trigger up time overheads. The embedded CPUs are FIC8230 modules from CES running under the Valet Plus system[5]. These conTo achieve the required performance for data selection, the trol all data transfers as well as facilitatingrun control and data mgger system[2] has been built to fully reconstruct events us- monitoring for the sub-detectors. Data transfer from the detecing custom electronics up to the level of shower reconstruc- tor front ends utilises the Super Vior (STR302) with a data 0018-9499/92$03.00 Q 1992 IEEE

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driven DMA moving the data to buffers in the CPUs. From there it is transferred via VSB to DPMs in the event builder. The events are acquired after a good decision of the hardware processors. Events requiring treatment from HWP3/4 are stored in buffers in the Event Builder which waits for the final trigger decision. Accepted events are incorporated into a standard ZEBRA buffer for transfer to cassette and for sampling by the VAX cluster for monitoring.

Number of Processor CPUs

Fig.3 Processor Throughput Neutral Trigger

These calculationsdetermine the number of CPU cards required in the system. There are other constraints apart from these. Cost and the capacity of the system also put a limit on the number of units used. These considerations place a limit on the maximum processing time available.

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Fig.2 The Upstream Acquisition

D . Utilisation of Processing Farms

11. THE TEST BENCH A RISC Processor based test bench to demonstrate an architecture for HWP3/4 (Fig.4) was presented at the REAL TIME '91 Conference. This was based upon the RAID/8235 from CES using the MIPS R3000 CPU. The input of data was simulated and processing results were monitored via various interfaces.

The processing farm is designed to process data in a conDS5000 tinuous system. Thus the number and speed of the processors has to be optimised so as to provide a flow through system with out data loss. The major factors (apart from cost) which VMENSB crate determine the size of the system are; The maximum number of data buffers available (NB) The expected data rate(DR) The expected processing time 0 VMEbus A combination of the NB and DR set an upper limit on PT. For example, if there are 255 buffers (as in the event builder) and DR is loo0 events/second, then the processing farm can have a maximum event latency (EL) of around 0.25s. I I I This upper limit should be above any values of PT considered here. Given a sufficiently high maximum value of EL, then Terminal the number of processor cards required is a function of PT and DR. To first approximation the efficiency of a system with NP processing cards can be estimated with a Poisson distribuFig.4 Components of the Test Bench tion (Fig.3). Some possible times for event processing have been given A. The Supervisor for HWP3/4 and Epsilon. The efficiency of the system has been calculated for processing times of; 300ps (HWP 3), The test bench used a DECSTATION 5000 as supervisor 1.4ms CHWp 3 BE 4). 6ms for Epsilon. No consideration is connected to the VME farm through a turbochanneWME ingiven here to processing over heads as these are small and are terface. From this the user can: load test events in the VME performed in parallel with event processing. memory, define the parameters of a test session, perform run control and monitor the results of the session. The interface

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for these tasks was built with RTI. The DS5000 was also used for cross-compilationof the code running on the RAIDs.

sufficient. It could also be extended to the requirements of the online event analysis required for E’/&. The system is reasonably scaleable. However a greater B . The VME Processing Farm event rate could saturate the band width of the VME and would require wider buffering space. Also the employment of a large The processor farm was built in VME and contained: a number of RAIDs could thrash the bus arbitration. To handle FIC8232 MC68030 based processor board running OS9, two these problems the RAIDs could be divided into groups of 4 units, each accessing 1 DPM over VSB for event information RAID 8235 units and a serial Dual Ported Memory. The FIC was used principally as a scheduler for the event thus reducing traffic on VME. processing on the RISC units. It also simulated the incoming 111. CONCLUSION events and performed supervisor communication with the DS5000 for status monitoring. Monitoring information was This development project has shown that a processing farm also displayed on a local ASCII terminal. These tasks were of high capacity may be constructed utilising commercially scheduledas OS9 services FigS. The two RAIDs worked as independent slaves under control available units. The system would be highly cost effective and of the FIC. Each ran the HWP3 trigger algorithm, working in easily incorporate into an existing, VME based, acquisition pardIel on different events. The number of RAIDs used is system. The high level of hardware functionality of the RAID scalable, the position and number of RAID cards are automati- and FIC e.g. FIFO managers and bus interconnections simplify the software view. cally taken into account for the each test session. The DPM was used as an event buffer. The memory was IV. ACKNOWLEDGEMENTS divided into fixed length buffers. The test events were loaded from the DS5000. When a RAID was told to process an event The realization of the development system has involved the it copied the data from the DPM to local memory for analysis. At the end of analysis the trigger decision was appended to the effort of many people whom we would like to acknowledge. F.H.Worm & J-F.Gillot from Creative Electronic Systems original buffer in the DPM. helped in acquiring and setting up the the VME hardware. D.Gillot & P.Zgraggen from Digital Equipment Corp. aided co-ordination and wrote the user-interface. W. von Ruden, Global Memory E.Bllrenzung & A.Miotto of IBEX Computing provided tools Event for the DS5000 and RAID development RDE [6]. P.Palazzi, OS9 Controlled CERN who loaned us a DS5000. Finally we acknowledge the support of P.Pavlopoulos, E.Aslanides from CPLEAR and F.Etienne from CPPM. Acquisition Scheduler

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Fig.5 Jiilich Test Bench Software Architecture

C . Communication Event data exchanges were made through the DPM. All control data from the DS5000 and between the RAID and FIC passed through the FIFO managers implemented on these cards. Only the VME bus was used.

D.Extension to the CPLEAR Experiment The configuration described would fit the requirements of the W 3 / 4 trigger processor where 2 to 3 RAIDs should be

V. REFERENCES E.Gabathuler and P.Pavlopoulos. “Strong and weak CP violation at LEAR,” Workshop on Physics at LEAR with Low Energy Cooled Antiprotons, 1982. & L.Adiels et QI, “Proposal for the experiment PS195,” CERN PSCC/85-6, 1985. D.Troster et a1 , “Trigger using track search and kinematical analysis for rare decay channels at high rates,” NIM A279 (1989) P.285 T.Geralis, Ph.D. dissertation, “The Processors of the E.M.Calorimeter of the CPLEAR Experiment Application in the PP + K + K k 0 channels,” University of Athens, 1991. C.P.Bee et al. “The CPLEAR Data Acquisition System,” ESONE VMEbus in research conference, Zurich, Proceedings / Ed. by C Eck and C Parkman. - Amsterdam : North Holland, 1988. Y.Perrin et al. “The Valet Plus Embedded into Large Physics Experiments”, ESONE VMEbus in research conference, Zurich, Proceedings / Ed. by C Eck and C Parkman. Amsterdam : North Holland, 1988. W. Von RUden, “A development for R3000 based VME CPUs.” REAL TIME ‘91 Conference.