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IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS, VOL. 17, NO. 11, NOVEMBER 2007
A Wide Locking Range Differential Colpitts Injection Locked Frequency Divider Chien-Feng Lee, Sheng-Lyang Jang, Senior Member, IEEE, and M.-H. Juang, Senior Member, IEEE
Abstract—This letter proposes a new wideband Colpitts injection locked frequency divider (ILFD) and describes the operation principle of the ILFD. The circuit consists of a differential CMOS LC-tank oscillator and a direct injection topology. The divide-by-two ILFD can provide wide locking range, and the measurement results show that at the supply voltage of 2.4 V, the tuning range of the free running ILFD is from 4.46 to 5.6 GHz, about 1.14 GHz, and the locking range of the ILFD is from 8.03 to 11.63 GHz, about 3.6 GHz, at the injection signal power of 0 dBm. The ILFD dissipates 19.92 mW at a supply voltage of 2.4 V and was fabricated in 1P6M 0.18 m CMOS process. At the tuning voltage of 1.2 V, the measured phase noise of the free running ILFD is 110.8 dBc/Hz at 1 MHz offset frequency from 4.94 GHz and the phase noise of the locked ILFD is 135.4 dBc/Hz, while the input signal power is 4 dBm. -tank oscillator, inductors, Index Terms—CMOS, Colpitts injection-locked frequency divider (ILFD), wide locking range.
I. INTRODUCTION
F
REQUENCY dividers (FDs) are widely used in high-speed systems such as frequency synthesizers and quadrature signal generators. They take a periodic input signal and generate a periodic output signal at a frequency that is a fraction of the input signal. There are several existing topologies for FD such as current-mode logic (CML) [1], dynamic logic [2], injection locked oscillator, and Miller divider [3]. Each method has its own advantages and disadvantages. For high speed resonator is the most suitable operation, the FD utilizing an one among various types of FDs [4], [5] because the operating frequency is determined by the resonant frequency. The resonator based injection-locked frequency divider (ILFD) is widely studied because of easy implementation by using a cross-coupled metal oxide semiconductor field effect transistor (MOSFET) pair. The locking range of cross-coupled ILFD is generally narrow, temperature and process variation may cause circuit operation failure due to the shifting of post process locking range out of desired design window. The design of large locking range ILFD is therefore important to ensure a reliable system function. Tuning varactors and degrading the resonator -factor are often used to extend the locking range. Alternatively, we can design ILFDs based on other voltage controlled oscillator (VCO) cores to find out a wide locking range ILFD, however, this has not been extensively studied. Manuscript received May 8, 2007; revised June 11, 2007. This work was supported by the National Science Council of Taiwan, R.O.C., under Contract NSC 95-2221-E-011-173. The authors are with the Department of Electronic Engineering, National Taiwan University of Science and Technology, Taipei, Taiwan, R.O.C. (e-mail:
[email protected];
[email protected]). Digital Object Identifier 10.1109/LMWC.2007.908055
Fig. 1. (a) Schematic of a pMOS core Colpitts oscillator. (b) Small-signal equivalent circuit with parasitic.
The goal of this letter is to design a wide locking range ILFD tank Colpitts VCO core. The proposed circuit based on an ILFD can work at a supply voltage of 2.4 V and has more than 36.6% locking range. This opens a new path to design wide locking range ILFDs. II. SINGLE-ENDED COLPITTS OSCILLATOR TOPOLOGY Fig. 1(a) and (b) shows the proposed single-ended pMOScore Colpitts oscillator and the equivalent small-signal circuit, 1 and its asrespectively. The inductor L1, the transistor sociated parasitic capacitors form the Colpitts oscillator. The 1 is used as a current source supplying nMOS transistor , , , the dc current to the oscillator. In Fig. 1(b), represent the transconductance of pMOS 1, the and 1, the drain-substrate capacitors gate-source capacitor of 1 and 1, and the parasitic substrate reof transistors sistor, respectively. R1 represents the series resistor of inductor 1 generates an effective negative differential L1.The PMOS 1, transconductance— , looking into the drain of pMOS and 1. Fig. 1(b) is to compensate for the tank loss due to a small-signal equivalent circuit of Colpitts oscillator [6], which has a tap between two capacitors. Due to the simplicity and low parasitic capacitance of oscillator core, the Colpitts oscillator is adequate for high frequency application. The gate and drain out1 can be used to drive the output buffers for puts of PMOS measurement, however, the magnitudes of the simulated drain and gate voltages are different, therefore the circuit is not suitable for differential application. III. DIFFERENTIAL COLPITTS ILFD TOPOLOGY There are many ways to make a differential VCO by using the single-ended VCO shown in Fig. 1. Fig. 2 shows the proposed ILFD circuit. We first neglect the effect of MOSFETs 3 and 6 to discuss the operation of the inherent differential Colpitts
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LEE et al.: WIDE LOCKING RANGE DIFFERENTIAL COLPITTS ILFD
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Fig. 4. Chip photograph of the proposed differential Colpitts ILFD.
Fig. 2. Proposed differential Colpitts ILFD topology.
Fig. 5. Measured frequency tuning characteristics of the free running oscillator. 1.2, 1.4, and 1.6 V.
Vinj = Fig. 3. Relationship between ac input voltage and ac output voltages of the differential ILFD.
VCO. There are two single-ended Colpitts oscillators combined into one differential circuit. The two single-ended Colpitts oscillators are coupled by a pair of cross-coupled nMOS transistors 1 and 4, which force the two oscillators to operate in a differential form. Transistors 1 and 4 serve as current sources without dc bias by connecting the drain of 1 ( 4) to the gate of 4 ( 1). The drain voltage of 1 ( 4) serves as the bias of the gate of 4 ( 1). The varactors (Cvar) are used for frequency tuning and connected between the gate and drain of pMOS transistors. In order to drive 50 test systems such as spectrum analyzer, we adopt a common source buffer amplifier. Fig. 2 also shows the proposed ILFD embedded with resonators, two injection MOSFETs ( 3, 6) in the two the source and drain of injection MOSFET are connected to the drain and gate nodes of PMOS. The injection MOSFETs are used to couple the injection signal to the resonators. The differential Colpitts ILFD consists of two single-ended ILFDs coupled by a pair of switching MOSFETs. There are two roles for the cross-coupled transistors 1 and 4. On the one hand, the transistors M1 and M4 are used to couple two single-ended Colpitts oscillators formed by (L1, 2) and (L2, 5) to generate differential outputs. On the other hand, they provide current sources for the PMOS Colpitts oscillators to sustain oscillation without using a bias circuit and they also provide parasitic capacitors from output nodes to the bodies for the PMOS-core Colpitts oscillators. A single external injection signal is applied simultaneously to the gates of the injection
Fig. 6. Measured relationship between input sensitivity and operating fre0.0, 1.2, 1.5, and 2.4 V. quency at the supply voltage of 2.4 V. 1.4 V.
Vinj =
Vtune =
MOSFETs. The tank is designed to have the oscillation frequency in the 5 GHz band. This circuit is put together piece by piece, therefore it can be used as a pedagogical purpose. The relationship between the ac injection signal and the ac outputs of ILFD is shown in Fig. 3. Under injection locked condition, the injection MOSFETs are turned on periodically, despite that the peak voltages at the gate and drain of 2 ( 5) are different, these two voltages are equalized at the maximum injection signal strength, because the injection MOSFETs are fully turned on. Between the two peak injection signal voltages, there is one peak output voltage at the gate/drain, thus the circuit operates as a divide-by-two circuit. Since the drain outputs of 2 and 5 are forced to operate differentially by the
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792
IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS, VOL. 17, NO. 11, NOVEMBER 2007
TABLE II COMPARISON OF INJECTION-LOCKED FREQUENCY DIVIDERS
Fig. 7. Measured phase noises of the free-running, injection-reference and in2.4 V, 1.2 V, and jection-locked of the ILFD at low band. f 4.93 GHz. Injection power 4 dBm.
=
=0
Vdd =
Vtune =
TABLE I PERFORMANCE SUMMARY
cross-coupled nMOS pair, the divider’s drain outputs are differential. IV. MEASUREMENT AND DISCUSSION The proposed ILFD is designed and implemented in the TSMC 0.18 m 1P6M CMOS process. Fig. 4 shows the photograph of the fabricated ILFD with chip area of 1.0 0.55 mm including the pad frame. Two symmetric octagonal inductors were designed using the top metal layer and the Agilent ADS Momentum EM simulator. The standard FR4 material is used to build test board for the Colpitts ILFD measurement. The die was glued directly onto the PC board with conductive materials, and aluminum wire bonds were used to connect all input and output pads. An Agilent E4407B spectrum analyzer and Agilent 83752B signal source were used to characterize the phase noise and locking range performance of the ILFD. Fig. 5 shows the measured tuning curve by varying the varactor tuning voltage at three Vinj. At Vinj 1.4 V, as the tuning voltage sweeps from 0 to 2.4 V, the oscillation frequency varies from 4.46 to 5.6 GHz, indicating a tuning range of 1.14 GHz. The tuning traces are slightly dependent on the injection bias. The current and power consumption of the differential Colpitts ILFD without buffers are 8.3 mA and 19.92 mW, respectively. Fig. 6 show the locking ranges of the differential Colpitts ILFD, when an injected signal of 0 dBm is applied, the locking range 2.4 V, of the ILFD is from 8.03 to 11.63 GHz while 1.4 V, 0.0, 1.2, 1.5, and 2.4 V, respectively. Fig. 7 shows the measured phase noises of the free-running, injection-reference and injection-locked. The phase noise of the free-running ILFD at 1-MHz offset is about 110.8 dBc/Hz at
the output frequency of 4.93 GHz. After the injection signal is applied to the ILFD, the phase noise of the ILFD becomes 135.4 dBc/Hz, while the phase noise of the injection reference is 125.9 dBc/Hz. The phase noise of the locked ILFD is lower than the free-running ILFD by 25 dB at 1-MHz offset frequency. The ILFD tracks the low phase noise of injection source, and shows a significant improvement over the free-running ILFD. Table I summarizes the circuit performance of the proposed Colpitts ILFD and Table II shows the comparison between our presented ILFD and previously published reports [7]. The ILFD prototype has a tuning range of 22.6% larger than 16% of the ILFD in [8]. It consumes a larger power, but the power can be reduced by changing the ILFD topology to use the nMOS-core oscillator rather than the implemented pMOS-core oscillator. V. CONCLUSION This letter demonstrates a differential Colpitts VCO can be used to design a wide locking range ILFD. The proposed ILFD was implemented in the TSMC 0.18 m CMOS process, and provides a wide locking range from 8.03 to 11.63 GHz at the incident signal power of 0 dBm. Similar to the cross-coupled VCO-based ILFD, this circuit is easy to implement because one MOS and an inductor are used to form an oscillator, which is then used to construct the whole divider. It is also potential for tanks. high frequency operation due to the use of ACKNOWLEDGMENT The authors would like to thank the Staff of the CIC for the chip fabrication and technical supports. REFERENCES [1] J. Craninckx and M. Steyaert, “A 1.75 GHz/3 V dual-modulus divideby-128/129 prescaler in 0.7-m CMOS,” in Proc. ESSCIRC, Sep. 1995, pp. 254–257. [2] Q. Huang and R. Rogenmoser, “Speed optimization of edge-triggered CMOS circuits for gigahertz single-phase clocks,” IEEE J. Solid-State Circuits, vol. 31, no. 3, pp. 456–463, Mar. 1996. [3] J. Lee and B. Razavi, “A 40 GHz frequency divider in 0.18-m CMOS technology,” in Symp. VLSI Circuits Tech. Dig., Jun. 2003, pp. 259–262. [4] M. Tiebout, “A CMOS direct injection-locked oscillator topology as high-frequency low-power frequency divider,” IEEE J. Solid-State Circuits, vol. 39, no. 7, pp. 1170–1174, Jul. 2004. [5] H. Wu and A. Hajimiri, “A 19 GHz 0.5 mW 0.35 m CMOS frequency divider with shunt-peaking locking-range enhancement,” in ISSCC Tech. Dig., Feb. 2001, pp. 412–413. [6] C.-Y. Cha and S.-G. Lee, “A complementary Colpitts oscillator in CMOS technology,” IEEE Trans. Microw. Theory Tech., vol. 53, no. 3, pp. 881–887, Mar. 2005. [7] J. Lee and B. Razavi, “A 40-GHz frequency divider in 0.18-m CMOS technology,” IEEE J. Solid-State Circuits, vol. 39, no. 4, pp. 594–601, Apr. 2004. [8] Y.-H. Chuang, S.-H. Lee, R.-H. Yen, S.-L. Jang, J.-F. Lee, and M.-H. Juang, “A wide locking range and low voltage CMOS direct injectionlocked frequency divider,” IEEE Microw. Wireless Compon. Lett., vol. 16, no. 5, pp. 299–301, May 2006.
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