Accurate Determination of Thermal Resistance of FETs - IEEE Xplore

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IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 53, NO. 1, JANUARY 2005

Accurate Determination of Thermal Resistance of FETs Ali Mohamed Darwish, Andrew J. Bayba, and H. Alfred Hung

Abstract—The accurate determination of the channel temperature in field-effect transistors (FETs) and monolithic microwave integrated circuits is critical for reliability. An original accurate closed-form expression is presented for the thermal resistance of multifinger FET structures. The model is based on the solution of Laplace’s equations in prolate spheroidal coordinates and elliptical cylinder coordinates. The model’s validity is verified by comparing the results with finite-element simulations, and experimental observations from liquid-crystal measurements and spatially resolved photoluminescence measurements. Very close agreement is observed in all cases. Index Terms—Field-effect transistors (FETs), power FETs, thermal effects, thermal resistance, reliability.

I. INTRODUCTION

Fig. 1.

T

HE reliability and performance of field-effect transistors (FETs) and monolithic microwave integrated circuits (MMICs), particularly for power devices, depend critically on the operating channel temperature. The maximum allowed channel temperature drives the design of the cooling system, device package, and maximum dc/RF power limitations. Therefore, an accurate estimate of channel temperature is highly desirable during the device (or circuit) design phase. Generally, the temperature behavior is governed by the three-dimensional (3-D) Laplace equation (1)

is the temperature at any point in space. Only where a few cases (e.g., concentric spheres, concentric cylinders, parallel plates) can be solved analytically in closed form [1], [2]. The rest are either intractable or result in infinite series summations [2]. Hence, numerical solutions are more commonly pursued and a number of simulators have been developed based on finite volume, finite difference, and finite-element techniques [3]–[6]. However, solving Laplace’s equation using numerical methods is not practical for most circuit designers for several reasons. First, they require great effort to define the problem and the boundary conditions; frequently, the solution does not converge. Second, they do not allow for device optimization with regards to thermal resistance. Third, the simulators required are generally expensive and are often unavailable to Manuscript received December 22, 2003; revised May 19, 2004. The authors are with the Army Research Laboratory, Adelphi, MD 20783 USA (e-mail: [email protected]; [email protected]; [email protected]). Digital Object Identifier 10.1109/TMTT.2004.839916

FET dimensions. Gate dimensions are L

2W

.

the MMIC designer. For these reasons, most designers rely on straightforward back-of-the-envelope formulas to estimate the channel temperature. These simplified formulas relate the device geometrical structure to the thermal resistance and are easy to understand and apply. The drawback of using these simple models is the inaccuracy of the result. In this paper, we present a closed-form expression for the channel temperature that is simple to use and is highly accurate (within 1%–2%) compared to the results of time-consuming and complex numerical analysis. It is excellent for visualization of temperature contours and gaining insight into the heat-flow problem. The formula takes into account the interaction of heat sources (i.e., gate fingers). The current two-step approach closely mimics the actual heat/temperature propagation. Most MMICs are designed using model-based microwave computer-aided design (CAD) programs such as Agilent Technologies’ ADS and Applied Wave Research’s Microwave Office. By presenting an accurate model, this study opens the door for the incorporation of accurate thermal calculation into model-based CAD programs and allows for the concurrent optimization of RF and thermal performance. This will accelerate the design cycle significantly. To our knowledge, this is the first accurate closed-form expression for thermal resistance for FET structures. The expression predicts the hottest temperature on the device. II. PROBLEM DEFINITION AND SOLUTION Consider an FET with a constant highly localized heat source (Fig. 1) on a substrate of thickness and constant thermal conductivity . The gate of the device represents a heat source with and width , and the gate–gate spacing is . The length

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DARWISH et al.: ACCURATE DETERMINATION OF THERMAL RESISTANCE OF FETs

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substrate area is assumed to be large enough that it has no effect (no constraining of heat) on the temperature, which is generally true in practice. The following boundary conditions are assumed: repre• constant heat flux over a surface area sents the dissipated power; ) are adia• all surfaces (except bottom of substrate batic, no heat flux allowed. The bottom of the substrate is an isothermal surface (constant temperature). The goal is to calculate the thermal resistance and, hence, find the maximum channel temperature (directly under the gate). To define various parameters, lets consider a parallel plate (capacitor-like) structure with thickness , cross-sectional area , thermal conductivity , heat flux , and temperature drop across the plates. The thermal resistance is (Fourier’s conduction law). The FET case is more complicated than the one above. The classical most popular method for calculating thermal resistance of an FET is an approximation based on Fourier’s conduction law. This approach makes the oversimplifying assumption that heat transfer is confined to a 45 wedge of material between the gate and base. The resulting equation is as follows:

Fig. 2. Cross section of an FET. Each FET is composed of multiple gate fingers. Finger spacing (gate pitch) is s. Downward heat propagation is considered through regions I and II.

(2) Although appreciated for its simplicity and ease of use, it has been shown to lack accuracy. Several modifications have been proposed to the above formula [7]–[9] to improve its accuracy for different special cases (square, circular disk, etc.). However, the accuracy of the simple models, when applied to the FET problem, remains an issue (percentage error 10%–50%) because the heat source is a thin long line, not a circle or a square. An analytical solution for the rectangular patch on a substrate and the circular patch on a cylinder is available in the form of an infinite series summation [10]–[12]. The exact solution is the sum of three infinite series with the last term consisting of two nested infinite summations. After using the infinite series solution for a few cases, one quickly realizes that convergence is very slow with tens of thousands of terms required to arrive at a reasonable answer, assuming numerical instabilities and errors are kept under control. Finally, earlier closed-form expressions based on transmission-line analogies have yielded results with 10%–20% errors [13]–[15]. Next, an accurate expression for the thermal resistance will be derived. In this study, detailed studies of the heat-flux behavior in FET structures were performed using finite-element simulations [5]. The results have led to the following observations and thermal model. • For an FET having multiple fingers, the outer fingers are the coolest. The fingers in the middle are the hottest. Since the middle fingers are surrounded to the left- and righthand side with numerous fingers, it is appropriate to assign adiabatic surfaces between each finger and the next, as indicated by the dashed lines in Fig. 2. In reality, only the neighboring fingers positioned within one (or two) substrate height contribute heat. This leads to an equivalent

Fig. 3. Temperature profile of an FET based on finite-element simulation. Front and side views are shown. In the side view, the elliptical nature of temperature contours is evident.

thermal model with an infinite number of fingers to the right- and left-hand side [14]. For a 100- m-thick substrate and 40- m gate pitch, only two (or four) fingers on each side contribute heat to the center finger. The rest have negligible effect. • Heat propagation can be divided into two regions I and II. In region I, heat propagates in a radial direction producing and (Fig. 2). In region isothermal lines such as II, heat propagates downward, producing isothermal lines such as and . This is motivated by observation of numerically generated temperature contours from finite-element simulations (see Fig. 3). In region I, heat propagates in an ellipsoidal manner. In region II, the propagation is similar to the elliptic cylinders case. Fig. 4 shows a 3-D view of the isothermal surfaces. The total thermal resistance equals the sum of the thermal resistances of regions I and II as follows: (3) Now, consider the thermal resistance in region I. In the prolate spheroidal coordinates, Laplace’s equation has an exact solution. Namely, the thermal resistance between two half-plane confocal ellipsoids: A, the inner, and B, the outer ellipsoid, with

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The remaining task is to relate to the gate spacing in light was selected, of the geometry in Fig. 5. Clearly, if then the thermal resistance would be underestimated. If was selected, then the resistance would be overestimated. Therefore, an appropriate estimate would be the geometric mean of . Thus, the two extremes

Hence,

Substituting back into (4), we obtain Fig. 4. 3-D view of isothermal surfaces for one gate finger. The ellipsoids represent region I isothermals and the two lower cylinders represent region II isothermals.

(5) where

Fig. 5. FET unit cell top view. Isothermal surfaces are modeled as ellipsoids. The gate is modeled as an ellipsoid with minor axis r and major axis r .

minor axes and , respectively, is

, respectively, and major axes

The equations have been rearranged and simplified. Now consider the thermal resistance of region II. The traditional method of assuming 45 spreading is not sufficiently accurate. From Fig. 3, it is observed that isothermal lines approach an elliptic cylinder shape. This suggests that elliptical cylinder coordinates may be the most suitable (Fig. 6). Given two half-plane confocal elliptical cylinders, i.e., and , with and , and major axes and , respecminor axes tively, and length , the thermal resistance between them is (6)

and where (4)

where provided

The critical task is to relate and to the current case. From Fig. 5, it is appropriate to select the dimensions of the inner ellipsoid, representing the heat source (i.e., gate finger) as follows:

Again, relating and to the current case is needed. From Fig. 4, it is reasonable to equate the dimensions of the inner ellipse (of region II) to the outer prolate ellipsoid of region I, and assign equal to

Hence, Given that approximated by

(e.g., 100 versus 0.25 m),

can be Next, we can relate to the substrate thickness with respect to the geometry in Fig. 6. It is expected that ,


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Fig. 6. FET side view. Isothermal lines in region II may be modeled as confocal elliptical cylinders.

where is a constant between 1 (an underestimate) and 2 (an overestimate). To determine the proper value for , one can av) or erage the two extremes (leading to evaluate a number of cases using numerical analysis and determine empirically. Pursuing the second approach, it is found . Substituting back into that, to a good approximation, (6), the thermal resistance is obtained as follows: (7) where

The equations have been rearranged and simplified. The above results can be summarized to evaluate the total thermal resistance (3) as

Fig. 7.

Temperature profile of isothermal surfaces.

is important to understand how the temperature drops with distance away from the channel. Consider the temperature profile at the cross section of the device (see Fig. 7). The cross section and at displacements shows isothermal surfaces and , respectively. Given a displacement , it is straightforward to calculate temperature at displacement from the source. The derived model above gives as , where is the total dissipated power. It is evident that (9) is the thermal resistance between the two where and (see Fig. 7). If the disisothermal surfaces at placement from the heat source is less than (thus, can be calculated as remaining in region I, Fig. 2), then

(8) (10) where and In the typical case, expression above, can be simplified as

and, hence, the

(11)

Again, the equations have been rearranged and simplified. The expression above gives the temperature at the center (hottest region) of the device. Experimentally, it is very difficult to measure the temperature right at the channel (at gate edge) due to the infinitesimal size of the gate. Thus, it is often measured close to the channel. It

This expression indicates that the temperature falls off logarithmically away from the source. Thus, if the temperature is measured a few micrometers away from the gate, it will be significantly different from that at the gate edge. Finally, it should be pointed out that, in deriving the current model, the following typical conditions were used and they need to be observed to ensure the accuracy of the result. and • The heat source is long and thin, i.e., (this is true in practical FET geometry). • There are at least two gate fingers on each side of the center gate finger in order to justify the adiabatic boundary conditions. Power FETs have multiple parallel fingers.

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Fig. 8. Dependence of thermal resistance on substrate thickness (t) for several practical thicknesses.

Fig. 9. Dependence of thermal resistance on substrate gate length (Lg ) for several practical situations.

Fig. 10. Dependence of thermal resistance on gatewidth (W g ) for several practical widths.

Fig. 11. Dependence of thermal resistance on gate pitch (s) for several practical spacings assuming t = 50 m.

• The metal thickness of gate, drain, and source is thin enough (less than 2 m) that heat conduction through them can be ignored. This is typically the case.

III. VERIFICATION OF MODEL The validity of the model will be verified using finite-element simulations (here) and experimental data (in Section IV). Numerical simulations have shown excellent agreement with experiment [16] in calculating thermal resistance, heat flux, and temperature. The widely used finite-element program ANSYS will be employed. We begin by analyzing classical cases with known exact solutions [17], [18] using ANSYS to verify the accuracy of the result. The mesh element shape selected is tetrahedral, and highly refined meshing is chosen to ensure the accuracy of the result (at the expense of computational speed).The current model is compared with ANSYS for the case of a GaAs FET structure (see Fig. 1). Very close agreement is observed (within 1%) between ANSYS and the solutions from the current model. Figs. 8–12 show the comparison of the thermal impedance and are changed, respectively. Close observaas tion of the curves shows that, on average, the error is within only 1%. The overall excellent agreement observed suggests

Fig. 12. Dependence of thermal resistance on gate pitch (s) for several practical spacings assuming t = 100 m.

that our model very closely mimics the actual heat flux and temperature propagation in the structure. The default values used m, in Figs. 8–12 (unless otherwise specified) are m, m, W/cm K, and m. Based on Figs. 8–12, Table I summarizes the average error, standard deviation of error, and maximum error observed (compared to ANSYS).


TABLE I ERROR STATISTICS FOR DIFFERENT METHODS OF ANALYSIS

The thermal resistance predicted by [15]1 and [19] is also plotted for reference. To produce a closed-form expression, [15] relied on a transmission-line analogy and [19] relied on extending the constant angle model (2). The approach used in [19] is based on amending a model that is too crude to yield accurate results. The transmission-line approach used in [15] suffers from several inaccuracies, including the approximation of the fringe capacitance, the averaging of temperature across the heat source, and the approximation of elliptic integrals with a closed-form expression. It should be pointed out that, in all of the analysis above, the thermal conductivity was assumed to be constant. In reality, is temperature dependent. This can be easily taken into account analytically without any approximation using Kirchhoff’s transformation [20] once the temperature-independent thermal resistance is calculated using the model above. For example, consider the case of GaAs where the thermal conductivity was curve fitted from 300 to 600 K (with 0.8% to 1.3% error) as [21] W/cm K

(12)

Once the thermal resistance is calculated from (8), then the temperature dependence of can be taken into account by applying Kirchhoff’s transformation on (12), which gives (13) where

is the base plate temperature in degrees kelvin. IV. COMPARISON WITH EXPERIMENT

The submicrometer gate-length dimension makes it very challenging to accurately measure the temperature right at the channel (FET gate edge). Nonetheless, several measurements with varying spatial resolutions have been reported using spatially resolved photoluminescence [22] and liquid crystal techniques [23]. In calculating the channel temperature, the nonlinearity of the thermal conductivity needs to be taken into account to arrive at the correct answer. The semiconductor material in the examples below is GaAs; however, the model works equally well for silicon-based devices. A. Liquid-Crystal Measurements Consider the liquid-crystal measurements reported in [23]. The parameters of the GaAs MESFET power amplifier are as follows: • gate–gate spacing (20 m); • gate length (0.5 m); 1It

should be noted that there is a typo in [15, eq. (1)].

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• gatewidth (62.5 m); • number of gates (80); • substrate thickness (100 m); • base plate temperature (125 C); • power input (0.0625 W/gate). Using (8) and taking into account the temperature-dependent nature of semiconductors (13), the resulting channel temperature equals K. The measured and calculated channel temperatures (in Celsius) are as follows. C • Measured • Calculated C Remarkable agreement is observed. The predicted temperature C using the same according to Cooke’s model [15] is temperature dependent thermal conductivity. The prediction of the current model provides a closer match to the measured data. In addition to the above, [23] reported channel temperature measurements on GaAs “dense array” amplifiers with: • gate–gate spacing (26 m); • gate length (0.5 m); • gatewidth (37.5 m); • number of gates (10); • substrate thickness (100 m); • base plate temperature (125 C); • power input 0.8 W/mm (or 0.03 W/gate). The measured and our calculated channel temperatures are as follows. C • Measured • Calculated C Very close agreement is observed. The predicted temperature according to Cooke’s model [15] is C using the same temperature dependent thermal conductivity. Again, the prediction of the current model provides a closer match to the experimental results. B. Spatially Resolved Photoluminescence Measurements Consider the spatially resolved photoluminescence measurements reported in [22] on GaAs pseudomorphic high electron-mobility transistor (pHEMT) devices. This is a relatively accurate approach to measuring the channel temperature without perturbing the device. Basically, a laser is focused into a small spot (approximately 1 m in diameter) on the gate finger. The resulting photoluminescence gives a direct measure of the bandgap of the material. Knowing the dependence of the bandgap on temperature, the channel temperature can be measured with great resolution. In this case, the laser was focused approximately 0.75 m away from the gate finger. The following device parameters were used: • gate–gate spacing (30 m); • gate length (0.25 m); • gatewidth (50 m); • number of gates (4); • substrate thickness (100 m); • thermal conductivity (0.47 W/K cm); • power input, variable. Applying (13) with the above parameters and variable input power, Fig. 13 is obtained. Equation (11) was applied with

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Fig. 13. Comparison between calculated and measured channel temperature increase [22]. The dashed line represents the model proposed by [15].

m to account for the 0.75- m displacement from the heat source. Again, close agreement is observed between our model and measured channel temperature.

V. CONCLUSION An accurate closed-form model based on device geometry, configuration, and material parameters has been derived for the thermal resistance of an FET structure. Excellent agreement has been obtained between the model and extensive numerical simulations across various variables (substrate thickness, gate pitch, gatewidth, and gate length). The model has been verified by comparing it to spatially resolved photoluminescence and liquid-crystal measurements. The examples that have been presented in this paper are based on GaAs FETs. However, the formulation applies equally well (this has been investigated by finite-element simulations) to other semiconductor materials such as Si and SiGe. The closed-form model can be readily used by device and MMIC designers to optimize the device geometry and configuration to achieve the desired electrical and thermal performance without invoking complex, time-consuming, and often nonconverging numerical techniques. Incorporating the result into model-based CAD programs can be easily done (as equations), thereby allowing the concurrent optimization of RF and thermal performance and accelerating the design cycle.

REFERENCES [1] R. Remsburg, Thermal Design of Electronic Equipment. New York: CRC, 2001. [2] J. C. Jaeger and H. S. Carslaw, Conduction of Heat in Solids, 2nd ed. Oxford, U.K.: Oxford Univ. Press, 1959. [3] WinTherm 7.0, ThermoAnalytics Inc., Calumet, MI, 2002. [4] Thermal Analysis System 6.1, Harvard Thermal Inc., Harvard, MA, 1997. [5] ANSYS 7.0, ANSYS Inc., Canonsburg, PA, 2002.

[6] FEMLAB 3.0, COMSOL Inc., Burlington, MA, 2003. [7] A. Pacelli, P. Palestri, and M. Mastrapasqua, “Compact modeling of thermal resistance in bipolar transistors on bulk and SOI substrates,” IEEE Trans. Electron Devices, vol. 49, no. 6, pp. 1027–1033, Jun. 2002. [8] R. Joy and E. S. Schlig, “Thermal properties of very fast transistors,” IEEE Trans. Electron Devices, vol. ED-17, pp. 586–594, 1970. [9] S. Song, S. Lee, and V. Au, “Closed-form equation for thermal constriction/spreading resistances with variable resistance boundary condition,” in Int. Electronics Packaging Soc. Conf., 1994, pp. 111–121. [10] R. D. Linstead and R. J. Surty, “Steady state junction temperature of semiconductor chips,” IEEE Trans. Electron Devices, vol. ED-19, no. 1, pp. 41–44, Jan. 1972. [11] D. Kennedy, “Spreading resistance in cylindrical semiconductor devices,” J. Appl. Phys., vol. 31, pp. 1490–1497, 1960. [12] R. David, “Computerized thermal analysis of hybrid circuits,” IEEE Trans. Parts, Hybrids, Packag., vol. PHP-13, no. 3, pp. 283–290, Sep. 1977. [13] H. F. Cooke, “FET’s and bipolars differ when the going gets hot,” Microwaves, pp. 55–61, 1978. [14] J. V. DiLorenzo and D. D. Khandelwal, GaAs FET Principles and Technology. Dedham, MA: Artech House, 1982. [15] H. F. Cooke, “Precise technique finds FET thermal resistance,” Microwaves RF, pp. 85–87, 1986. [16] M. Kuball, J. M. Hayes, M. J. Uren, T. Martin, J. C. Birbeck, R. S. Balmer, and B. T. Hughes, “Measurement of temperature in active highpower AlGaN/GaN HFETs using Raman spectroscopy,” IEEE Electron Device Lett., vol. 23, no. 1, pp. 7–9, Jan. 2002. [17] Handbook of Heat Transfer, 3rd ed., McGraw-Hill, Washington, DC, 1998. [18] D. Pitts, Schaum’s Outline of Theory and Problems of Heat Transfer, 2nd ed. Washington, DC: McGraw-Hill, 1997. [19] F. Masana, “A closed form solution of junction to substrate thermal resistance in semiconductor chips,” IEEE Trans. Comp., Packag., Manufact. Technol. A, vol. 19, no. 4, pp. 539–545, Dec. 1996. [20] W. B. Joyce, “Thermal resistance of heat sinks with temperature-dependent conductivity,” Solid State Electron., vol. 18, pp. 321–322, 1975. [21] Purdue Univ., West Lafayette, IN, CINDAS Semiconduct. Properties Rep., 1988. [22] J. P. Landesman, E. Martin, and P. Braun, “Temperature distribution in power GaAs field effect transistors using spatially resolved photoluminescence mapping,” in Proc. 7th Int. Physical and Failure Analysis of Integrated Circuits, 1999, pp. 185–190. [23] J. Wright, B. W. Marks, and K. D. Decker, “Modeling of MMIC devices for determining MMIC channel temperatures during life tests,” in 7th IEEE Semiconductor Thermal Measurement, Modeling, and Management Symp., 1991, pp. 131–139.

Ali Mohamed Darwish was born in Manhattan, KS, in 1969. He received the B.Sc. and M.S. degrees (with honors) in electrical engineering from the University of Maryland at College Park, in 1990 and 1992, respectively, and the Ph.D. degree from the Massachusetts Institute of Technology (MIT), Cambridge, in 1996. In 1990, he joined COMSAT Laboratories, where he conducted the experimental work for his M.S. thesis. In 1992, he was a Research Assistant with the Optics and Quantum Electronics Group, MIT. In 1997, he cofounded Amcom Communications Inc., a leading supplier of high-power microwave devices. In May 2003, he joined the RF Electronics Division, Army Research Laboratory, Adelphi, MD, where he currently conducts research on wide-bandgap materials (GaN), thermal analysis of active devices, and novel MMIC concepts. Dr. Darwish was the recipient of a National Science Foundation (NSF) Fellowship.


Andrew J. Bayba received the B.S. degree from the University of Arizona, Tucson, in 1985, and the Masters degree from The Johns Hopkins University, Baltimore, MD, in 1992, both in mechanical engineering. For over 18 years, he has been a Mechanical Engineer with the Army Research Laboratory, Adelphi, MD, where, for the last five years, he has focused on packaging and heat removal of high-power-density RF Devices. Mr. Bayba is a Professional Engineer in the state of Maryland. He is a member of the American Society of Mechanical Engineers (ASME).

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H. Alfred Hung received the S.B. degree in electrical engineering from the Massachusetts Institute of Technology (MIT), Cambridge, in 1968, and the M.S. and Ph.D. degrees from Cornell University, Ithaca, NY, in 1970 and 1974, respectively. He is currently with the Army Research Laboratory, Adelphi, MD, where he is involved with the development of new electronic devices, sensors, and multifunction RF subsystems. His research interests include wide-bandgap and compound semiconductors and RF microelectromechanical systems (MEMS) technologies for millimeter-wave and mixed-signal integrated circuits. He is the Army lead in a number of research programs. He previously held various research, functional, and program management positions with General Technical Services, TRW, Raytheon, and COMSAT Laboratories. He was also an Adjunct Professor with the George Washington University. He has been involved in the areas of GaAs and InP HEMTs and HBTs, related MMICs, and subsystems integration, as well as optical/microwave techniques for wireless and radar systems, and terrestrial and satellite communications. He has authored or coauthored over 100 publications in journals, book chapters, and conference proceedings. He is on the Editorial Boards of technical journals. Dr. Hung has also been active with IEEE conference technical committees.